diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
| commit | 25e1b1c1f5f4e0ad3976c88998161700135f4aae (patch) | |
| tree | 36e668b99a36c3dfcfefc157d7bd6b102b8f8af6 /tests/long/fs/10.linux-boot/ref | |
| parent | 7e711c98f8fcd949b9430bbf243d60348d0ef28b (diff) | |
| download | gem5-25e1b1c1f5f4e0ad3976c88998161700135f4aae.tar.xz | |
stats: Update stats for cache, crossbar and DRAM changes
This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.
Needless to say, almost every regression is affected.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref')
28 files changed, 43235 insertions, 42396 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt index 2bd7abaa8..b894ed506 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt @@ -1,109 +1,109 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.887179 # Number of seconds simulated -sim_ticks 1887179292000 # Number of ticks simulated -final_tick 1887179292000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.886196 # Number of seconds simulated +sim_ticks 1886195993000 # Number of ticks simulated +final_tick 1886195993000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 271909 # Simulator instruction rate (inst/s) -host_op_rate 271909 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9140545464 # Simulator tick rate (ticks/s) -host_mem_usage 373988 # Number of bytes of host memory used -host_seconds 206.46 # Real time elapsed on the host -sim_insts 56138893 # Number of instructions simulated -sim_ops 56138893 # Number of ops (including micro ops) simulated +host_inst_rate 256659 # Simulator instruction rate (inst/s) +host_op_rate 256659 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8626071053 # Simulator tick rate (ticks/s) +host_mem_usage 374008 # Number of bytes of host memory used +host_seconds 218.66 # Real time elapsed on the host +sim_insts 56121694 # Number of instructions simulated +sim_ops 56121694 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 1052544 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24858944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1049728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24850240 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25912448 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1052544 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1052544 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7556224 # Number of bytes written to this memory -system.physmem.bytes_written::total 7556224 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 16446 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388421 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25900928 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1049728 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1049728 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7553600 # Number of bytes written to this memory +system.physmem.bytes_written::total 7553600 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 16402 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388285 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 404882 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 118066 # Number of write requests responded to by this memory -system.physmem.num_writes::total 118066 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 557734 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13172540 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 404702 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 118025 # Number of write requests responded to by this memory +system.physmem.num_writes::total 118025 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 556532 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13174792 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 509 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13730782 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 557734 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 557734 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4003978 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4003978 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4003978 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 557734 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13172540 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13731833 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 556532 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 556532 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4004674 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4004674 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4004674 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 556532 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13174792 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 509 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17734760 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 404882 # Number of read requests accepted -system.physmem.writeReqs 159618 # Number of write requests accepted -system.physmem.readBursts 404882 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 159618 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25905920 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6528 # Total number of bytes read from write queue -system.physmem.bytesWritten 8528320 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25912448 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10215552 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 102 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 26335 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 157 # Number of requests that are neither read nor write +system.physmem.bw_total::total 17736507 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 404702 # Number of read requests accepted +system.physmem.writeReqs 118025 # Number of write requests accepted +system.physmem.readBursts 404702 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 118025 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25894272 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6656 # Total number of bytes read from write queue +system.physmem.bytesWritten 7551808 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25900928 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7553600 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 104 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 41706 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 25487 # Per bank write bursts -system.physmem.perBankRdBursts::1 25681 # Per bank write bursts -system.physmem.perBankRdBursts::2 25706 # Per bank write bursts -system.physmem.perBankRdBursts::3 25753 # Per bank write bursts -system.physmem.perBankRdBursts::4 25164 # Per bank write bursts -system.physmem.perBankRdBursts::5 25107 # Per bank write bursts -system.physmem.perBankRdBursts::6 24789 # Per bank write bursts -system.physmem.perBankRdBursts::7 24544 # Per bank write bursts -system.physmem.perBankRdBursts::8 25200 # Per bank write bursts -system.physmem.perBankRdBursts::9 25299 # Per bank write bursts -system.physmem.perBankRdBursts::10 25393 # Per bank write bursts -system.physmem.perBankRdBursts::11 24991 # Per bank write bursts -system.physmem.perBankRdBursts::12 24525 # Per bank write bursts -system.physmem.perBankRdBursts::13 25570 # Per bank write bursts -system.physmem.perBankRdBursts::14 25834 # Per bank write bursts +system.physmem.perBankRdBursts::1 25728 # Per bank write bursts +system.physmem.perBankRdBursts::2 25822 # Per bank write bursts +system.physmem.perBankRdBursts::3 25769 # Per bank write bursts +system.physmem.perBankRdBursts::4 25085 # Per bank write bursts +system.physmem.perBankRdBursts::5 25016 # Per bank write bursts +system.physmem.perBankRdBursts::6 24650 # Per bank write bursts +system.physmem.perBankRdBursts::7 24524 # Per bank write bursts +system.physmem.perBankRdBursts::8 25293 # Per bank write bursts +system.physmem.perBankRdBursts::9 25190 # Per bank write bursts +system.physmem.perBankRdBursts::10 25398 # Per bank write bursts +system.physmem.perBankRdBursts::11 24986 # Per bank write bursts +system.physmem.perBankRdBursts::12 24522 # Per bank write bursts +system.physmem.perBankRdBursts::13 25563 # Per bank write bursts +system.physmem.perBankRdBursts::14 25828 # Per bank write bursts system.physmem.perBankRdBursts::15 25737 # Per bank write bursts -system.physmem.perBankWrBursts::0 8901 # Per bank write bursts -system.physmem.perBankWrBursts::1 8465 # Per bank write bursts -system.physmem.perBankWrBursts::2 9022 # Per bank write bursts -system.physmem.perBankWrBursts::3 8725 # Per bank write bursts -system.physmem.perBankWrBursts::4 8062 # Per bank write bursts -system.physmem.perBankWrBursts::5 8096 # Per bank write bursts -system.physmem.perBankWrBursts::6 7614 # Per bank write bursts -system.physmem.perBankWrBursts::7 7482 # Per bank write bursts -system.physmem.perBankWrBursts::8 8269 # Per bank write bursts -system.physmem.perBankWrBursts::9 7671 # Per bank write bursts -system.physmem.perBankWrBursts::10 8104 # Per bank write bursts -system.physmem.perBankWrBursts::11 7830 # Per bank write bursts -system.physmem.perBankWrBursts::12 8200 # Per bank write bursts -system.physmem.perBankWrBursts::13 9100 # Per bank write bursts -system.physmem.perBankWrBursts::14 8920 # Per bank write bursts -system.physmem.perBankWrBursts::15 8794 # Per bank write bursts +system.physmem.perBankWrBursts::0 7820 # Per bank write bursts +system.physmem.perBankWrBursts::1 7688 # Per bank write bursts +system.physmem.perBankWrBursts::2 8067 # Per bank write bursts +system.physmem.perBankWrBursts::3 7737 # Per bank write bursts +system.physmem.perBankWrBursts::4 7196 # Per bank write bursts +system.physmem.perBankWrBursts::5 7011 # Per bank write bursts +system.physmem.perBankWrBursts::6 6646 # Per bank write bursts +system.physmem.perBankWrBursts::7 6392 # Per bank write bursts +system.physmem.perBankWrBursts::8 7401 # Per bank write bursts +system.physmem.perBankWrBursts::9 6804 # Per bank write bursts +system.physmem.perBankWrBursts::10 7278 # Per bank write bursts +system.physmem.perBankWrBursts::11 6972 # Per bank write bursts +system.physmem.perBankWrBursts::12 7052 # Per bank write bursts +system.physmem.perBankWrBursts::13 8008 # Per bank write bursts +system.physmem.perBankWrBursts::14 7983 # Per bank write bursts +system.physmem.perBankWrBursts::15 7942 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 50 # Number of times write queue was full causing retry -system.physmem.totGap 1887170570500 # Total gap between requests +system.physmem.numWrRetry 17 # Number of times write queue was full causing retry +system.physmem.totGap 1886187226500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 404882 # Read request sizes (log2) +system.physmem.readPktSize::6 404702 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 159618 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 402496 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2204 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 68 # What read queue length does an incoming req see +system.physmem.writePktSize::6 118025 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 402327 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2193 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 66 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -148,201 +148,188 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1093 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1663 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5882 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5366 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5673 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5897 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5801 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6757 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6471 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 667 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1390 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1888 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1841 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1859 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1976 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 2613 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 2770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 744 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 78 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64763 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 531.696185 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 324.957517 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 415.417041 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14664 22.64% 22.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11016 17.01% 39.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5432 8.39% 48.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3093 4.78% 52.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2464 3.80% 56.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1908 2.95% 59.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1486 2.29% 61.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1430 2.21% 64.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 23270 35.93% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64763 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4906 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 82.503669 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 3015.330482 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 4903 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1481 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1905 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6090 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6388 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7084 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8808 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7466 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8358 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6976 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5590 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5494 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 37 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 63594 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 525.931377 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 320.890659 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 414.200803 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14460 22.74% 22.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10997 17.29% 40.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4933 7.76% 47.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3625 5.70% 53.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2479 3.90% 57.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1827 2.87% 60.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1418 2.23% 62.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1367 2.15% 64.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22488 35.36% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63594 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5295 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 76.408121 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2902.928186 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5292 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4906 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4906 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.161639 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.352681 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 61.394400 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 4666 95.11% 95.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 49 1.00% 96.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 4 0.08% 96.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 5 0.10% 96.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 7 0.14% 96.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 1 0.02% 96.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 2 0.04% 96.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 7 0.14% 96.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 21 0.43% 97.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 22 0.45% 97.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 9 0.18% 97.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 10 0.20% 97.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 3 0.06% 97.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 2 0.04% 98.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 2 0.04% 98.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 3 0.06% 98.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 2 0.04% 98.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 2 0.04% 98.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 3 0.06% 98.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 19 0.39% 98.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 9 0.18% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 5 0.10% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 13 0.26% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 3 0.06% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::400-415 1 0.02% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::432-447 1 0.02% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::448-463 3 0.06% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::464-479 5 0.10% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 3 0.06% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 8 0.16% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 2 0.04% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 1 0.02% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 3 0.06% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::560-575 1 0.02% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::656-671 1 0.02% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::672-687 3 0.06% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::704-719 1 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::720-735 3 0.06% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::816-831 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4906 # Writes before turning the bus around for reads -system.physmem.totQLat 2145475500 # Total ticks spent queuing -system.physmem.totMemAccLat 9735100500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2023900000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5300.35 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5295 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5295 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.284608 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.797942 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.673735 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4676 88.31% 88.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 227 4.29% 92.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 77 1.45% 94.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 16 0.30% 94.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 14 0.26% 94.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 6 0.11% 94.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 7 0.13% 94.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 9 0.17% 95.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 7 0.13% 95.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 34 0.64% 95.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 171 3.23% 99.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 10 0.19% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 1 0.02% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 1 0.02% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 5 0.09% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 3 0.06% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 1 0.02% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 2 0.04% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 4 0.08% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 4 0.08% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 8 0.15% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 1 0.02% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 2 0.04% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 7 0.13% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5295 # Writes before turning the bus around for reads +system.physmem.totQLat 2213284250 # Total ticks spent queuing +system.physmem.totMemAccLat 9799496750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2022990000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5470.33 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24050.35 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 24220.33 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.73 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.52 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 4.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.73 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 5.41 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.35 # Average write queue length when enqueuing -system.physmem.readRowHits 363650 # Number of row buffer hits during reads -system.physmem.writeRowHits 109622 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.84 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 82.25 # Row buffer hit rate for writes -system.physmem.avgGap 3343083.38 # Average gap between requests -system.physmem.pageHitRate 87.96 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 239016960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 130416000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1577401800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 430058160 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 123261212880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 60604997490 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1079143932000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1265387035290 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.518464 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1795039940480 # Time in different power states -system.physmem_0.memoryStateTime::REF 63016980000 # Time in different power states +system.physmem.avgWrQLen 24.19 # Average write queue length when enqueuing +system.physmem.readRowHits 363516 # Number of row buffer hits during reads +system.physmem.writeRowHits 95485 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.85 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.90 # Row buffer hit rate for writes +system.physmem.avgGap 3608360.06 # Average gap between requests +system.physmem.pageHitRate 87.83 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 233845920 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 127594500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1576231800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 379449360 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 123197134320 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 60326866845 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1078799265750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1264640388495 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.471373 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1794467110750 # Time in different power states +system.physmem_0.memoryStateTime::REF 62984220000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 29120110770 # Time in different power states +system.physmem_0.memoryStateTime::ACT 28744633000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 250591320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 136731375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1579882200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 433434240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 123261212880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 61665698520 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1078213500750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1265541051285 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.600071 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1793490285480 # Time in different power states -system.physmem_1.memoryStateTime::REF 63016980000 # Time in different power states +system.physmem_1.actEnergy 246924720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 134730750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1579632600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 385171200 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 123197134320 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 61494025635 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1077775442250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1264813061475 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.562919 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1792762379750 # Time in different power states +system.physmem_1.memoryStateTime::REF 62984220000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30669779520 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30449364000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 15009390 # Number of BP lookups -system.cpu.branchPred.condPredicted 13017239 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 373223 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9937559 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5199343 # Number of BTB hits +system.cpu.branchPred.lookups 15004879 # Number of BP lookups +system.cpu.branchPred.condPredicted 13013312 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 375549 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10036322 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5207234 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 52.320122 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 808599 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 32086 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 51.883887 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 808293 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 31321 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9244571 # DTB read hits -system.cpu.dtb.read_misses 17796 # DTB read misses +system.cpu.dtb.read_hits 9242647 # DTB read hits +system.cpu.dtb.read_misses 17811 # DTB read misses system.cpu.dtb.read_acv 211 # DTB read access violations -system.cpu.dtb.read_accesses 766653 # DTB read accesses -system.cpu.dtb.write_hits 6387559 # DTB write hits -system.cpu.dtb.write_misses 2314 # DTB write misses +system.cpu.dtb.read_accesses 766734 # DTB read accesses +system.cpu.dtb.write_hits 6385782 # DTB write hits +system.cpu.dtb.write_misses 2309 # DTB write misses system.cpu.dtb.write_acv 160 # DTB write access violations -system.cpu.dtb.write_accesses 298430 # DTB write accesses -system.cpu.dtb.data_hits 15632130 # DTB hits -system.cpu.dtb.data_misses 20110 # DTB misses +system.cpu.dtb.write_accesses 298407 # DTB write accesses +system.cpu.dtb.data_hits 15628429 # DTB hits +system.cpu.dtb.data_misses 20120 # DTB misses system.cpu.dtb.data_acv 371 # DTB access violations -system.cpu.dtb.data_accesses 1065083 # DTB accesses -system.cpu.itb.fetch_hits 4016391 # ITB hits -system.cpu.itb.fetch_misses 6902 # ITB misses -system.cpu.itb.fetch_acv 656 # ITB acv -system.cpu.itb.fetch_accesses 4023293 # ITB accesses +system.cpu.dtb.data_accesses 1065141 # DTB accesses +system.cpu.itb.fetch_hits 4016387 # ITB hits +system.cpu.itb.fetch_misses 6834 # ITB misses +system.cpu.itb.fetch_acv 689 # ITB acv +system.cpu.itb.fetch_accesses 4023221 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -355,39 +342,39 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 180739367 # number of cpu cycles simulated +system.cpu.numCycles 180216793 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56138893 # Number of instructions committed -system.cpu.committedOps 56138893 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2514465 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 5513 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 3593619217 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 3.219504 # CPI: cycles per instruction -system.cpu.ipc 0.310607 # IPC: instructions per cycle +system.cpu.committedInsts 56121694 # Number of instructions committed +system.cpu.committedOps 56121694 # Number of ops (including micro ops) committed +system.cpu.discardedOps 2519198 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 5577 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 3592175193 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 3.211179 # CPI: cycles per instruction +system.cpu.ipc 0.311412 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211474 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74790 40.94% 40.94% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl +system.cpu.kern.inst.hwrei 211471 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74788 40.94% 40.94% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 133 0.07% 41.01% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1901 1.04% 42.05% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105866 57.95% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182688 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73423 49.32% 49.32% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 105864 57.95% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182686 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73421 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::21 133 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1901 1.28% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73423 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148878 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1834553179500 97.21% 97.21% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 80704500 0.00% 97.22% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 676355500 0.04% 97.25% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 51868058000 2.75% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1887178297500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_good::31 73422 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148877 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1833775262000 97.22% 97.22% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 81341000 0.00% 97.23% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 679703500 0.04% 97.26% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 51658703500 2.74% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1886195010000 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981722 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.693547 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814930 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.693550 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814934 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -426,112 +413,112 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4172 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175529 91.23% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6805 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal::swpipl 175525 91.23% 93.43% # number of callpals executed +system.cpu.kern.callpal::rdps 6804 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rti 5126 2.66% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5127 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192412 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5872 # number of protection mode switches +system.cpu.kern.callpal::total 192408 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5868 # number of protection mode switches system.cpu.kern.mode_switch::user 1739 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2092 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches system.cpu.kern.mode_good::kernel 1907 system.cpu.kern.mode_good::user 1739 system.cpu.kern.mode_good::idle 168 -system.cpu.kern.mode_switch_good::kernel 0.324762 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.324983 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080306 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.393074 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 36563872500 1.94% 1.94% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 4128201000 0.22% 2.16% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1846486214000 97.84% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.080114 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.393034 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 36513483500 1.94% 1.94% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 4123557000 0.22% 2.15% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1845557959500 97.85% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4173 # number of times the context was actually changed -system.cpu.tickCycles 84425844 # Number of cycles that the object actually ticked -system.cpu.idleCycles 96313523 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 1395605 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.981737 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 13777018 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1396117 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 9.868097 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 90985250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.981737 # Average occupied blocks per requestor +system.cpu.tickCycles 84408299 # Number of cycles that the object actually ticked +system.cpu.idleCycles 95808494 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 1395428 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.981685 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 13773051 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1395940 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 9.866506 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 90850500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.981685 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999964 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999964 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63673578 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63673578 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7816852 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7816852 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5578390 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5578390 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 182745 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 182745 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 198996 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 198996 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13395242 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13395242 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13395242 # number of overall hits -system.cpu.dcache.overall_hits::total 13395242 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1201883 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1201883 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 573228 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 573228 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17271 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17271 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1775111 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1775111 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1775111 # number of overall misses -system.cpu.dcache.overall_misses::total 1775111 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 33009196500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 33009196500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22459728804 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22459728804 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 231661750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 231661750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 55468925304 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 55468925304 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 55468925304 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 55468925304 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9018735 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9018735 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6151618 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6151618 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200016 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200016 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 198996 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 198996 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15170353 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15170353 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15170353 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15170353 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133265 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.133265 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093183 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.093183 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086348 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086348 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.117012 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.117012 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.117012 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.117012 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27464.567267 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 27464.567267 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39181.143985 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39181.143985 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13413.337386 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13413.337386 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31248.144653 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31248.144653 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31248.144653 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31248.144653 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 63660654 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63660654 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7815445 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7815445 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5575784 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5575784 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 182800 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 182800 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 198989 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 198989 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13391229 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13391229 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13391229 # number of overall hits +system.cpu.dcache.overall_hits::total 13391229 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1201797 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1201797 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 574153 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 574153 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17210 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17210 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1775950 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1775950 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1775950 # number of overall misses +system.cpu.dcache.overall_misses::total 1775950 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32866409500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32866409500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22318082000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22318082000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 230873000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 230873000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 55184491500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 55184491500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 55184491500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 55184491500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9017242 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9017242 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6149937 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6149937 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200010 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200010 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 198989 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 198989 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15167179 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15167179 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15167179 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15167179 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133278 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.133278 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093359 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.093359 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086046 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086046 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.117092 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.117092 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.117092 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.117092 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27347.721371 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 27347.721371 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38871.314789 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38871.314789 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13415.049390 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13415.049390 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31073.223627 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31073.223627 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31073.223627 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31073.223627 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -540,129 +527,129 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 838424 # number of writebacks -system.cpu.dcache.writebacks::total 838424 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 127263 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 127263 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 268960 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 268960 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 838228 # number of writebacks +system.cpu.dcache.writebacks::total 838228 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 127318 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 127318 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 269861 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 269861 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 396223 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 396223 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 396223 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 396223 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074620 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1074620 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304268 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304268 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17268 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17268 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1378888 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1378888 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1378888 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1378888 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable -system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9619 # number of WriteReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::total 9619 # number of WriteReq MSHR uncacheable -system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16549 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 16549 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29346931250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 29346931250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11233755093 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11233755093 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 205574750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 205574750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 40580686343 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 40580686343 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40580686343 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 40580686343 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1433335500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1433335500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2017328500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2017328500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3450664000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3450664000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119154 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119154 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049461 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049461 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086333 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086333 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090894 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.090894 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090894 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.090894 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27309.124388 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27309.124388 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36920.593335 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36920.593335 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11904.954251 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11904.954251 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29430.009067 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29430.009067 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29430.009067 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29430.009067 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 206830.519481 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 206830.519481 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 209723.308036 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 209723.308036 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 208511.934256 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 208511.934256 # average overall mshr uncacheable latency +system.cpu.dcache.demand_mshr_hits::cpu.data 397179 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 397179 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 397179 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 397179 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074479 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1074479 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304292 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304292 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17207 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17207 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1378771 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1378771 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1378771 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1378771 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6934 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadReq_mshr_uncacheable::total 6934 # number of ReadReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9621 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 9621 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16555 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 16555 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29864669500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 29864669500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11367980000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11367980000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 213500500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 213500500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41232649500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 41232649500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41232649500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 41232649500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1451443000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1451443000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2042111500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2042111500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3493554500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3493554500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119158 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119158 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049479 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049479 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086031 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086031 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090905 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.090905 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090905 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.090905 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27794.558572 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27794.558572 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37358.786955 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37358.786955 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12407.770094 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12407.770094 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29905.364633 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29905.364633 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29905.364633 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29905.364633 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209322.613210 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209322.613210 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212255.638707 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212255.638707 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 211027.151918 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 211027.151918 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1458527 # number of replacements -system.cpu.icache.tags.tagsinuse 509.440030 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 18957390 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1459038 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 12.993075 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 33850944250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.440030 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.995000 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.995000 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1459012 # number of replacements +system.cpu.icache.tags.tagsinuse 509.459740 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 18968780 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1459523 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 12.996561 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 33609211500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.459740 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.995039 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.995039 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 401 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 21875821 # Number of tag accesses -system.cpu.icache.tags.data_accesses 21875821 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 18957393 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 18957393 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 18957393 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 18957393 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 18957393 # number of overall hits -system.cpu.icache.overall_hits::total 18957393 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1459214 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1459214 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1459214 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1459214 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1459214 # number of overall misses -system.cpu.icache.overall_misses::total 1459214 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 20146503654 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 20146503654 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 20146503654 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 20146503654 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 20146503654 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 20146503654 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 20416607 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 20416607 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 20416607 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 20416607 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 20416607 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 20416607 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071472 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.071472 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.071472 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.071472 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.071472 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.071472 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13806.407870 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13806.407870 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13806.407870 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13806.407870 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13806.407870 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13806.407870 # average overall miss latency +system.cpu.icache.tags.tag_accesses 21888175 # Number of tag accesses +system.cpu.icache.tags.data_accesses 21888175 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 18968783 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 18968783 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 18968783 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 18968783 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 18968783 # number of overall hits +system.cpu.icache.overall_hits::total 18968783 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1459696 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1459696 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1459696 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1459696 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1459696 # number of overall misses +system.cpu.icache.overall_misses::total 1459696 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 20145975000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 20145975000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 20145975000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 20145975000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 20145975000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 20145975000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 20428479 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 20428479 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 20428479 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 20428479 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 20428479 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 20428479 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071454 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.071454 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.071454 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.071454 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.071454 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.071454 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13801.486748 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13801.486748 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13801.486748 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13801.486748 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13801.486748 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13801.486748 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -671,135 +658,141 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1459214 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1459214 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1459214 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1459214 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1459214 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1459214 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17950426346 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 17950426346 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17950426346 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 17950426346 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17950426346 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 17950426346 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071472 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071472 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071472 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.071472 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071472 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.071472 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12301.435119 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12301.435119 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12301.435119 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12301.435119 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12301.435119 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12301.435119 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1459696 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1459696 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1459696 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1459696 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1459696 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1459696 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18686279000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 18686279000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18686279000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 18686279000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18686279000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 18686279000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071454 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071454 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071454 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.071454 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071454 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.071454 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12801.486748 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12801.486748 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12801.486748 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12801.486748 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12801.486748 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12801.486748 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 339383 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65314.882486 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2982705 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 404543 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 7.373023 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 6335415750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 54442.497002 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 5830.422847 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 5041.962637 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.830727 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088965 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.076934 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996626 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65160 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 228 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1415 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5172 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2814 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55531 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994263 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 30258908 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 30258908 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 1442704 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 819672 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2262376 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 838424 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 838424 # number of Writeback hits +system.cpu.l2cache.tags.replacements 339196 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65318.328839 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4996938 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 404358 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 12.357708 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 6286116000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 54387.720391 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 5865.311953 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 5065.296495 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.829891 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.089498 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.077290 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996679 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1416 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5169 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2809 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55538 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 46373741 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 46373741 # Number of data accesses +system.cpu.l2cache.Writeback_hits::writebacks 838228 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 838228 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187612 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187612 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1442704 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1007284 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2449988 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1442704 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1007284 # number of overall hits -system.cpu.l2cache.overall_hits::total 2449988 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 16447 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 272188 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 288635 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 18 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 18 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 116662 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 116662 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 16447 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 388850 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 405297 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 16447 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 388850 # number of overall misses -system.cpu.l2cache.overall_misses::total 405297 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1321749250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 19747496500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 21069245750 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 254997 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 254997 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8955533859 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 8955533859 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1321749250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 28703030359 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 30024779609 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1321749250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 28703030359 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 30024779609 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1459151 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1091860 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2551011 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 838424 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 838424 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 22 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 22 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 304274 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 304274 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1459151 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1396134 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2855285 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1459151 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1396134 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2855285 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.011272 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.249288 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.113145 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.818182 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.818182 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383411 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.383411 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.011272 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.278519 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.141946 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.011272 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.278519 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.141946 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80364.154557 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72550.944568 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 72996.156911 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14166.500000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14166.500000 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76764.789383 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76764.789383 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80364.154557 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73815.173869 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74080.932277 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80364.154557 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73815.173869 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74080.932277 # average overall miss latency +system.cpu.l2cache.ReadExReq_hits::cpu.data 187768 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 187768 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1443233 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1443233 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 819477 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 819477 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1443233 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1007245 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2450478 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1443233 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1007245 # number of overall hits +system.cpu.l2cache.overall_hits::total 2450478 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 16 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 16 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 116534 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 116534 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16403 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 16403 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 272179 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 272179 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 16403 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 388713 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 405116 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 16403 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 388713 # number of overall misses +system.cpu.l2cache.overall_misses::total 405116 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 253000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 253000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8935872000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 8935872000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1324497500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 1324497500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 19726651500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 19726651500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1324497500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 28662523500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 29987021000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1324497500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 28662523500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 29987021000 # number of overall miss cycles +system.cpu.l2cache.Writeback_accesses::writebacks 838228 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 838228 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 20 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 20 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 304302 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 304302 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1459636 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1459636 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1091656 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1091656 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1459636 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1395958 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2855594 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1459636 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1395958 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2855594 # number of overall (read+write) accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.800000 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.800000 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382955 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.382955 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.011238 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.011238 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.249327 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.249327 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.011238 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.278456 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.141868 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.011238 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.278456 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.141868 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15812.500000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15812.500000 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76680.385124 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76680.385124 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80747.271841 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80747.271841 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 72476.757942 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 72476.757942 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80747.271841 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73736.982041 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74020.826134 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80747.271841 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73736.982041 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74020.826134 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -808,115 +801,126 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 76554 # number of writebacks -system.cpu.l2cache.writebacks::total 76554 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16447 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 272188 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 288635 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 18 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 18 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116662 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 116662 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 16447 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 388850 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 405297 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 16447 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 388850 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 405297 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9619 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9619 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16549 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16549 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1115769250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16346505000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17462274250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 421016 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 421016 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7497021141 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7497021141 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1115769250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23843526141 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 24959295391 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1115769250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23843526141 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 24959295391 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1336297500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1336297500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1892281000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1892281000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3228578500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3228578500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.011272 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.249288 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.113145 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.818182 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.818182 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383411 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383411 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011272 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278519 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.141946 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011272 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278519 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.141946 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67840.290022 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60055.935603 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60499.503698 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 23389.777778 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 23389.777778 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64262.751719 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64262.751719 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67840.290022 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61318.056168 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61582.729186 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67840.290022 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61318.056168 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61582.729186 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 192827.922078 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 192827.922078 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 196723.256056 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 196723.256056 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 195092.059943 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 195092.059943 # average overall mshr uncacheable latency +system.cpu.l2cache.writebacks::writebacks 76513 # number of writebacks +system.cpu.l2cache.writebacks::total 76513 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 317 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 317 # number of CleanEvict MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 16 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 16 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116534 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 116534 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16403 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16403 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 272179 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 272179 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 16403 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 388713 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 405116 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 16403 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 388713 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 405116 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6934 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6934 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9621 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9621 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16555 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16555 # number of overall MSHR uncacheable misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 431000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 431000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7770532000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7770532000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1160467500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1160467500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 17006826000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 17006826000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1160467500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 24777358000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 25937825500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1160467500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 24777358000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25937825500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1364748500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1364748500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1931469000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1931469000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3296217500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3296217500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.800000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.800000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382955 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382955 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011238 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011238 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249327 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249327 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011238 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278456 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.141868 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011238 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278456 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.141868 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 26937.500000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26937.500000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66680.385124 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66680.385124 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70747.271841 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70747.271841 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 62483.975619 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 62483.975619 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70747.271841 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63742.035898 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64025.675362 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70747.271841 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63742.035898 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64025.675362 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196819.800981 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196819.800981 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200755.534768 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200755.534768 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199107.067351 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199107.067351 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2558177 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2558144 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9619 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9619 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 838424 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41594 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 22 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 22 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304274 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304274 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 6934 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2558426 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9621 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9621 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 956270 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2277118 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 20 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 20 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 304302 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304302 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1459696 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091829 # Transaction distribution system.cpu.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2918365 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3663990 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6582355 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93385664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143064988 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 236450652 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 41986 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3752110 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.011132 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.104918 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4377747 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4219297 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8597044 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93416704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143041221 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 236457925 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 422839 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 6149292 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.068727 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.252990 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3710343 98.89% 98.89% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 41767 1.11% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5726669 93.13% 93.13% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 422623 6.87% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3752110 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2698405000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.snoop_fanout::total 6149292 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3706373000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2192449154 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2189771045 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2195119407 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2105677995 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -930,44 +934,43 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 7103 # Transaction distribution -system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51171 # Transaction distribution -system.iobus.trans_dist::WriteResp 9619 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5094 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 7107 # Transaction distribution +system.iobus.trans_dist::ReadResp 7107 # Transaction distribution +system.iobus.trans_dist::WriteReq 51173 # Transaction distribution +system.iobus.trans_dist::WriteResp 51173 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5104 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6674 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33098 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33110 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116548 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20376 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 116560 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20416 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 44316 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 44357 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2705924 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 4705000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2705965 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 4712000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -981,7 +984,7 @@ system.iobus.reqLayer23.occupancy 13484000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 5167000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) @@ -989,23 +992,23 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 242104189 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 216063756 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23479000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 23489000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42024001 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.302269 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.294607 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1729988196000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.302269 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.081392 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.081392 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1729988854000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.294607 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.080913 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.080913 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1013,49 +1016,49 @@ system.iocache.tags.tag_accesses 375525 # Nu system.iocache.tags.data_accesses 375525 # Number of data accesses system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21714383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21714383 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8768796805 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 8768796805 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21714383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21714383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21714383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21714383 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21637883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21637883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4907200873 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4907200873 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21637883 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21637883 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21637883 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21637883 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125516.664740 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125516.664740 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 211031.883062 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 211031.883062 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125516.664740 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125516.664740 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 73108 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125074.468208 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125074.468208 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118097.826170 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118097.826170 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 125074.468208 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125074.468208 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 125074.468208 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125074.468208 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 9982 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.323983 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1063,83 +1066,85 @@ system.iocache.writebacks::writebacks 41512 # nu system.iocache.writebacks::total 41512 # number of writebacks system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12562383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12562383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6608090807 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6608090807 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12562383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12562383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12562383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12562383 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12987883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12987883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2829600873 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2829600873 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12987883 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12987883 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12987883 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12987883 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72614.930636 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 159031.834978 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 159031.834978 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72614.930636 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72614.930636 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 75074.468208 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68097.826170 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68097.826170 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 75074.468208 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 75074.468208 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 295738 # Transaction distribution -system.membus.trans_dist::ReadResp 295722 # Transaction distribution -system.membus.trans_dist::WriteReq 9619 # Transaction distribution -system.membus.trans_dist::WriteResp 9619 # Transaction distribution -system.membus.trans_dist::Writeback 118066 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 159 # Transaction distribution -system.membus.trans_dist::UpgradeResp 159 # Transaction distribution -system.membus.trans_dist::ReadExReq 116521 # Transaction distribution -system.membus.trans_dist::ReadExResp 116521 # Transaction distribution +system.membus.trans_dist::ReadReq 6934 # Transaction distribution +system.membus.trans_dist::ReadResp 295673 # Transaction distribution +system.membus.trans_dist::WriteReq 9621 # Transaction distribution +system.membus.trans_dist::WriteResp 9621 # Transaction distribution +system.membus.trans_dist::Writeback 118025 # Transaction distribution +system.membus.trans_dist::CleanEvict 262175 # Transaction distribution +system.membus.trans_dist::UpgradeReq 156 # Transaction distribution +system.membus.trans_dist::UpgradeResp 156 # Transaction distribution +system.membus.trans_dist::ReadExReq 116394 # Transaction distribution +system.membus.trans_dist::ReadExResp 116394 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 288755 # Transaction distribution system.membus.trans_dist::BadAddressError 16 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33098 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 886877 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33110 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920007 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1044811 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44316 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30810944 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30855260 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36172316 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181774 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1306591 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44357 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30796800 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30841157 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33498885 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 433 # Total snoops (count) -system.membus.snoop_fanout::samples 581705 # Request fanout histogram +system.membus.snoop_fanout::samples 843789 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 581705 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 843789 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 581705 # Request fanout histogram -system.membus.reqLayer0.occupancy 29342000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 843789 # Request fanout histogram +system.membus.reqLayer0.occupancy 29576000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1229889311 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1318697936 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) system.membus.reqLayer2.occupancy 20500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2160670093 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2160007596 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 42495999 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 72031934 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index dad37454b..e5b1b4540 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,123 +1,123 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.904438 # Number of seconds simulated -sim_ticks 1904437574000 # Number of ticks simulated -final_tick 1904437574000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.907980 # Number of seconds simulated +sim_ticks 1907980084000 # Number of ticks simulated +final_tick 1907980084000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 149880 # Simulator instruction rate (inst/s) -host_op_rate 149880 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5044505517 # Simulator tick rate (ticks/s) -host_mem_usage 380636 # Number of bytes of host memory used -host_seconds 377.53 # Real time elapsed on the host -sim_insts 56583768 # Number of instructions simulated -sim_ops 56583768 # Number of ops (including micro ops) simulated +host_inst_rate 144634 # Simulator instruction rate (inst/s) +host_op_rate 144633 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4918211693 # Simulator tick rate (ticks/s) +host_mem_usage 381420 # Number of bytes of host memory used +host_seconds 387.94 # Real time elapsed on the host +sim_insts 56109384 # Number of instructions simulated +sim_ops 56109384 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 878144 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24662016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 107328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 745792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 744000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24138496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 236608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1227584 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26394240 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 878144 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 107328 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 985472 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7983616 # Number of bytes written to this memory -system.physmem.bytes_written::total 7983616 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13721 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 385344 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1677 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 11653 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26347648 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 744000 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 236608 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 980608 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7952896 # Number of bytes written to this memory +system.physmem.bytes_written::total 7952896 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 11625 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 377164 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3697 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 19181 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 412410 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 124744 # Number of write requests responded to by this memory -system.physmem.num_writes::total 124744 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 461104 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12949763 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 56357 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 391607 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 504 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13859336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 461104 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 56357 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 517461 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4192112 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4192112 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4192112 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 461104 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12949763 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 56357 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 391607 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 504 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18051448 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 412410 # Number of read requests accepted -system.physmem.writeReqs 166296 # Number of write requests accepted -system.physmem.readBursts 412410 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 166296 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26387648 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6592 # Total number of bytes read from write queue -system.physmem.bytesWritten 9015296 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26394240 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10642944 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 103 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 25417 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4739 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25681 # Per bank write bursts -system.physmem.perBankRdBursts::1 26031 # Per bank write bursts -system.physmem.perBankRdBursts::2 26262 # Per bank write bursts -system.physmem.perBankRdBursts::3 25929 # Per bank write bursts -system.physmem.perBankRdBursts::4 25778 # Per bank write bursts -system.physmem.perBankRdBursts::5 25597 # Per bank write bursts -system.physmem.perBankRdBursts::6 26273 # Per bank write bursts -system.physmem.perBankRdBursts::7 25295 # Per bank write bursts -system.physmem.perBankRdBursts::8 25970 # Per bank write bursts -system.physmem.perBankRdBursts::9 26150 # Per bank write bursts -system.physmem.perBankRdBursts::10 25721 # Per bank write bursts -system.physmem.perBankRdBursts::11 25208 # Per bank write bursts -system.physmem.perBankRdBursts::12 25640 # Per bank write bursts -system.physmem.perBankRdBursts::13 25768 # Per bank write bursts +system.physmem.num_reads::total 411682 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 124264 # Number of write requests responded to by this memory +system.physmem.num_writes::total 124264 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 389941 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12651335 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 124010 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 643395 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 503 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13809184 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 389941 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 124010 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 513951 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4168228 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4168228 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4168228 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 389941 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12651335 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 124010 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 643395 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17977412 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 411682 # Number of read requests accepted +system.physmem.writeReqs 124264 # Number of write requests accepted +system.physmem.readBursts 411682 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 124264 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26340672 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6976 # Total number of bytes read from write queue +system.physmem.bytesWritten 7951552 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26347648 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7952896 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 109 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 45002 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25908 # Per bank write bursts +system.physmem.perBankRdBursts::1 25789 # Per bank write bursts +system.physmem.perBankRdBursts::2 26010 # Per bank write bursts +system.physmem.perBankRdBursts::3 25614 # Per bank write bursts +system.physmem.perBankRdBursts::4 25643 # Per bank write bursts +system.physmem.perBankRdBursts::5 25797 # Per bank write bursts +system.physmem.perBankRdBursts::6 25922 # Per bank write bursts +system.physmem.perBankRdBursts::7 25550 # Per bank write bursts +system.physmem.perBankRdBursts::8 25897 # Per bank write bursts +system.physmem.perBankRdBursts::9 25701 # Per bank write bursts +system.physmem.perBankRdBursts::10 25484 # Per bank write bursts +system.physmem.perBankRdBursts::11 25508 # Per bank write bursts +system.physmem.perBankRdBursts::12 25696 # Per bank write bursts +system.physmem.perBankRdBursts::13 25817 # Per bank write bursts system.physmem.perBankRdBursts::14 25547 # Per bank write bursts -system.physmem.perBankRdBursts::15 25457 # Per bank write bursts -system.physmem.perBankWrBursts::0 9358 # Per bank write bursts -system.physmem.perBankWrBursts::1 9077 # Per bank write bursts -system.physmem.perBankWrBursts::2 9200 # Per bank write bursts -system.physmem.perBankWrBursts::3 8756 # Per bank write bursts -system.physmem.perBankWrBursts::4 8419 # Per bank write bursts -system.physmem.perBankWrBursts::5 8251 # Per bank write bursts -system.physmem.perBankWrBursts::6 9072 # Per bank write bursts -system.physmem.perBankWrBursts::7 8046 # Per bank write bursts -system.physmem.perBankWrBursts::8 8692 # Per bank write bursts -system.physmem.perBankWrBursts::9 8978 # Per bank write bursts -system.physmem.perBankWrBursts::10 8574 # Per bank write bursts -system.physmem.perBankWrBursts::11 8968 # Per bank write bursts -system.physmem.perBankWrBursts::12 8555 # Per bank write bursts -system.physmem.perBankWrBursts::13 9260 # Per bank write bursts -system.physmem.perBankWrBursts::14 8896 # Per bank write bursts -system.physmem.perBankWrBursts::15 8762 # Per bank write bursts +system.physmem.perBankRdBursts::15 25690 # Per bank write bursts +system.physmem.perBankWrBursts::0 7970 # Per bank write bursts +system.physmem.perBankWrBursts::1 7556 # Per bank write bursts +system.physmem.perBankWrBursts::2 7711 # Per bank write bursts +system.physmem.perBankWrBursts::3 7606 # Per bank write bursts +system.physmem.perBankWrBursts::4 7633 # Per bank write bursts +system.physmem.perBankWrBursts::5 7951 # Per bank write bursts +system.physmem.perBankWrBursts::6 7934 # Per bank write bursts +system.physmem.perBankWrBursts::7 7815 # Per bank write bursts +system.physmem.perBankWrBursts::8 8060 # Per bank write bursts +system.physmem.perBankWrBursts::9 8044 # Per bank write bursts +system.physmem.perBankWrBursts::10 7565 # Per bank write bursts +system.physmem.perBankWrBursts::11 7446 # Per bank write bursts +system.physmem.perBankWrBursts::12 7634 # Per bank write bursts +system.physmem.perBankWrBursts::13 8000 # Per bank write bursts +system.physmem.perBankWrBursts::14 7754 # Per bank write bursts +system.physmem.perBankWrBursts::15 7564 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 50 # Number of times write queue was full causing retry -system.physmem.totGap 1904433039500 # Total gap between requests +system.physmem.numWrRetry 18 # Number of times write queue was full causing retry +system.physmem.totGap 1907975777500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 412410 # Read request sizes (log2) +system.physmem.readPktSize::6 411682 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 166296 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 317706 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 39027 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 30801 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 24670 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 80 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 124264 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 317784 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 38583 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 29989 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 25130 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 71 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see @@ -158,200 +158,204 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4340 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5378 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5892 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5750 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5976 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6391 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7775 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7719 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9990 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7735 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7720 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1084 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1301 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 880 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1700 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1725 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1711 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1699 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1843 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1941 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 2112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 2607 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 2803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1758 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1391 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 490 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 92 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 66375 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 533.371902 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 326.032515 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 416.702689 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14841 22.36% 22.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11366 17.12% 39.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5910 8.90% 48.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2909 4.38% 52.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2416 3.64% 56.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1747 2.63% 59.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1634 2.46% 61.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1312 1.98% 63.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 24240 36.52% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 66375 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5272 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 78.206942 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2891.855588 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5269 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1631 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3880 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4994 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5583 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 10048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9014 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7398 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8967 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 46 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 65129 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 526.524774 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 320.940318 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 415.518091 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14691 22.56% 22.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11476 17.62% 40.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5283 8.11% 48.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3332 5.12% 53.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2563 3.94% 57.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1696 2.60% 59.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1442 2.21% 62.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1386 2.13% 64.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 23260 35.71% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65129 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5620 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 73.233096 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2814.761745 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5617 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5272 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5272 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 26.719272 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.348145 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 60.306865 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 5026 95.33% 95.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 55 1.04% 96.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 6 0.11% 96.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 3 0.06% 96.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 6 0.11% 96.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 3 0.06% 96.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 3 0.06% 96.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 6 0.11% 96.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 24 0.46% 97.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 10 0.19% 97.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 9 0.17% 97.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 16 0.30% 98.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 2 0.04% 98.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 3 0.06% 98.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 3 0.06% 98.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 4 0.08% 98.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 1 0.02% 98.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 4 0.08% 98.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 6 0.11% 98.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 11 0.21% 98.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 13 0.25% 98.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 7 0.13% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 10 0.19% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 3 0.06% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::400-415 1 0.02% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::416-431 1 0.02% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::464-479 2 0.04% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 11 0.21% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 3 0.06% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 2 0.04% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 1 0.02% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 5 0.09% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::560-575 3 0.06% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::640-655 1 0.02% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::672-687 2 0.04% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::688-703 2 0.04% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::720-735 3 0.06% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::896-911 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5272 # Writes before turning the bus around for reads -system.physmem.totQLat 4111304500 # Total ticks spent queuing -system.physmem.totMemAccLat 11842060750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2061535000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9971.46 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5620 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5620 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.107295 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.769658 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.265728 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4863 86.53% 86.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 151 2.69% 89.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 190 3.38% 92.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 20 0.36% 92.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 26 0.46% 93.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 52 0.93% 94.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 14 0.25% 94.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 7 0.12% 94.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 2 0.04% 94.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 2 0.04% 94.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 6 0.11% 94.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 7 0.12% 95.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 8 0.14% 95.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 5 0.09% 95.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 3 0.05% 95.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 3 0.05% 95.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 8 0.14% 95.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 8 0.14% 95.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 26 0.46% 96.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 16 0.28% 96.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 144 2.56% 98.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 12 0.21% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.04% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.04% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.02% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 4 0.07% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.04% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.04% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.02% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 3 0.05% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.02% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 6 0.11% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.02% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 3 0.05% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.02% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 7 0.12% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 2 0.04% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 1 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 5 0.09% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-235 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-243 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5620 # Writes before turning the bus around for reads +system.physmem.totQLat 4128600500 # Total ticks spent queuing +system.physmem.totMemAccLat 11845594250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2057865000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10031.27 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28721.46 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.86 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.73 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.86 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 5.59 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28781.27 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.81 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.17 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.81 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.17 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.15 # Data bus utilization in percentage +system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.27 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.00 # Average write queue length when enqueuing -system.physmem.readRowHits 371693 # Number of row buffer hits during reads -system.physmem.writeRowHits 115102 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.15 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.70 # Row buffer hit rate for writes -system.physmem.avgGap 3290847.23 # Average gap between requests -system.physmem.pageHitRate 88.00 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 251551440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 137255250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1613398800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 454759920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 124388181840 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 57693505320 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1092050470500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1276589123070 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.325620 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1816548038492 # Time in different power states -system.physmem_0.memoryStateTime::REF 63593140000 # Time in different power states +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 2.21 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.72 # Average write queue length when enqueuing +system.physmem.readRowHits 370844 # Number of row buffer hits during reads +system.physmem.writeRowHits 99842 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.10 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.35 # Row buffer hit rate for writes +system.physmem.avgGap 3560014.96 # Average gap between requests +system.physmem.pageHitRate 87.84 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 245019600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 133691250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1608188400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 402589440 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 124619576640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 57486510675 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1094357699250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1278853275255 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.267627 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1820391723000 # Time in different power states +system.physmem_0.memoryStateTime::REF 63711440000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 24290182758 # Time in different power states +system.physmem_0.memoryStateTime::ACT 23872193000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 250137720 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 136483875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1602190200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 457604640 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 124388181840 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 57661176915 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1092078837000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1276574612190 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.317995 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1816597555496 # Time in different power states -system.physmem_1.memoryStateTime::REF 63593140000 # Time in different power states +system.physmem_1.actEnergy 247287600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 134928750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1601652000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 402194160 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 124619576640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 57648050955 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1094215997250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1278869687355 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.276229 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1820158780750 # Time in different power states +system.physmem_1.memoryStateTime::REF 63711440000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 24242350004 # Time in different power states +system.physmem_1.memoryStateTime::ACT 24103898000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu0.branchPred.lookups 16050181 # Number of BP lookups -system.cpu0.branchPred.condPredicted 14012515 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 321303 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 9883832 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 5384164 # Number of BTB hits +system.cpu0.branchPred.lookups 11788808 # Number of BP lookups +system.cpu0.branchPred.condPredicted 10301623 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 235567 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 7623393 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4144660 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 54.474459 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 809394 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 17633 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 54.367655 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 590548 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 12472 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9185685 # DTB read hits -system.cpu0.dtb.read_misses 31794 # DTB read misses -system.cpu0.dtb.read_acv 464 # DTB read access violations -system.cpu0.dtb.read_accesses 674724 # DTB read accesses -system.cpu0.dtb.write_hits 5856177 # DTB write hits -system.cpu0.dtb.write_misses 6642 # DTB write misses -system.cpu0.dtb.write_acv 308 # DTB write access violations -system.cpu0.dtb.write_accesses 220970 # DTB write accesses -system.cpu0.dtb.data_hits 15041862 # DTB hits -system.cpu0.dtb.data_misses 38436 # DTB misses -system.cpu0.dtb.data_acv 772 # DTB access violations -system.cpu0.dtb.data_accesses 895694 # DTB accesses -system.cpu0.itb.fetch_hits 1413849 # ITB hits -system.cpu0.itb.fetch_misses 27924 # ITB misses -system.cpu0.itb.fetch_acv 522 # ITB acv -system.cpu0.itb.fetch_accesses 1441773 # ITB accesses +system.cpu0.dtb.read_hits 7021210 # DTB read hits +system.cpu0.dtb.read_misses 28922 # DTB read misses +system.cpu0.dtb.read_acv 549 # DTB read access violations +system.cpu0.dtb.read_accesses 680178 # DTB read accesses +system.cpu0.dtb.write_hits 4516223 # DTB write hits +system.cpu0.dtb.write_misses 6969 # DTB write misses +system.cpu0.dtb.write_acv 383 # DTB write access violations +system.cpu0.dtb.write_accesses 234540 # DTB write accesses +system.cpu0.dtb.data_hits 11537433 # DTB hits +system.cpu0.dtb.data_misses 35891 # DTB misses +system.cpu0.dtb.data_acv 932 # DTB access violations +system.cpu0.dtb.data_accesses 914718 # DTB accesses +system.cpu0.itb.fetch_hits 1192769 # ITB hits +system.cpu0.itb.fetch_misses 29243 # ITB misses +system.cpu0.itb.fetch_acv 632 # ITB acv +system.cpu0.itb.fetch_accesses 1222012 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -364,595 +368,598 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 115311619 # number of cpu cycles simulated +system.cpu0.numCycles 94258709 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 26308115 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 70327057 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 16050181 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6193558 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 81501759 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1071492 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 564 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 28477 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1405877 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 453989 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 199 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 8110639 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 231031 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 110234726 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.637976 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.938280 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 18560589 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 53027757 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 11788808 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4735208 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 69979824 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 806070 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 422 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 25803 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 1456351 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 296845 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 178 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 6342869 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 170274 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 90723047 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.584501 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.854201 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 97059343 88.05% 88.05% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 844439 0.77% 88.81% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1832569 1.66% 90.48% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 778966 0.71% 91.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2587591 2.35% 93.53% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 590382 0.54% 94.07% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 655112 0.59% 94.66% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 842956 0.76% 95.42% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 5043368 4.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 80634947 88.88% 88.88% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 672953 0.74% 89.62% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1448081 1.60% 91.22% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 584574 0.64% 91.86% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2111688 2.33% 94.19% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 463915 0.51% 94.70% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 450869 0.50% 95.20% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 614781 0.68% 95.88% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3741239 4.12% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 110234726 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.139190 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.609887 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 21404943 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 78060690 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 8511786 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1756604 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 500702 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 518589 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 35397 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 61724420 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 110442 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 500702 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 22241314 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 51035680 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 18875449 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9340106 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 8241473 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 59592973 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 194522 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2018079 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 142482 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 4327383 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 39868450 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 72416227 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 72269697 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 136600 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 34997307 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4871143 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1466604 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 213801 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 12439963 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9310742 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6112181 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1342468 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 951279 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 53110388 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1887245 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 52243998 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 50112 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6621677 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 2924940 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1298251 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 110234726 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.473934 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.210494 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 90723047 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.125069 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.562577 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 14977569 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 67686915 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6257157 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1423439 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 377966 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 370983 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 25389 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 46677806 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 79994 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 377966 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 15660908 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 46083028 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 14369152 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6948168 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 7283823 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 45068314 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 191995 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 1547824 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 115834 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 4229403 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 30289226 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 55138176 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 55047778 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 82793 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 26689501 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 3599717 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1126936 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 168790 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 10038208 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7066684 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 4739993 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1073845 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 760534 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 40346624 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1418133 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 39715880 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 51531 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 4979263 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 2318512 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 978590 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 90723047 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.437771 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.168840 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 88757561 80.52% 80.52% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 9303542 8.44% 88.96% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3888317 3.53% 92.48% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2690563 2.44% 94.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2829805 2.57% 97.49% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1399486 1.27% 98.76% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 891988 0.81% 99.57% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 364157 0.33% 99.90% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 109307 0.10% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 74240349 81.83% 81.83% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 7278177 8.02% 89.85% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3014429 3.32% 93.18% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2002130 2.21% 95.38% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2057446 2.27% 97.65% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1059416 1.17% 98.82% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 709655 0.78% 99.60% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 273899 0.30% 99.90% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 87546 0.10% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 110234726 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 90723047 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 184539 19.02% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 463483 47.76% 66.78% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 322428 33.22% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 128942 17.20% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 362987 48.42% 65.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 257779 34.38% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 4481 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 35873428 68.67% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 57323 0.11% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 30345 0.06% 68.84% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.84% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.84% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.84% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 2234 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9533353 18.25% 87.09% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5924969 11.34% 98.43% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 817865 1.57% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3788 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 27155018 68.37% 68.38% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 40485 0.10% 68.48% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.48% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 25259 0.06% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 7282480 18.34% 86.89% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 4576355 11.52% 98.41% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 630612 1.59% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 52243998 # Type of FU issued -system.cpu0.iq.rate 0.453068 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 970450 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.018575 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 215148578 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 61357419 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 50866456 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 594706 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 279378 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 273817 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 52889876 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 320091 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 579148 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 39715880 # Type of FU issued +system.cpu0.iq.rate 0.421350 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 749708 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.018877 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 170597233 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 46586090 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 38643243 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 358812 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 172505 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 165745 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 40269961 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 191839 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 469267 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1102308 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 4274 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 17841 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 488268 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 864378 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3380 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 14864 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 401917 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18769 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 362429 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 11804 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 365714 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 500702 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 47770294 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 975694 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 58389413 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 117266 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9310742 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6112181 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1666926 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 38737 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 734939 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 17841 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 161758 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 354564 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 516322 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 51738600 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9239994 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 505398 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 377966 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 43619498 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 675796 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 44202753 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 88904 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7066684 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 4739993 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1257449 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 23012 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 538948 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 14864 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 117466 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 265776 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 383242 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 39342618 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 7067139 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 373261 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3391780 # number of nop insts executed -system.cpu0.iew.exec_refs 15116199 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8225133 # Number of branches executed -system.cpu0.iew.exec_stores 5876205 # Number of stores executed -system.cpu0.iew.exec_rate 0.448685 # Inst execution rate -system.cpu0.iew.wb_sent 51252595 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 51140273 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 26435135 # num instructions producing a value -system.cpu0.iew.wb_consumers 36676301 # num instructions consuming a value +system.cpu0.iew.exec_nop 2437996 # number of nop insts executed +system.cpu0.iew.exec_refs 11599884 # number of memory reference insts executed +system.cpu0.iew.exec_branches 6171265 # Number of branches executed +system.cpu0.iew.exec_stores 4532745 # Number of stores executed +system.cpu0.iew.exec_rate 0.417390 # Inst execution rate +system.cpu0.iew.wb_sent 38908729 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 38808988 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 20149850 # num instructions producing a value +system.cpu0.iew.wb_consumers 27578035 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.443496 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.720769 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.411728 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.730649 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6957791 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 588994 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 471378 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 109009912 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.470894 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.405994 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 5183738 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 439543 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 349838 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 89803768 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.433386 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.354442 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 90895183 83.38% 83.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7166067 6.57% 89.96% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 3956975 3.63% 93.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2029230 1.86% 95.45% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1623676 1.49% 96.94% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 582620 0.53% 97.47% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 429957 0.39% 97.87% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 432812 0.40% 98.26% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1893392 1.74% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 76032999 84.67% 84.67% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5542678 6.17% 90.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2869062 3.19% 94.03% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1578965 1.76% 95.79% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1284314 1.43% 97.22% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 412798 0.46% 97.68% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 324191 0.36% 98.04% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 314453 0.35% 98.39% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1444308 1.61% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 109009912 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 51332073 # Number of instructions committed -system.cpu0.commit.committedOps 51332073 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 89803768 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 38919724 # Number of instructions committed +system.cpu0.commit.committedOps 38919724 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13832347 # Number of memory references committed -system.cpu0.commit.loads 8208434 # Number of loads committed -system.cpu0.commit.membars 200823 # Number of memory barriers committed -system.cpu0.commit.branches 7767218 # Number of branches committed -system.cpu0.commit.fp_insts 270478 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 47526784 # Number of committed integer instructions. -system.cpu0.commit.function_calls 660195 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 2960587 5.77% 5.77% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 33426068 65.12% 70.88% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 56116 0.11% 70.99% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.99% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 30044 0.06% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 2234 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 8409257 16.38% 87.44% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 5629902 10.97% 98.41% # Class of committed instruction -system.cpu0.commit.op_class_0::IprAccess 817865 1.59% 100.00% # Class of committed instruction +system.cpu0.commit.refs 10540382 # Number of memory references committed +system.cpu0.commit.loads 6202306 # Number of loads committed +system.cpu0.commit.membars 144405 # Number of memory barriers committed +system.cpu0.commit.branches 5839773 # Number of branches committed +system.cpu0.commit.fp_insts 162063 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 36166381 # Number of committed integer instructions. +system.cpu0.commit.function_calls 471449 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 2138002 5.49% 5.49% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 25394964 65.25% 70.74% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 39484 0.10% 70.84% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.84% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 24801 0.06% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 6346711 16.31% 87.22% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 4343267 11.16% 98.38% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 630612 1.62% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 51332073 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1893392 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 165216916 # The number of ROB reads -system.cpu0.rob.rob_writes 117798939 # The number of ROB writes -system.cpu0.timesIdled 506110 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 5076893 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3693292578 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 48375955 # Number of Instructions Simulated -system.cpu0.committedOps 48375955 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 2.383656 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.383656 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.419524 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.419524 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 67964697 # number of integer regfile reads -system.cpu0.int_regfile_writes 37032803 # number of integer regfile writes -system.cpu0.fp_regfile_reads 135608 # number of floating regfile reads -system.cpu0.fp_regfile_writes 136877 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1822860 # number of misc regfile reads -system.cpu0.misc_regfile_writes 821150 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 1283357 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.867544 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 10588066 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1283792 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.247493 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 26416000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.867544 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988023 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.988023 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 435 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 435 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.849609 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 56965784 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 56965784 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6531926 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6531926 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3699481 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3699481 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 164387 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 164387 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 189172 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 189172 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10231407 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10231407 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10231407 # number of overall hits -system.cpu0.dcache.overall_hits::total 10231407 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1592146 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1592146 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1718300 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1718300 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20836 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20836 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2478 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2478 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3310446 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3310446 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3310446 # number of overall misses -system.cpu0.dcache.overall_misses::total 3310446 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 39294199360 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 39294199360 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 76231824796 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 76231824796 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 326020750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 326020750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 20798848 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 20798848 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 115526024156 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 115526024156 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 115526024156 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 115526024156 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8124072 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8124072 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5417781 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5417781 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 185223 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 185223 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 191650 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 191650 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13541853 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13541853 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13541853 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13541853 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.195979 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.195979 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.317159 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.317159 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.112491 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.112491 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.012930 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.012930 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.244460 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.244460 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.244460 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.244460 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 24680.022661 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 24680.022661 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44364.677179 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 44364.677179 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15646.993185 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15646.993185 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8393.401130 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8393.401130 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34897.419911 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 34897.419911 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34897.419911 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 34897.419911 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 4226969 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 4392 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 103766 # number of cycles access was blocked +system.cpu0.commit.op_class_0::total 38919724 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1444308 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 132264444 # The number of ROB reads +system.cpu0.rob.rob_writes 89122078 # The number of ROB writes +system.cpu0.timesIdled 337516 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 3535662 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3721701460 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 36785489 # Number of Instructions Simulated +system.cpu0.committedOps 36785489 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 2.562388 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.562388 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.390261 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.390261 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 51878765 # number of integer regfile reads +system.cpu0.int_regfile_writes 28204778 # number of integer regfile writes +system.cpu0.fp_regfile_reads 81728 # number of floating regfile reads +system.cpu0.fp_regfile_writes 81429 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1387632 # number of misc regfile reads +system.cpu0.misc_regfile_writes 636485 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 898491 # number of replacements +system.cpu0.dcache.tags.tagsinuse 481.994698 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 8012262 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 899003 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.912386 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 26393500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 481.994698 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.941396 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.941396 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 236 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 43230678 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 43230678 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 5046736 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5046736 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 2679789 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 2679789 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 129628 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 129628 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149296 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 149296 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 7726525 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 7726525 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 7726525 # number of overall hits +system.cpu0.dcache.overall_hits::total 7726525 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1067598 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1067598 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1496200 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1496200 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 12202 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 12202 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 769 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 769 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 2563798 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2563798 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 2563798 # number of overall misses +system.cpu0.dcache.overall_misses::total 2563798 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 32014122500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 32014122500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 69455032918 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 69455032918 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 190587000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 190587000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5445000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 5445000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 101469155418 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 101469155418 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 101469155418 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 101469155418 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6114334 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6114334 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4175989 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4175989 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 141830 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 141830 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 150065 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 150065 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 10290323 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 10290323 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 10290323 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 10290323 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.174606 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.174606 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.358286 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.358286 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086033 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086033 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.005124 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.005124 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.249147 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.249147 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.249147 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.249147 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 29987.057394 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 29987.057394 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 46420.955031 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 46420.955031 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15619.324701 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15619.324701 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7080.624187 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7080.624187 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39577.671649 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 39577.671649 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39577.671649 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 39577.671649 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 4094264 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 5021 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 103728 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 94 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 40.735588 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 46.723404 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 39.471155 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 53.414894 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 752753 # number of writebacks -system.cpu0.dcache.writebacks::total 752753 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 572031 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 572031 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1457971 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1457971 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4881 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4881 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2030002 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2030002 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2030002 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2030002 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1020115 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1020115 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 260329 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 260329 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15955 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15955 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2477 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 2477 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1280444 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1280444 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1280444 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1280444 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7039 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7039 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10032 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10032 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17071 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17071 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 28982142208 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 28982142208 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11887451669 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11887451669 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 177873500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 177873500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 17082652 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 17082652 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 40869593877 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 40869593877 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 40869593877 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 40869593877 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1464167000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1464167000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2129748498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2129748498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3593915498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3593915498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125567 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125567 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048051 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048051 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086139 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086139 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.012925 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.012925 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094555 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.094555 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094555 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.094555 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28410.661747 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28410.661747 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45663.186464 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45663.186464 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11148.448762 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11148.448762 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6896.508680 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6896.508680 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31918.298557 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31918.298557 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31918.298557 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31918.298557 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208007.813610 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208007.813610 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 212295.504187 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212295.504187 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 210527.531955 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 210527.531955 # average overall mshr uncacheable latency +system.cpu0.dcache.writebacks::writebacks 426068 # number of writebacks +system.cpu0.dcache.writebacks::total 426068 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 384761 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 384761 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1282051 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1282051 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 3514 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 3514 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1666812 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1666812 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1666812 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1666812 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 682837 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 682837 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 214149 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 214149 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8688 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8688 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 769 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 769 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 896986 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 896986 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 896986 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 896986 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 4777 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 4777 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 8020 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 8020 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 12797 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 12797 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25205904500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25205904500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10851652245 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10851652245 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 107603000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 107603000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4676000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4676000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 36057556745 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 36057556745 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 36057556745 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 36057556745 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1013290500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1013290500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1707574498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1707574498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2720864998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2720864998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.111678 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.111678 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051281 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051281 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061256 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.061256 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.005124 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.005124 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.087168 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.087168 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.087168 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.087168 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 36913.501319 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 36913.501319 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 50673.373422 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 50673.373422 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12385.244015 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12385.244015 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6080.624187 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6080.624187 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 40198.572492 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 40198.572492 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 40198.572492 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 40198.572492 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 212118.589073 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 212118.589073 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 212914.525935 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212914.525935 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 212617.410174 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 212617.410174 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 911417 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.418391 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 7153262 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 911929 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 7.844100 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 28352545250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.418391 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994958 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.994958 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 615978 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.684225 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 5692804 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 616490 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 9.234220 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 28149663500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.684225 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.993524 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.993524 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 430 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 9022750 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 9022750 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 7153262 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 7153262 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 7153262 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 7153262 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 7153262 # number of overall hits -system.cpu0.icache.overall_hits::total 7153262 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 957376 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 957376 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 957376 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 957376 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 957376 # number of overall misses -system.cpu0.icache.overall_misses::total 957376 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13452406105 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13452406105 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13452406105 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13452406105 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13452406105 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13452406105 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 8110638 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 8110638 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 8110638 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 8110638 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 8110638 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 8110638 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.118040 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.118040 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.118040 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.118040 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.118040 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.118040 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14051.329995 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14051.329995 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14051.329995 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14051.329995 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14051.329995 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14051.329995 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 5687 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 6959538 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 6959538 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 5692804 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 5692804 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5692804 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 5692804 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5692804 # number of overall hits +system.cpu0.icache.overall_hits::total 5692804 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 650065 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 650065 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 650065 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 650065 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 650065 # number of overall misses +system.cpu0.icache.overall_misses::total 650065 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9309214992 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 9309214992 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 9309214992 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 9309214992 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 9309214992 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 9309214992 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6342869 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 6342869 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6342869 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 6342869 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6342869 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 6342869 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.102488 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.102488 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.102488 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.102488 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.102488 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.102488 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14320.437175 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14320.437175 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14320.437175 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14320.437175 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14320.437175 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14320.437175 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 3481 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 195 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 166 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 29.164103 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 20.969880 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 45264 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 45264 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 45264 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 45264 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 45264 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 45264 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 912112 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 912112 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 912112 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 912112 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 912112 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 912112 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11511971092 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11511971092 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11511971092 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11511971092 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11511971092 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11511971092 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.112459 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.112459 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.112459 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.112459 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.112459 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.112459 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12621.225345 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12621.225345 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12621.225345 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12621.225345 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12621.225345 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12621.225345 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 33396 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 33396 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 33396 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 33396 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 33396 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 33396 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 616669 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 616669 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 616669 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 616669 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 616669 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 616669 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8251915495 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 8251915495 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8251915495 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 8251915495 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8251915495 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 8251915495 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.097222 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.097222 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.097222 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.097222 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.097222 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.097222 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13381.433954 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13381.433954 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13381.433954 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13381.433954 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13381.433954 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13381.433954 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 3445639 # Number of BP lookups -system.cpu1.branchPred.condPredicted 3003437 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 69264 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 1910439 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 836162 # Number of BTB hits +system.cpu1.branchPred.lookups 7710185 # Number of BP lookups +system.cpu1.branchPred.condPredicted 6710334 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 163097 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 4502045 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 2070765 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 43.768055 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 167186 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 4809 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 45.996097 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 394984 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 11166 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1858276 # DTB read hits -system.cpu1.dtb.read_misses 10905 # DTB read misses -system.cpu1.dtb.read_acv 64 # DTB read access violations -system.cpu1.dtb.read_accesses 300263 # DTB read accesses -system.cpu1.dtb.write_hits 1193771 # DTB write hits -system.cpu1.dtb.write_misses 2902 # DTB write misses -system.cpu1.dtb.write_acv 104 # DTB write access violations -system.cpu1.dtb.write_accesses 125157 # DTB write accesses -system.cpu1.dtb.data_hits 3052047 # DTB hits -system.cpu1.dtb.data_misses 13807 # DTB misses -system.cpu1.dtb.data_acv 168 # DTB access violations -system.cpu1.dtb.data_accesses 425420 # DTB accesses -system.cpu1.itb.fetch_hits 529068 # ITB hits -system.cpu1.itb.fetch_misses 7485 # ITB misses -system.cpu1.itb.fetch_acv 158 # ITB acv -system.cpu1.itb.fetch_accesses 536553 # ITB accesses +system.cpu1.dtb.read_hits 4026297 # DTB read hits +system.cpu1.dtb.read_misses 14233 # DTB read misses +system.cpu1.dtb.read_acv 6 # DTB read access violations +system.cpu1.dtb.read_accesses 293572 # DTB read accesses +system.cpu1.dtb.write_hits 2497972 # DTB write hits +system.cpu1.dtb.write_misses 2408 # DTB write misses +system.cpu1.dtb.write_acv 37 # DTB write access violations +system.cpu1.dtb.write_accesses 109195 # DTB write accesses +system.cpu1.dtb.data_hits 6524269 # DTB hits +system.cpu1.dtb.data_misses 16641 # DTB misses +system.cpu1.dtb.data_acv 43 # DTB access violations +system.cpu1.dtb.data_accesses 402767 # DTB accesses +system.cpu1.itb.fetch_hits 750930 # ITB hits +system.cpu1.itb.fetch_misses 5383 # ITB misses +system.cpu1.itb.fetch_acv 53 # ITB acv +system.cpu1.itb.fetch_accesses 756313 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -965,570 +972,564 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 14296923 # number of cpu cycles simulated +system.cpu1.numCycles 34369930 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 5827989 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 13624759 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 3445639 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1003348 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 7312463 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 270756 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 304 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 25051 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 299772 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 60327 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1551048 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 55046 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 13661307 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.997325 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.404073 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 13361598 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 30714280 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 7710185 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 2465749 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 18120966 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 547594 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 46 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 23797 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 211021 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 198154 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 54 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 3304195 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 117193 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 32189433 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.954173 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.349586 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 11273523 82.52% 82.52% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 149434 1.09% 83.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 236962 1.73% 85.35% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 182278 1.33% 86.68% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 319422 2.34% 89.02% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 124907 0.91% 89.94% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 138046 1.01% 90.95% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 169812 1.24% 92.19% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1066923 7.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 26750456 83.10% 83.10% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 307184 0.95% 84.06% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 618506 1.92% 85.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 382121 1.19% 87.17% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 801179 2.49% 89.66% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 249293 0.77% 90.43% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 334783 1.04% 91.47% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 403446 1.25% 92.72% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 2342465 7.28% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 13661307 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.241006 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.952985 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 4848979 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 6756897 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 1724085 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 202692 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 128653 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 104901 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 6833 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 11127112 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 21450 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 128653 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 4991483 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 690115 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 5206241 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1784475 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 860338 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 10551561 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 3558 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 63390 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 12017 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 381484 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 6914568 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 12620115 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 12571129 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 43721 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 5829921 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1084639 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 430965 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 39644 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1821487 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 1910201 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1273290 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 221141 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 146764 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 9284732 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 487174 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 9053277 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 20996 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1564088 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 731721 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 360528 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 13661307 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.662695 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.384311 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 32189433 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.224329 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.893638 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 11124412 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 16339992 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 3934359 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 534571 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 256098 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 250042 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 17822 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 25897409 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 55799 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 256098 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 11423416 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 4918911 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 9329125 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 4131002 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 2130879 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 24789451 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 5724 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 540758 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 43054 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 820253 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 16289258 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 29487961 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 29391972 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 88964 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 13777657 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 2511601 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 753305 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 82405 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 4252225 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 4127805 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 2629581 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 507300 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 331297 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 21789875 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 948507 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 21283611 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 28389 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 3414486 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 1484281 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 680406 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 32189433 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.661199 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.387208 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 9895925 72.44% 72.44% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1648518 12.07% 84.50% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 704790 5.16% 89.66% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 494622 3.62% 93.28% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 437905 3.21% 96.49% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 233549 1.71% 98.20% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 155573 1.14% 99.34% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 64890 0.47% 99.81% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 25535 0.19% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 23533399 73.11% 73.11% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 3630192 11.28% 84.39% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 1573878 4.89% 89.28% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 1186258 3.69% 92.96% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 1178148 3.66% 96.62% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 546160 1.70% 98.32% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 337865 1.05% 99.37% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 151957 0.47% 99.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 51576 0.16% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 13661307 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 32189433 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 22279 8.85% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 136629 54.29% 63.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 92774 36.86% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 80499 16.46% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 246874 50.47% 66.92% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 161807 33.08% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 2817 0.03% 0.03% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 5609130 61.96% 61.99% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 14890 0.16% 62.15% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.15% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 8778 0.10% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1408 0.02% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 1940639 21.44% 83.70% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1217689 13.45% 97.15% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 257926 2.85% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3518 0.02% 0.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 14071465 66.11% 66.13% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 30174 0.14% 66.27% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 66.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 13456 0.06% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1759 0.01% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 4194422 19.71% 86.05% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 2532925 11.90% 97.95% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 435892 2.05% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 9053277 # Type of FU issued -system.cpu1.iq.rate 0.633233 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 251682 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.027800 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 31870123 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 11259293 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 8718718 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 170415 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 80938 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 78899 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 9210850 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 91292 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 92092 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 21283611 # Type of FU issued +system.cpu1.iq.rate 0.619251 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 489180 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.022984 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 74907239 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 25989017 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 20583813 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 366985 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 171482 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 168729 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 21571772 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 197501 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 207443 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 283440 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 879 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 4333 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 136775 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 572592 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 1888 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 7837 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 247159 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 421 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 73078 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 7441 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 131088 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 128653 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 295868 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 364148 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 10275512 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 29401 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 1910201 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1273290 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 443383 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 3815 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 359581 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 4333 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 31404 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 95843 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 127247 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 8933578 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1876162 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 119698 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 256098 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 4050515 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 319306 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 24169619 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 59065 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 4127805 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 2629581 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 846465 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 33159 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 202940 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 7837 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 80858 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 187737 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 268595 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 21021510 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 4051663 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 262101 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 503606 # number of nop insts executed -system.cpu1.iew.exec_refs 3078439 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1318456 # Number of branches executed -system.cpu1.iew.exec_stores 1202277 # Number of stores executed -system.cpu1.iew.exec_rate 0.624860 # Inst execution rate -system.cpu1.iew.wb_sent 8830913 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 8797617 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 4148200 # num instructions producing a value -system.cpu1.iew.wb_consumers 5856949 # num instructions consuming a value +system.cpu1.iew.exec_nop 1431237 # number of nop insts executed +system.cpu1.iew.exec_refs 6560061 # number of memory reference insts executed +system.cpu1.iew.exec_branches 3322997 # Number of branches executed +system.cpu1.iew.exec_stores 2508398 # Number of stores executed +system.cpu1.iew.exec_rate 0.611625 # Inst execution rate +system.cpu1.iew.wb_sent 20805592 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 20752542 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 10210202 # num instructions producing a value +system.cpu1.iew.wb_consumers 14612629 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.615350 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.708253 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.603799 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.698725 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 1592161 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 126646 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 116539 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 13369044 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.644454 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.620421 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 3582987 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 268101 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 243613 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 31565232 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.650241 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.623237 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 10245809 76.64% 76.64% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1446725 10.82% 87.46% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 518907 3.88% 91.34% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 315988 2.36% 93.70% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 242120 1.81% 95.52% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 97246 0.73% 96.24% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 91600 0.69% 96.93% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 106270 0.79% 97.72% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 304379 2.28% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 24282945 76.93% 76.93% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 2976975 9.43% 86.36% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1587723 5.03% 91.39% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 771361 2.44% 93.83% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 532421 1.69% 95.52% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 258990 0.82% 96.34% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 207817 0.66% 97.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 189047 0.60% 97.60% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 757953 2.40% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 13369044 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 8615735 # Number of instructions committed -system.cpu1.commit.committedOps 8615735 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 31565232 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 20524993 # Number of instructions committed +system.cpu1.commit.committedOps 20524993 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 2763276 # Number of memory references committed -system.cpu1.commit.loads 1626761 # Number of loads committed -system.cpu1.commit.membars 39485 # Number of memory barriers committed -system.cpu1.commit.branches 1225974 # Number of branches committed -system.cpu1.commit.fp_insts 77544 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 7995429 # Number of committed integer instructions. -system.cpu1.commit.function_calls 135018 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 410738 4.77% 4.77% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 5119196 59.42% 64.18% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 14466 0.17% 64.35% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.35% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 8774 0.10% 64.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 1408 0.02% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 1666246 19.34% 83.81% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 1136981 13.20% 97.01% # Class of committed instruction -system.cpu1.commit.op_class_0::IprAccess 257926 2.99% 100.00% # Class of committed instruction +system.cpu1.commit.refs 5937635 # Number of memory references committed +system.cpu1.commit.loads 3555213 # Number of loads committed +system.cpu1.commit.membars 92415 # Number of memory barriers committed +system.cpu1.commit.branches 3082130 # Number of branches committed +system.cpu1.commit.fp_insts 166998 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 18893824 # Number of committed integer instructions. +system.cpu1.commit.function_calls 318960 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 1204616 5.87% 5.87% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 12808497 62.40% 68.27% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 29745 0.14% 68.42% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 68.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 13451 0.07% 68.48% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 68.48% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 68.48% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 68.48% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 1759 0.01% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 3647628 17.77% 86.26% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 2383405 11.61% 97.88% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 435892 2.12% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 8615735 # Class of committed instruction -system.cpu1.commit.bw_lim_events 304379 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 23176968 # The number of ROB reads -system.cpu1.rob.rob_writes 20704388 # The number of ROB writes -system.cpu1.timesIdled 112605 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 635616 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3794578226 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 8207813 # Number of Instructions Simulated -system.cpu1.committedOps 8207813 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.741868 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.741868 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.574096 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.574096 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 11535994 # number of integer regfile reads -system.cpu1.int_regfile_writes 6250844 # number of integer regfile writes -system.cpu1.fp_regfile_reads 43175 # number of floating regfile reads -system.cpu1.fp_regfile_writes 42684 # number of floating regfile writes -system.cpu1.misc_regfile_reads 891820 # number of misc regfile reads -system.cpu1.misc_regfile_writes 203240 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 102439 # number of replacements -system.cpu1.dcache.tags.tagsinuse 489.756832 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 2417231 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 102951 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 23.479432 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 1034185261500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 489.756832 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.956556 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.956556 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 224 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 237 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 11476458 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 11476458 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 1494681 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1494681 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 855193 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 855193 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 29899 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 29899 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 28520 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 28520 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 2349874 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2349874 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 2349874 # number of overall hits -system.cpu1.dcache.overall_hits::total 2349874 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 181396 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 181396 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 244262 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 244262 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4731 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 4731 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2607 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 2607 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 425658 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 425658 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 425658 # number of overall misses -system.cpu1.dcache.overall_misses::total 425658 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2290258065 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2290258065 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 9952106154 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 9952106154 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 46237999 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 46237999 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 22188385 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 22188385 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 12242364219 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 12242364219 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 12242364219 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 12242364219 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1676077 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1676077 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1099455 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1099455 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 34630 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 34630 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 31127 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 31127 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 2775532 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 2775532 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 2775532 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 2775532 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.108227 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.108227 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.222166 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.222166 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.136616 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.136616 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.083754 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.083754 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.153361 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.153361 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.153361 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.153361 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12625.736317 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12625.736317 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 40743.571059 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 40743.571059 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9773.409216 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9773.409216 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8511.079785 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8511.079785 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 28761.034020 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 28761.034020 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 28761.034020 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 28761.034020 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 574336 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 346 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 18255 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 8 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 31.461846 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 43.250000 # average number of cycles each access was blocked +system.cpu1.commit.op_class_0::total 20524993 # Class of committed instruction +system.cpu1.commit.bw_lim_events 757953 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 54833276 # The number of ROB reads +system.cpu1.rob.rob_writes 48835744 # The number of ROB writes +system.cpu1.timesIdled 276866 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 2180497 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3780899978 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 19323895 # Number of Instructions Simulated +system.cpu1.committedOps 19323895 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.778623 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.778623 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.562233 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.562233 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 27142723 # number of integer regfile reads +system.cpu1.int_regfile_writes 14810250 # number of integer regfile writes +system.cpu1.fp_regfile_reads 88193 # number of floating regfile reads +system.cpu1.fp_regfile_writes 88824 # number of floating regfile writes +system.cpu1.misc_regfile_reads 1272248 # number of misc regfile reads +system.cpu1.misc_regfile_writes 377130 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 561653 # number of replacements +system.cpu1.dcache.tags.tagsinuse 496.197725 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 4717582 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 561970 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 8.394722 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 37149185000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 496.197725 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.969136 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.969136 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 317 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 317 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.619141 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 24916279 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 24916279 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 2844065 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2844065 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1751257 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1751257 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 62172 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 62172 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 69860 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 69860 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 4595322 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 4595322 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 4595322 # number of overall hits +system.cpu1.dcache.overall_hits::total 4595322 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 792097 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 792097 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 552973 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 552973 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14160 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 14160 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 786 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 786 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 1345070 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 1345070 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 1345070 # number of overall misses +system.cpu1.dcache.overall_misses::total 1345070 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 10154789500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 10154789500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 16820667860 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 16820667860 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 217520000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 217520000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 6395000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 6395000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 26975457360 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 26975457360 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 26975457360 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 26975457360 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 3636162 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3636162 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 2304230 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 2304230 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 76332 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 76332 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 70646 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 70646 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 5940392 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 5940392 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 5940392 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 5940392 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.217839 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.217839 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.239982 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.239982 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.185505 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.185505 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.011126 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.011126 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.226428 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.226428 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.226428 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.226428 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12820.133771 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12820.133771 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30418.606080 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 30418.606080 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15361.581921 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15361.581921 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8136.132316 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8136.132316 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20055.058369 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20055.058369 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20055.058369 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20055.058369 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 765854 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 810 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 36939 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 18 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 20.732938 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 45 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 70134 # number of writebacks -system.cpu1.dcache.writebacks::total 70134 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 110614 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 110614 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 203686 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 203686 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 700 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 700 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 314300 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 314300 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 314300 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 314300 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 70782 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 70782 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 40576 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 40576 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4031 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4031 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2607 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 2607 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 111358 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 111358 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 111358 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 111358 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 158 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 158 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2893 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2893 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3051 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3051 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 815361518 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 815361518 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1580599049 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1580599049 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 32399501 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 32399501 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 18277115 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 18277115 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2395960567 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2395960567 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2395960567 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2395960567 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 29330000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 29330000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 630993000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 630993000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 660323000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 660323000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042231 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042231 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036906 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036906 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.116402 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.116402 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.083754 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.083754 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.040121 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.040121 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.040121 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.040121 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11519.334266 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11519.334266 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38954.038077 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 38954.038077 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8037.583974 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8037.583974 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7010.784427 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7010.784427 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 21515.836913 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 21515.836913 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21515.836913 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21515.836913 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 185632.911392 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185632.911392 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 218110.266160 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 218110.266160 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 216428.384136 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 216428.384136 # average overall mshr uncacheable latency +system.cpu1.dcache.writebacks::writebacks 435263 # number of writebacks +system.cpu1.dcache.writebacks::total 435263 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 332265 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 332265 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 455576 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 455576 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 2707 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 2707 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 787841 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 787841 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 787841 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 787841 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 459832 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 459832 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 97397 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 97397 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11453 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11453 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 786 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 786 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 557229 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 557229 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 557229 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 557229 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 2425 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 2425 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 4340 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 4340 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 6765 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 6765 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 5761115500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 5761115500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2818212839 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2818212839 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 135759000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 135759000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5609000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5609000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8579328339 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 8579328339 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8579328339 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 8579328339 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 499447000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 499447000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 957710500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 957710500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1457157500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1457157500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.126461 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.126461 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.042269 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.042269 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.150042 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.150042 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.011126 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.011126 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.093803 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.093803 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.093803 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.093803 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12528.739844 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12528.739844 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28935.314630 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28935.314630 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11853.575482 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11853.575482 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7136.132316 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7136.132316 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15396.413932 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15396.413932 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15396.413932 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15396.413932 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 205957.525773 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 205957.525773 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 220670.622120 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 220670.622120 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 215396.526238 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 215396.526238 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 211356 # number of replacements -system.cpu1.icache.tags.tagsinuse 472.195820 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 1331062 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 211865 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 6.282595 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1880244277250 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 472.195820 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.922257 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.922257 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 392 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 1762968 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 1762968 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 1331062 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1331062 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1331062 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1331062 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1331062 # number of overall hits -system.cpu1.icache.overall_hits::total 1331062 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 219986 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 219986 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 219986 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 219986 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 219986 # number of overall misses -system.cpu1.icache.overall_misses::total 219986 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2974295730 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 2974295730 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 2974295730 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 2974295730 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 2974295730 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 2974295730 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1551048 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1551048 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1551048 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1551048 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1551048 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1551048 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.141831 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.141831 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.141831 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.141831 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.141831 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.141831 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13520.386434 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13520.386434 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13520.386434 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13520.386434 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13520.386434 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13520.386434 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 613 # number of cycles access was blocked +system.cpu1.icache.tags.replacements 499853 # number of replacements +system.cpu1.icache.tags.tagsinuse 504.618896 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 2783346 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 500364 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 5.562642 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 48744804500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 504.618896 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.985584 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.985584 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 511 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 3804626 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 3804626 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 2783351 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 2783351 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 2783351 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 2783351 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 2783351 # number of overall hits +system.cpu1.icache.overall_hits::total 2783351 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 520843 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 520843 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 520843 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 520843 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 520843 # number of overall misses +system.cpu1.icache.overall_misses::total 520843 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7005360499 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7005360499 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7005360499 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7005360499 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7005360499 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7005360499 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 3304194 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 3304194 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 3304194 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 3304194 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 3304194 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 3304194 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.157631 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.157631 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.157631 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.157631 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.157631 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.157631 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13450.042525 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13450.042525 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13450.042525 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13450.042525 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13450.042525 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13450.042525 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 1720 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 40 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 65 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 15.325000 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 26.461538 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 8066 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 8066 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 8066 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 8066 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 8066 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 8066 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 211920 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 211920 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 211920 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 211920 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 211920 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 211920 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2567742004 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 2567742004 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2567742004 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 2567742004 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2567742004 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 2567742004 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.136630 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.136630 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.136630 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.136630 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.136630 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.136630 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12116.562873 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12116.562873 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12116.562873 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12116.562873 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12116.562873 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12116.562873 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 20411 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 20411 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 20411 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 20411 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 20411 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 20411 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 500432 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 500432 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 500432 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 500432 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 500432 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 500432 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6297993499 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 6297993499 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6297993499 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 6297993499 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6297993499 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 6297993499 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.151454 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.151454 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.151454 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.151454 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.151454 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.151454 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12585.113460 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12585.113460 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12585.113460 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12585.113460 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12585.113460 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12585.113460 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1542,54 +1543,53 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 7375 # Transaction distribution -system.iobus.trans_dist::ReadResp 7375 # Transaction distribution -system.iobus.trans_dist::WriteReq 54477 # Transaction distribution -system.iobus.trans_dist::WriteResp 12925 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11660 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 7377 # Transaction distribution +system.iobus.trans_dist::ReadResp 7377 # Transaction distribution +system.iobus.trans_dist::WriteReq 53912 # Transaction distribution +system.iobus.trans_dist::WriteResp 53912 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10518 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 172 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18142 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6674 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 40244 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83460 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83460 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 123704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 46640 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 39124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 122578 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 42072 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 149 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9071 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 72837 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661648 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661648 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2734485 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 11011000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 68315 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2729939 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 9868000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 148000 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 13500000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 2450000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) @@ -1601,285 +1601,291 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 242105442 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 216085248 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 27319000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 26764000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42037503 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41950000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 41698 # number of replacements -system.iocache.tags.tagsinuse 0.483577 # Cycle average of tags in use +system.iocache.tags.replacements 41701 # number of replacements +system.iocache.tags.tagsinuse 0.804902 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41714 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41717 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1711318407000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.483577 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.030224 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.030224 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1711319254000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.804902 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.050306 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.050306 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375570 # Number of tag accesses -system.iocache.tags.data_accesses 375570 # Number of data accesses -system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses -system.iocache.ReadReq_misses::total 178 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses -system.iocache.demand_misses::tsunami.ide 178 # number of demand (read+write) misses -system.iocache.demand_misses::total 178 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 178 # number of overall misses -system.iocache.overall_misses::total 178 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 22300881 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 22300881 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8783600058 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 8783600058 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 22300881 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 22300881 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 22300881 # number of overall miss cycles -system.iocache.overall_miss_latency::total 22300881 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 178 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 178 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 178 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 178 # number of overall (read+write) accesses +system.iocache.tags.tag_accesses 375543 # Number of tag accesses +system.iocache.tags.data_accesses 375543 # Number of data accesses +system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses +system.iocache.ReadReq_misses::total 175 # number of ReadReq misses +system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses +system.iocache.demand_misses::tsunami.ide 175 # number of demand (read+write) misses +system.iocache.demand_misses::total 175 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 175 # number of overall misses +system.iocache.overall_misses::total 175 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 25392883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 25392883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4907312365 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4907312365 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 25392883 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 25392883 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 25392883 # number of overall miss cycles +system.iocache.overall_miss_latency::total 25392883 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) +system.iocache.demand_accesses::tsunami.ide 175 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 175 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 175 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 175 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125285.848315 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125285.848315 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 211388.141558 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 211388.141558 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 125285.848315 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125285.848315 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 125285.848315 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125285.848315 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 73351 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 145102.188571 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 145102.188571 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118100.509362 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118100.509362 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 145102.188571 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 145102.188571 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 145102.188571 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 145102.188571 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10036 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.308788 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 41520 # number of writebacks -system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 178 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 178 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 178 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 178 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12879885 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12879885 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6622894060 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6622894060 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12879885 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12879885 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12879885 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12879885 # number of overall MSHR miss cycles +system.iocache.writebacks::writebacks 41526 # number of writebacks +system.iocache.writebacks::total 41526 # number of writebacks +system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 175 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 175 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 175 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 175 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 16642883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 16642883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2829712365 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2829712365 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 16642883 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 16642883 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 16642883 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 16642883 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72358.904494 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72358.904494 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 159388.093473 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 159388.093473 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72358.904494 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72358.904494 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72358.904494 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72358.904494 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 95102.188571 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 95102.188571 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68100.509362 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68100.509362 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 95102.188571 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 95102.188571 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 95102.188571 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 95102.188571 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 346915 # number of replacements -system.l2c.tags.tagsinuse 65246.496404 # Cycle average of tags in use -system.l2c.tags.total_refs 2614060 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 412065 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.343805 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 7589002750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 53536.501359 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5301.488199 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6124.882413 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 215.988746 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 67.635688 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.816902 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.080894 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.093458 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003296 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.001032 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995583 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65150 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 223 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 2446 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5392 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 7744 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 49345 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.994110 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 27379617 # Number of tag accesses -system.l2c.tags.data_accesses 27379617 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 898215 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 742471 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 210198 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 63927 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1914811 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 822887 # number of Writeback hits -system.l2c.Writeback_hits::total 822887 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 176 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 246 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 422 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 53 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 30 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 83 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 152332 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 25116 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 177448 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 898215 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 894803 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 210198 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 89043 # number of demand (read+write) hits -system.l2c.demand_hits::total 2092259 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 898215 # number of overall hits -system.l2c.overall_hits::cpu0.data 894803 # number of overall hits -system.l2c.overall_hits::cpu1.inst 210198 # number of overall hits -system.l2c.overall_hits::cpu1.data 89043 # number of overall hits -system.l2c.overall_hits::total 2092259 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 13731 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 273058 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1686 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 819 # number of ReadReq misses -system.l2c.ReadReq_misses::total 289294 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2683 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1043 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3726 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 349 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 386 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 735 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 112818 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 10944 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 123762 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 13731 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 385876 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1686 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 11763 # number of demand (read+write) misses -system.l2c.demand_misses::total 413056 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 13731 # number of overall misses -system.l2c.overall_misses::cpu0.data 385876 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1686 # number of overall misses -system.l2c.overall_misses::cpu1.data 11763 # number of overall misses -system.l2c.overall_misses::total 413056 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 1146699750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 19948507750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 143666750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 75193250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 21314067500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 1596458 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 5835814 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 7432272 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1194963 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 187494 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 1382457 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 9983790515 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1229173205 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 11212963720 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1146699750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 29932298265 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 143666750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1304366455 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 32527031220 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1146699750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 29932298265 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 143666750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1304366455 # number of overall miss cycles -system.l2c.overall_miss_latency::total 32527031220 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 911946 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 1015529 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 211884 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 64746 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2204105 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 822887 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 822887 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2859 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1289 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 4148 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 402 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 416 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 818 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 265150 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 36060 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 301210 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 911946 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1280679 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 211884 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 100806 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2505315 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 911946 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1280679 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 211884 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 100806 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2505315 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015057 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.268883 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.007957 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.012649 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.131252 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.938440 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.809154 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.898264 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.868159 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.927885 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.898533 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.425487 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.303494 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.410883 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015057 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.301306 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.007957 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.116689 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.164872 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015057 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.301306 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.007957 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.116689 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.164872 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 83511.743500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 73055.935918 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 85211.595492 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 91811.050061 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 73676.147794 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 595.027208 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5595.219559 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 1994.705314 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3423.962751 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 485.735751 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 1880.893878 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 88494.659673 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 112314.803088 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 90601.022285 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 83511.743500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 77569.732932 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 85211.595492 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 110887.227323 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 78747.267247 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 83511.743500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 77569.732932 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 85211.595492 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 110887.227323 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 78747.267247 # average overall miss latency +system.l2c.tags.replacements 346141 # number of replacements +system.l2c.tags.tagsinuse 65297.340756 # Cycle average of tags in use +system.l2c.tags.total_refs 4025883 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 411324 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 9.787620 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 7535768000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 53443.709143 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4213.616295 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 5688.285915 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1375.831057 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 575.898345 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.815486 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.064295 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.086796 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.020994 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.008788 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.996358 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65183 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 228 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 2225 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 5965 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6968 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 49797 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.994614 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 38794162 # Number of tag accesses +system.l2c.tags.data_accesses 38794162 # Number of data accesses +system.l2c.Writeback_hits::writebacks 861331 # number of Writeback hits +system.l2c.Writeback_hits::total 861331 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 141 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 80 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 221 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 38 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 36 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 74 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 115055 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 78240 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 193295 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 604919 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 496677 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 1101596 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 403562 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 443803 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 847365 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.inst 604919 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 518617 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 496677 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 522043 # number of demand (read+write) hits +system.l2c.demand_hits::total 2142256 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 604919 # number of overall hits +system.l2c.overall_hits::cpu0.data 518617 # number of overall hits +system.l2c.overall_hits::cpu1.inst 496677 # number of overall hits +system.l2c.overall_hits::cpu1.data 522043 # number of overall hits +system.l2c.overall_hits::total 2142256 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 2583 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 538 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3121 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 69 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 100 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 169 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 105448 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 17488 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 122936 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 11627 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 3714 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 15341 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 272098 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 2179 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 274277 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.inst 11627 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 377546 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 3714 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 19667 # number of demand (read+write) misses +system.l2c.demand_misses::total 412554 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 11627 # number of overall misses +system.l2c.overall_misses::cpu0.data 377546 # number of overall misses +system.l2c.overall_misses::cpu1.inst 3714 # number of overall misses +system.l2c.overall_misses::cpu1.data 19667 # number of overall misses +system.l2c.overall_misses::total 412554 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0.data 1390000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 1722000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 3112000 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 341500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 214500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 556000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 9317536000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 1807849000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 11125385000 # number of ReadExReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu0.inst 964295500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu1.inst 315495500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 1279791000 # number of ReadCleanReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 19840935500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 172644000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 20013579500 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 964295500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 29158471500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 315495500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1980493000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 32418755500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 964295500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 29158471500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 315495500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1980493000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 32418755500 # number of overall miss cycles +system.l2c.Writeback_accesses::writebacks 861331 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 861331 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 2724 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 618 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3342 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 107 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 136 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 243 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 220503 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 95728 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 316231 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 616546 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 500391 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 1116937 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 675660 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 445982 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 1121642 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 616546 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 896163 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 500391 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 541710 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2554810 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 616546 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 896163 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 500391 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 541710 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2554810 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.948238 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.870550 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.933872 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.644860 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.735294 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.695473 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.478216 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.182684 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.388754 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.018858 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.007422 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.013735 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.402714 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.004886 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.244532 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.018858 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.421292 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.007422 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.036305 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.161481 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.018858 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.421292 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.007422 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.036305 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.161481 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 538.133953 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3200.743494 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 997.116309 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4949.275362 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2145 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 3289.940828 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 88361.429330 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 103376.543916 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 90497.372617 # average ReadExReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 82935.881999 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 84947.630587 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 83422.918975 # average ReadCleanReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 72918.343758 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 79230.839835 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 72968.493530 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 82935.881999 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 77231.573106 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 84947.630587 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 100701.327096 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 78580.635505 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 82935.881999 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 77231.573106 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 84947.630587 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 100701.327096 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 78580.635505 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1888,239 +1894,253 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 83224 # number of writebacks -system.l2c.writebacks::total 83224 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 9 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 9 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 19 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 9 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 9 # number of demand (read+write) MSHR hits +system.l2c.writebacks::writebacks 82738 # number of writebacks +system.l2c.writebacks::total 82738 # number of writebacks +system.l2c.ReadCleanReq_mshr_hits::cpu0.inst 1 # number of ReadCleanReq MSHR hits +system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 17 # number of ReadCleanReq MSHR hits +system.l2c.ReadCleanReq_mshr_hits::total 18 # number of ReadCleanReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.data 1 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 1 # number of ReadSharedReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 17 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 19 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 9 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 9 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 17 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 19 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 13722 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 273058 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 1677 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 818 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 289275 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 2683 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1043 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 3726 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 349 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 386 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 735 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 112818 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 10944 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 123762 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 13722 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 385876 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 1677 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 11762 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 413037 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 13722 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 385876 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 1677 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 11762 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 413037 # number of overall MSHR misses -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 7039 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 158 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 7197 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 10032 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2893 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 12925 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 17071 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 3051 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 20122 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 974652500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 16545106250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 122062750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 65122250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 17706943750 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 47889169 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 18491538 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 66380707 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 6218348 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 6847885 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 13066233 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 8604034485 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1094197795 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 9698232280 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 974652500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 25149140735 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 122062750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 1159320045 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 27405176030 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 974652500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 25149140735 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 122062750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 1159320045 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 27405176030 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1365620000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 27118000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 1392738000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1999167500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 591543000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 2590710500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3364787500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 618661000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 3983448500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015047 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.268883 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.007915 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.012634 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.131244 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.938440 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.809154 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.898264 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.868159 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.927885 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.898533 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.425487 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.303494 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.410883 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015047 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.301306 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007915 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.116680 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.164864 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015047 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.301306 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007915 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.116680 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.164864 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 71028.457951 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 60591.911792 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 72786.374478 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 79611.552567 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 61211.455363 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17849.112561 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17729.183126 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17815.541331 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17817.616046 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17740.634715 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17777.187755 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 76264.731559 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 99981.523666 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 78361.955043 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71028.457951 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 65174.151113 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72786.374478 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 98564.873746 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 66350.414200 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71028.457951 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 65174.151113 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72786.374478 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 98564.873746 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 66350.414200 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 194007.671544 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171632.911392 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 193516.465194 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 199279.057018 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 204473.902523 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 200441.818182 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 197105.471267 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 202773.189118 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 197964.839479 # average overall mshr uncacheable latency +system.l2c.CleanEvict_mshr_misses::writebacks 356 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 356 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 2583 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 538 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 3121 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 69 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 100 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 169 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 105448 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 17488 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 122936 # number of ReadExReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 11626 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 3697 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::total 15323 # number of ReadCleanReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 272098 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 2178 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 274276 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 11626 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 377546 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 3697 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 19666 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 412535 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 11626 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 377546 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 3697 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 19666 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 412535 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 4777 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 2425 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 7202 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 8020 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 4340 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 12360 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 12797 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 6765 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 19562 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 53861495 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 11082500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 64943995 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 1433500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 2068000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 3501500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 8263056000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1632969000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 9896025000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 847954500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 277279000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 1125233500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 17126346500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 197172000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 17323518500 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 847954500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 25389402500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 277279000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1830141000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 28344777000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 847954500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 25389402500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 277279000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1830141000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 28344777000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 953578000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 469134500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1422712500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1615175500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 905955000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2521130500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2568753500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1375089500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 3943843000 # number of overall MSHR uncacheable cycles +system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.948238 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.870550 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.933872 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.644860 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.735294 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.695473 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.478216 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.182684 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.388754 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.018857 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.007388 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013719 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.402714 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.004884 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.244531 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018857 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.421292 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007388 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.036304 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.161474 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018857 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.421292 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007388 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.036304 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.161474 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20852.301587 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20599.442379 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20808.713553 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20775.362319 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20680 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20718.934911 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 78361.429330 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 93376.543916 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 80497.372617 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 72936.048512 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 75001.081958 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73434.281799 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 62941.831619 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 90528.925620 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 63160.898146 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72936.048512 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 67248.500845 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75001.081958 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 93061.171565 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 68708.781073 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72936.048512 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 67248.500845 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75001.081958 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 93061.171565 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 68708.781073 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 199618.589073 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 193457.525773 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197544.084976 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 201393.453865 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 208745.391705 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 203974.959547 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 200730.913495 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 203265.262380 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 201607.350987 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 296650 # Transaction distribution -system.membus.trans_dist::ReadResp 296572 # Transaction distribution -system.membus.trans_dist::WriteReq 12925 # Transaction distribution -system.membus.trans_dist::WriteResp 12925 # Transaction distribution -system.membus.trans_dist::Writeback 124744 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 9402 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 5001 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4742 # Transaction distribution -system.membus.trans_dist::ReadExReq 123808 # Transaction distribution -system.membus.trans_dist::ReadExResp 123481 # Transaction distribution -system.membus.trans_dist::BadAddressError 78 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40244 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 927766 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 156 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 968166 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1092983 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 72837 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31719616 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31792453 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 5317568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 37110021 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 10437 # Total snoops (count) -system.membus.snoop_fanout::samples 614132 # Request fanout histogram +system.membus.trans_dist::ReadReq 7202 # Transaction distribution +system.membus.trans_dist::ReadResp 296546 # Transaction distribution +system.membus.trans_dist::WriteReq 12360 # Transaction distribution +system.membus.trans_dist::WriteResp 12360 # Transaction distribution +system.membus.trans_dist::Writeback 124264 # Transaction distribution +system.membus.trans_dist::CleanEvict 262871 # Transaction distribution +system.membus.trans_dist::UpgradeReq 5279 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1481 # Transaction distribution +system.membus.trans_dist::UpgradeResp 3452 # Transaction distribution +system.membus.trans_dist::ReadExReq 122900 # Transaction distribution +system.membus.trans_dist::ReadExResp 122774 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 289774 # Transaction distribution +system.membus.trans_dist::BadAddressError 430 # Transaction distribution +system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39124 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1179542 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 860 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1219526 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124833 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124833 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1344359 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 68315 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31641920 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31710235 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2658624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 34368859 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3872 # Total snoops (count) +system.membus.snoop_fanout::samples 867863 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 614132 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 867863 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 614132 # Request fanout histogram -system.membus.reqLayer0.occupancy 36342500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 867863 # Request fanout histogram +system.membus.reqLayer0.occupancy 35224999 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1279237311 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1361324691 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 100000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 531000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2197321028 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2190703579 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 42525497 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 72073655 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 2231372 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2231278 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 12925 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 12925 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 822887 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 41587 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 9543 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 5084 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 14627 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 302295 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 302295 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 78 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1824058 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3369862 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 423804 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 296769 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5914493 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 58364544 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 130195442 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 13560576 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 10962579 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 213083141 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 72565 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3425693 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.012192 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.109741 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 7202 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2275897 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 12360 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 12360 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 985613 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1602095 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 5338 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 1555 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 6893 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 317171 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 317171 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1117101 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1152039 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 430 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1728214 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2704934 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1334787 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1622621 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7390556 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39458944 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 84672718 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 32025024 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 62527373 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 218684059 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 464381 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 5618153 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.076464 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.265739 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 3383928 98.78% 98.78% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 41765 1.22% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 5188566 92.35% 92.35% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 429587 7.65% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3425693 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2521355915 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 243000 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 5618153 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3461836914 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 240000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1371805405 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2024294017 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 925515973 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 1363977262 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 318303496 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 751744303 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 173244936 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 856189885 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2154,171 +2174,161 @@ system.tsunami.ethernet.coalescedTotal nan # av system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6519 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 185119 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 65685 40.48% 40.48% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 132 0.08% 40.56% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1924 1.19% 41.75% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 154 0.09% 41.84% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 94359 58.16% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 162254 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 64617 49.22% 49.22% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 132 0.10% 49.32% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1924 1.47% 50.78% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 154 0.12% 50.90% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 64464 49.10% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 131291 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1861341200000 97.74% 97.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 60253000 0.00% 97.75% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 540538500 0.03% 97.78% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 69963500 0.00% 97.78% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 42290129000 2.22% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1904302084000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.983741 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 4815 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 139340 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 45519 38.89% 38.89% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 133 0.11% 39.01% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1927 1.65% 40.65% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 16 0.01% 40.67% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 69446 59.33% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 117041 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 44932 48.88% 48.88% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 133 0.14% 49.02% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1927 2.10% 51.12% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 16 0.02% 51.14% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 44917 48.86% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 91925 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1870471244000 98.03% 98.03% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 61392000 0.00% 98.04% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 548913500 0.03% 98.07% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 8511500 0.00% 98.07% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 36889187000 1.93% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1907979248000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.987104 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.683178 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.809170 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 6 2.79% 2.79% # number of syscalls executed -system.cpu0.kern.syscall::3 18 8.37% 11.16% # number of syscalls executed -system.cpu0.kern.syscall::4 3 1.40% 12.56% # number of syscalls executed -system.cpu0.kern.syscall::6 29 13.49% 26.05% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.47% 26.51% # number of syscalls executed -system.cpu0.kern.syscall::15 1 0.47% 26.98% # number of syscalls executed -system.cpu0.kern.syscall::17 9 4.19% 31.16% # number of syscalls executed -system.cpu0.kern.syscall::19 6 2.79% 33.95% # number of syscalls executed -system.cpu0.kern.syscall::20 4 1.86% 35.81% # number of syscalls executed -system.cpu0.kern.syscall::23 2 0.93% 36.74% # number of syscalls executed -system.cpu0.kern.syscall::24 4 1.86% 38.60% # number of syscalls executed -system.cpu0.kern.syscall::33 7 3.26% 41.86% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.93% 42.79% # number of syscalls executed -system.cpu0.kern.syscall::45 35 16.28% 59.07% # number of syscalls executed -system.cpu0.kern.syscall::47 4 1.86% 60.93% # number of syscalls executed -system.cpu0.kern.syscall::48 7 3.26% 64.19% # number of syscalls executed -system.cpu0.kern.syscall::54 9 4.19% 68.37% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.47% 68.84% # number of syscalls executed -system.cpu0.kern.syscall::59 5 2.33% 71.16% # number of syscalls executed -system.cpu0.kern.syscall::71 32 14.88% 86.05% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.40% 87.44% # number of syscalls executed -system.cpu0.kern.syscall::74 9 4.19% 91.63% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.47% 92.09% # number of syscalls executed -system.cpu0.kern.syscall::90 1 0.47% 92.56% # number of syscalls executed -system.cpu0.kern.syscall::92 7 3.26% 95.81% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.93% 96.74% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.93% 97.67% # number of syscalls executed -system.cpu0.kern.syscall::132 2 0.93% 98.60% # number of syscalls executed -system.cpu0.kern.syscall::144 1 0.47% 99.07% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.93% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 215 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.646790 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.785409 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 8 3.56% 3.56% # number of syscalls executed +system.cpu0.kern.syscall::3 19 8.44% 12.00% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.78% 13.78% # number of syscalls executed +system.cpu0.kern.syscall::6 33 14.67% 28.44% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.44% 28.89% # number of syscalls executed +system.cpu0.kern.syscall::17 9 4.00% 32.89% # number of syscalls executed +system.cpu0.kern.syscall::19 10 4.44% 37.33% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.67% 40.00% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.44% 40.44% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.33% 41.78% # number of syscalls executed +system.cpu0.kern.syscall::33 7 3.11% 44.89% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.89% 45.78% # number of syscalls executed +system.cpu0.kern.syscall::45 36 16.00% 61.78% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.33% 63.11% # number of syscalls executed +system.cpu0.kern.syscall::48 10 4.44% 67.56% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.44% 72.00% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.44% 72.44% # number of syscalls executed +system.cpu0.kern.syscall::59 6 2.67% 75.11% # number of syscalls executed +system.cpu0.kern.syscall::71 25 11.11% 86.22% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.33% 87.56% # number of syscalls executed +system.cpu0.kern.syscall::74 6 2.67% 90.22% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.44% 90.67% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.33% 92.00% # number of syscalls executed +system.cpu0.kern.syscall::92 9 4.00% 96.00% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.89% 96.89% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.89% 97.78% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.44% 98.22% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.89% 99.11% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.89% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 225 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 255 0.15% 0.15% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.15% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.15% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.15% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3502 2.05% 2.20% # number of callpals executed -system.cpu0.kern.callpal::tbi 43 0.03% 2.23% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.23% # number of callpals executed -system.cpu0.kern.callpal::swpipl 155594 91.14% 93.38% # number of callpals executed -system.cpu0.kern.callpal::rdps 6351 3.72% 97.10% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.10% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 97.10% # number of callpals executed -system.cpu0.kern.callpal::rdusp 7 0.00% 97.10% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.10% # number of callpals executed -system.cpu0.kern.callpal::rti 4450 2.61% 99.71% # number of callpals executed -system.cpu0.kern.callpal::callsys 347 0.20% 99.91% # number of callpals executed -system.cpu0.kern.callpal::imb 148 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 170714 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6908 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1181 # number of protection mode switches +system.cpu0.kern.callpal::wripir 104 0.08% 0.08% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.09% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.09% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.09% # number of callpals executed +system.cpu0.kern.callpal::swpctx 2293 1.85% 1.93% # number of callpals executed +system.cpu0.kern.callpal::tbi 50 0.04% 1.97% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.01% 1.98% # number of callpals executed +system.cpu0.kern.callpal::swpipl 110963 89.30% 91.28% # number of callpals executed +system.cpu0.kern.callpal::rdps 6296 5.07% 96.35% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.35% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.35% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.36% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.36% # number of callpals executed +system.cpu0.kern.callpal::rti 4002 3.22% 99.58% # number of callpals executed +system.cpu0.kern.callpal::callsys 382 0.31% 99.89% # number of callpals executed +system.cpu0.kern.callpal::imb 138 0.11% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 124254 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 5723 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1342 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1181 -system.cpu0.kern.mode_good::user 1181 +system.cpu0.kern.mode_good::kernel 1341 +system.cpu0.kern.mode_good::user 1342 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.170961 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.234318 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.292001 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1901823094000 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1927479500 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.379759 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1905987592000 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1991648000 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3503 # number of times the context was actually changed +system.cpu0.kern.swap_context 2294 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2448 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 54000 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 16487 36.42% 36.42% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1922 4.25% 40.66% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 255 0.56% 41.23% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 26607 58.77% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 45271 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 16178 47.20% 47.20% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1922 5.61% 52.80% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 255 0.74% 53.55% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 15923 46.45% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 34278 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1872287559000 98.31% 98.31% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 533777500 0.03% 98.34% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 116465000 0.01% 98.35% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 31498958000 1.65% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1904436759500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.981258 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 3855 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 98215 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 36112 40.36% 40.36% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1925 2.15% 42.52% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 104 0.12% 42.63% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 51325 57.37% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 89466 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 35322 48.67% 48.67% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1925 2.65% 51.33% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 104 0.14% 51.47% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 35218 48.53% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 72569 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1870768654000 98.07% 98.07% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 540231000 0.03% 98.10% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 48911000 0.00% 98.10% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 36277143500 1.90% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1907634939500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.978124 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.598452 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.757173 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::2 2 1.80% 1.80% # number of syscalls executed -system.cpu1.kern.syscall::3 12 10.81% 12.61% # number of syscalls executed -system.cpu1.kern.syscall::4 1 0.90% 13.51% # number of syscalls executed -system.cpu1.kern.syscall::6 13 11.71% 25.23% # number of syscalls executed -system.cpu1.kern.syscall::17 6 5.41% 30.63% # number of syscalls executed -system.cpu1.kern.syscall::19 4 3.60% 34.23% # number of syscalls executed -system.cpu1.kern.syscall::20 2 1.80% 36.04% # number of syscalls executed -system.cpu1.kern.syscall::23 2 1.80% 37.84% # number of syscalls executed -system.cpu1.kern.syscall::24 2 1.80% 39.64% # number of syscalls executed -system.cpu1.kern.syscall::33 4 3.60% 43.24% # number of syscalls executed -system.cpu1.kern.syscall::45 19 17.12% 60.36% # number of syscalls executed -system.cpu1.kern.syscall::47 2 1.80% 62.16% # number of syscalls executed -system.cpu1.kern.syscall::48 3 2.70% 64.86% # number of syscalls executed -system.cpu1.kern.syscall::54 1 0.90% 65.77% # number of syscalls executed -system.cpu1.kern.syscall::59 2 1.80% 67.57% # number of syscalls executed -system.cpu1.kern.syscall::71 22 19.82% 87.39% # number of syscalls executed -system.cpu1.kern.syscall::74 7 6.31% 93.69% # number of syscalls executed -system.cpu1.kern.syscall::90 2 1.80% 95.50% # number of syscalls executed -system.cpu1.kern.syscall::92 2 1.80% 97.30% # number of syscalls executed -system.cpu1.kern.syscall::132 2 1.80% 99.10% # number of syscalls executed -system.cpu1.kern.syscall::144 1 0.90% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 111 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.686176 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.811135 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::3 11 10.89% 10.89% # number of syscalls executed +system.cpu1.kern.syscall::6 9 8.91% 19.80% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.99% 20.79% # number of syscalls executed +system.cpu1.kern.syscall::17 6 5.94% 26.73% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.97% 29.70% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.97% 32.67% # number of syscalls executed +system.cpu1.kern.syscall::33 4 3.96% 36.63% # number of syscalls executed +system.cpu1.kern.syscall::45 18 17.82% 54.46% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.97% 57.43% # number of syscalls executed +system.cpu1.kern.syscall::59 1 0.99% 58.42% # number of syscalls executed +system.cpu1.kern.syscall::71 29 28.71% 87.13% # number of syscalls executed +system.cpu1.kern.syscall::74 10 9.90% 97.03% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.97% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 101 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 154 0.33% 0.33% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.33% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.33% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1023 2.18% 2.52% # number of callpals executed -system.cpu1.kern.callpal::tbi 10 0.02% 2.54% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.55% # number of callpals executed -system.cpu1.kern.callpal::swpipl 40053 85.39% 87.95% # number of callpals executed -system.cpu1.kern.callpal::rdps 2403 5.12% 93.07% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.07% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 93.08% # number of callpals executed -system.cpu1.kern.callpal::rdusp 2 0.00% 93.08% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 93.09% # number of callpals executed -system.cpu1.kern.callpal::rti 3040 6.48% 99.57% # number of callpals executed -system.cpu1.kern.callpal::callsys 168 0.36% 99.93% # number of callpals executed -system.cpu1.kern.callpal::imb 32 0.07% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 16 0.02% 0.02% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.02% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.02% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1949 2.12% 2.14% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 2.14% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.15% # number of callpals executed +system.cpu1.kern.callpal::swpipl 84230 91.49% 93.64% # number of callpals executed +system.cpu1.kern.callpal::rdps 2466 2.68% 96.32% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 96.32% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.00% 96.32% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 96.33% # number of callpals executed +system.cpu1.kern.callpal::rti 3206 3.48% 99.81% # number of callpals executed +system.cpu1.kern.callpal::callsys 133 0.14% 99.95% # number of callpals executed +system.cpu1.kern.callpal::imb 42 0.05% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 46904 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1413 # number of protection mode switches -system.cpu1.kern.mode_switch::user 554 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2352 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 733 -system.cpu1.kern.mode_good::user 554 -system.cpu1.kern.mode_good::idle 179 -system.cpu1.kern.mode_switch_good::kernel 0.518754 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 92064 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 2331 # number of protection mode switches +system.cpu1.kern.mode_switch::user 395 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2054 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 461 +system.cpu1.kern.mode_good::user 395 +system.cpu1.kern.mode_good::idle 66 +system.cpu1.kern.mode_switch_good::kernel 0.197769 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.076105 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.339430 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 4023798000 0.21% 0.21% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 775821000 0.04% 0.25% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1899637132500 99.75% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1024 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.032132 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.192887 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 42837305000 2.25% 2.25% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 697376000 0.04% 2.28% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1863790118000 97.72% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1950 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 038a204b1..156f5647f 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,112 +1,112 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.861006 # Number of seconds simulated -sim_ticks 1861005569500 # Number of ticks simulated -final_tick 1861005569500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.861005 # Number of seconds simulated +sim_ticks 1861005347500 # Number of ticks simulated +final_tick 1861005347500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 152837 # Simulator instruction rate (inst/s) -host_op_rate 152837 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5373256396 # Simulator tick rate (ticks/s) -host_mem_usage 376300 # Number of bytes of host memory used -host_seconds 346.35 # Real time elapsed on the host -sim_insts 52934565 # Number of instructions simulated -sim_ops 52934565 # Number of ops (including micro ops) simulated +host_inst_rate 149955 # Simulator instruction rate (inst/s) +host_op_rate 149955 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5267476367 # Simulator tick rate (ticks/s) +host_mem_usage 376564 # Number of bytes of host memory used +host_seconds 353.30 # Real time elapsed on the host +sim_insts 52979113 # Number of instructions simulated +sim_ops 52979113 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 968000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24876864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 965824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24879488 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25845824 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 968000 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 968000 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7517248 # Number of bytes written to this memory -system.physmem.bytes_written::total 7517248 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15125 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388701 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25846272 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 965824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 965824 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7524416 # Number of bytes written to this memory +system.physmem.bytes_written::total 7524416 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15091 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388742 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 403841 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117457 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117457 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 520149 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13367431 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 403848 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117569 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117569 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 518980 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13368843 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 516 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13888096 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 520149 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 520149 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4039347 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4039347 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4039347 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 520149 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13367431 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13888338 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 518980 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 518980 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4043200 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4043200 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4043200 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 518980 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13368843 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17927443 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 403841 # Number of read requests accepted -system.physmem.writeReqs 159009 # Number of write requests accepted -system.physmem.readBursts 403841 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 159009 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bw_total::total 17931538 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 403848 # Number of read requests accepted +system.physmem.writeReqs 117569 # Number of write requests accepted +system.physmem.readBursts 403848 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 117569 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 25839488 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6336 # Total number of bytes read from write queue -system.physmem.bytesWritten 8519424 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25845824 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10176576 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 99 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 25870 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 189 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25748 # Per bank write bursts -system.physmem.perBankRdBursts::1 25559 # Per bank write bursts -system.physmem.perBankRdBursts::2 25508 # Per bank write bursts -system.physmem.perBankRdBursts::3 25346 # Per bank write bursts -system.physmem.perBankRdBursts::4 25393 # Per bank write bursts -system.physmem.perBankRdBursts::5 24806 # Per bank write bursts -system.physmem.perBankRdBursts::6 25027 # Per bank write bursts -system.physmem.perBankRdBursts::7 25127 # Per bank write bursts -system.physmem.perBankRdBursts::8 24925 # Per bank write bursts -system.physmem.perBankRdBursts::9 25034 # Per bank write bursts -system.physmem.perBankRdBursts::10 25436 # Per bank write bursts -system.physmem.perBankRdBursts::11 24774 # Per bank write bursts -system.physmem.perBankRdBursts::12 24551 # Per bank write bursts -system.physmem.perBankRdBursts::13 25233 # Per bank write bursts -system.physmem.perBankRdBursts::14 25663 # Per bank write bursts -system.physmem.perBankRdBursts::15 25612 # Per bank write bursts -system.physmem.perBankWrBursts::0 9148 # Per bank write bursts -system.physmem.perBankWrBursts::1 8514 # Per bank write bursts -system.physmem.perBankWrBursts::2 8998 # Per bank write bursts -system.physmem.perBankWrBursts::3 8298 # Per bank write bursts -system.physmem.perBankWrBursts::4 8214 # Per bank write bursts -system.physmem.perBankWrBursts::5 7705 # Per bank write bursts -system.physmem.perBankWrBursts::6 7696 # Per bank write bursts -system.physmem.perBankWrBursts::7 7707 # Per bank write bursts -system.physmem.perBankWrBursts::8 8055 # Per bank write bursts -system.physmem.perBankWrBursts::9 7602 # Per bank write bursts -system.physmem.perBankWrBursts::10 8149 # Per bank write bursts -system.physmem.perBankWrBursts::11 7799 # Per bank write bursts -system.physmem.perBankWrBursts::12 8377 # Per bank write bursts -system.physmem.perBankWrBursts::13 9062 # Per bank write bursts -system.physmem.perBankWrBursts::14 8903 # Per bank write bursts -system.physmem.perBankWrBursts::15 8889 # Per bank write bursts +system.physmem.bytesReadWrQ 6784 # Total number of bytes read from write queue +system.physmem.bytesWritten 7523328 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25846272 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7524416 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 106 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 41759 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25651 # Per bank write bursts +system.physmem.perBankRdBursts::1 25422 # Per bank write bursts +system.physmem.perBankRdBursts::2 25567 # Per bank write bursts +system.physmem.perBankRdBursts::3 25497 # Per bank write bursts +system.physmem.perBankRdBursts::4 25384 # Per bank write bursts +system.physmem.perBankRdBursts::5 24734 # Per bank write bursts +system.physmem.perBankRdBursts::6 24943 # Per bank write bursts +system.physmem.perBankRdBursts::7 25079 # Per bank write bursts +system.physmem.perBankRdBursts::8 24928 # Per bank write bursts +system.physmem.perBankRdBursts::9 25027 # Per bank write bursts +system.physmem.perBankRdBursts::10 25572 # Per bank write bursts +system.physmem.perBankRdBursts::11 24872 # Per bank write bursts +system.physmem.perBankRdBursts::12 24489 # Per bank write bursts +system.physmem.perBankRdBursts::13 25240 # Per bank write bursts +system.physmem.perBankRdBursts::14 25741 # Per bank write bursts +system.physmem.perBankRdBursts::15 25596 # Per bank write bursts +system.physmem.perBankWrBursts::0 7944 # Per bank write bursts +system.physmem.perBankWrBursts::1 7514 # Per bank write bursts +system.physmem.perBankWrBursts::2 7965 # Per bank write bursts +system.physmem.perBankWrBursts::3 7518 # Per bank write bursts +system.physmem.perBankWrBursts::4 7330 # Per bank write bursts +system.physmem.perBankWrBursts::5 6666 # Per bank write bursts +system.physmem.perBankWrBursts::6 6776 # Per bank write bursts +system.physmem.perBankWrBursts::7 6716 # Per bank write bursts +system.physmem.perBankWrBursts::8 7141 # Per bank write bursts +system.physmem.perBankWrBursts::9 6711 # Per bank write bursts +system.physmem.perBankWrBursts::10 7422 # Per bank write bursts +system.physmem.perBankWrBursts::11 6968 # Per bank write bursts +system.physmem.perBankWrBursts::12 7145 # Per bank write bursts +system.physmem.perBankWrBursts::13 7857 # Per bank write bursts +system.physmem.perBankWrBursts::14 8054 # Per bank write bursts +system.physmem.perBankWrBursts::15 7825 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 85 # Number of times write queue was full causing retry -system.physmem.totGap 1861000236500 # Total gap between requests +system.physmem.numWrRetry 23 # Number of times write queue was full causing retry +system.physmem.totGap 1860999975500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 403841 # Read request sizes (log2) +system.physmem.readPktSize::6 403848 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 159009 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 314763 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 36627 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 28957 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 23318 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117569 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 314964 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 36182 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 28364 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 24147 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 67 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see @@ -148,199 +148,190 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4827 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5591 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5498 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5482 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5462 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5789 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5773 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6965 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9031 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7006 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6948 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5988 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1703 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1519 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1726 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 2145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1965 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 2231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 2575 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 2937 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1790 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 722 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 404 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 323 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62685 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 548.114030 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 339.010384 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 417.134053 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13424 21.42% 21.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10425 16.63% 38.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5386 8.59% 46.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2710 4.32% 50.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2462 3.93% 54.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1644 2.62% 57.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1512 2.41% 59.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1300 2.07% 62.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 23822 38.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62685 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4847 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 83.295234 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 3032.862596 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 4844 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1537 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1938 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3666 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4711 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7065 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9566 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8780 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7660 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8572 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8387 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5838 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 339 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 41 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 61779 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 540.028683 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 331.823835 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 416.833229 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13638 22.08% 22.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10412 16.85% 38.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4989 8.08% 47.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3229 5.23% 52.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2263 3.66% 55.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1516 2.45% 58.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1526 2.47% 60.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1289 2.09% 62.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22917 37.10% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 61779 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5213 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 77.447919 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2924.392219 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5210 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4847 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4847 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.463586 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.516932 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 62.014286 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 4601 94.92% 94.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 56 1.16% 96.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 4 0.08% 96.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 1 0.02% 96.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 13 0.27% 96.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 3 0.06% 96.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 3 0.06% 96.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 6 0.12% 96.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 21 0.43% 97.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 18 0.37% 97.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 8 0.17% 97.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 12 0.25% 97.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 2 0.04% 97.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 4 0.08% 98.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 1 0.02% 98.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 2 0.04% 98.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 5 0.10% 98.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 17 0.35% 98.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 13 0.27% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 3 0.06% 98.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 11 0.23% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 4 0.08% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::432-447 2 0.04% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::448-463 2 0.04% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::464-479 4 0.08% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 4 0.08% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 4 0.08% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 2 0.04% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 2 0.04% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 8 0.17% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::560-575 2 0.04% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::624-639 2 0.04% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::640-655 2 0.04% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::656-671 1 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::688-703 2 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::704-719 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::720-735 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4847 # Writes before turning the bus around for reads -system.physmem.totQLat 3741904500 # Total ticks spent queuing -system.physmem.totMemAccLat 11312067000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.rdPerTurnAround::total 5213 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5213 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.549779 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.928650 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 23.456391 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4618 88.59% 88.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 208 3.99% 92.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 74 1.42% 94.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 17 0.33% 94.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 8 0.15% 94.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 5 0.10% 94.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 10 0.19% 94.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 10 0.19% 94.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 7 0.13% 95.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 32 0.61% 95.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 168 3.22% 98.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 10 0.19% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 2 0.04% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 5 0.10% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 2 0.04% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 1 0.02% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 2 0.04% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 3 0.06% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 2 0.04% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 5 0.10% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 3 0.06% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 4 0.08% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 1 0.02% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 1 0.02% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 1 0.02% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 12 0.23% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5213 # Writes before turning the bus around for reads +system.physmem.totQLat 3805918000 # Total ticks spent queuing +system.physmem.totMemAccLat 11376080500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2018710000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9268.06 # Average queueing delay per DRAM burst +system.physmem.avgQLat 9426.61 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28018.06 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28176.61 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.88 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.58 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.89 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 5.47 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.04 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.48 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.77 # Average write queue length when enqueuing -system.physmem.readRowHits 364326 # Number of row buffer hits during reads -system.physmem.writeRowHits 109846 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.24 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 82.50 # Row buffer hit rate for writes -system.physmem.avgGap 3306387.56 # Average gap between requests -system.physmem.pageHitRate 88.32 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 235516680 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 128506125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1579609200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 429494400 # Energy for write commands per rank (pJ) +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.30 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.54 # Average write queue length when enqueuing +system.physmem.readRowHits 364169 # Number of row buffer hits during reads +system.physmem.writeRowHits 95345 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.20 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 81.10 # Row buffer hit rate for writes +system.physmem.avgGap 3569120.25 # Average gap between requests +system.physmem.pageHitRate 88.15 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 232515360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 126868500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1577760600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 378619920 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 121551434160 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 56182721175 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1067316698250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1247423979990 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.297807 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1775410357162 # Time in different power states +system.physmem_0.actBackEnergy 56250477360 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1067257263000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1247374938900 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.271455 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1775312455750 # Time in different power states system.physmem_0.memoryStateTime::REF 62142860000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 23446441588 # Time in different power states +system.physmem_0.memoryStateTime::ACT 23544343000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 238381920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 130069500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1569531600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 433097280 # Energy for write commands per rank (pJ) +system.physmem_1.actEnergy 234533880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 127969875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1571380200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 383117040 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 121551434160 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 56034129015 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1067447050500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1247403693975 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.286901 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1775626000168 # Time in different power states +system.physmem_1.actBackEnergy 55982569095 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1067492278500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1247343282750 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.254439 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1775708219250 # Time in different power states system.physmem_1.memoryStateTime::REF 62142860000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 23231077332 # Time in different power states +system.physmem_1.memoryStateTime::ACT 23148593250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 17721924 # Number of BP lookups -system.cpu.branchPred.condPredicted 15403228 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 380344 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11703979 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5913014 # Number of BTB hits +system.cpu.branchPred.lookups 17721018 # Number of BP lookups +system.cpu.branchPred.condPredicted 15408782 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 378784 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 12470436 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5897235 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 50.521400 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 923784 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 21447 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 47.289726 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 918220 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 21032 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 10269214 # DTB read hits -system.cpu.dtb.read_misses 41261 # DTB read misses -system.cpu.dtb.read_acv 507 # DTB read access violations -system.cpu.dtb.read_accesses 967301 # DTB read accesses -system.cpu.dtb.write_hits 6648637 # DTB write hits -system.cpu.dtb.write_misses 9303 # DTB write misses -system.cpu.dtb.write_acv 402 # DTB write access violations -system.cpu.dtb.write_accesses 342644 # DTB write accesses -system.cpu.dtb.data_hits 16917851 # DTB hits -system.cpu.dtb.data_misses 50564 # DTB misses -system.cpu.dtb.data_acv 909 # DTB access violations -system.cpu.dtb.data_accesses 1309945 # DTB accesses -system.cpu.itb.fetch_hits 1769158 # ITB hits -system.cpu.itb.fetch_misses 36068 # ITB misses -system.cpu.itb.fetch_acv 660 # ITB acv -system.cpu.itb.fetch_accesses 1805226 # ITB accesses +system.cpu.dtb.read_hits 10294388 # DTB read hits +system.cpu.dtb.read_misses 42024 # DTB read misses +system.cpu.dtb.read_acv 506 # DTB read access violations +system.cpu.dtb.read_accesses 968687 # DTB read accesses +system.cpu.dtb.write_hits 6648521 # DTB write hits +system.cpu.dtb.write_misses 9456 # DTB write misses +system.cpu.dtb.write_acv 408 # DTB write access violations +system.cpu.dtb.write_accesses 343243 # DTB write accesses +system.cpu.dtb.data_hits 16942909 # DTB hits +system.cpu.dtb.data_misses 51480 # DTB misses +system.cpu.dtb.data_acv 914 # DTB access violations +system.cpu.dtb.data_accesses 1311930 # DTB accesses +system.cpu.itb.fetch_hits 1769476 # ITB hits +system.cpu.itb.fetch_misses 36155 # ITB misses +system.cpu.itb.fetch_acv 662 # ITB acv +system.cpu.itb.fetch_accesses 1805631 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -353,258 +344,258 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 122572361 # number of cpu cycles simulated +system.cpu.numCycles 122272854 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29541441 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 78093998 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17721924 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6836798 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 84630340 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1254210 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 1349 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 26888 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1745325 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 441267 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 294 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9051182 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 273719 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 117014009 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.667390 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.979034 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29542399 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 77951342 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17721018 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6815455 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 84318662 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1251172 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 1032 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 27002 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1751503 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 450615 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 220 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9037094 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 274713 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 116717019 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.667866 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.979948 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 102427448 87.53% 87.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 934169 0.80% 88.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1984138 1.70% 90.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 910061 0.78% 90.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2793690 2.39% 93.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 647956 0.55% 93.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 739168 0.63% 94.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1007210 0.86% 95.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 5570169 4.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 102159840 87.53% 87.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 935001 0.80% 88.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1975635 1.69% 90.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 907890 0.78% 90.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2798283 2.40% 93.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 634657 0.54% 93.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 731012 0.63% 94.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1008696 0.86% 95.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 5566005 4.77% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 117014009 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.144583 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.637126 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 24038562 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 80987042 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 9497307 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1906242 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 584855 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 586733 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42672 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 68295720 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 134238 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 584855 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 24961940 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 51456440 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 20841952 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 10391328 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8777492 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 65857652 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 204161 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2078785 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 153522 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4578470 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 43917673 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 79850033 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79669145 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 168436 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38142428 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5775237 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1690640 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 240974 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13460579 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10430513 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6961741 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1496363 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1107333 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58622970 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2136022 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 57539781 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 62715 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7824422 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3554737 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1474907 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 117014009 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.491734 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.229968 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 116717019 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.144930 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.637520 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 24051579 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 80690981 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 9487535 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1903773 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 583150 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 586842 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42848 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 68182155 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 134674 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 583150 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 24974215 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 50913599 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 20868972 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 10381558 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8995523 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65764072 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 201455 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2078667 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 157006 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4811107 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 43858088 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79749030 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79568293 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 168286 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38179356 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5678724 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1691117 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 241700 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13523739 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10414999 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6951257 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1489090 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1076371 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58557437 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2137330 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 57550552 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 58383 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7715649 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3482179 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1476201 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 116717019 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.493078 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.231262 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 93391037 79.81% 79.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10179390 8.70% 88.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 4310458 3.68% 92.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3008329 2.57% 94.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 3082993 2.63% 97.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1515380 1.30% 98.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1001151 0.86% 99.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 403458 0.34% 99.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 121813 0.10% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 93076852 79.75% 79.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10193735 8.73% 88.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 4312708 3.70% 92.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3021195 2.59% 94.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 3081764 2.64% 97.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1495449 1.28% 98.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1007889 0.86% 99.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 403235 0.35% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 124192 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 117014009 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 116717019 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 210088 18.84% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 537781 48.22% 67.06% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 367354 32.94% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 208462 18.43% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 547266 48.38% 66.81% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 375475 33.19% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 39070075 67.90% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61902 0.11% 68.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 38396 0.07% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10678994 18.56% 86.65% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6730550 11.70% 98.35% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 948942 1.65% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 39056911 67.87% 67.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61891 0.11% 67.99% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 38552 0.07% 68.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10704988 18.60% 86.66% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6728388 11.69% 98.35% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 948900 1.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 57539781 # Type of FU issued -system.cpu.iq.rate 0.469435 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1115223 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019382 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 232558248 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 68266797 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55883323 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 713260 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 336497 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 329169 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 58264569 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 383149 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 636979 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 57550552 # Type of FU issued +system.cpu.iq.rate 0.470673 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1131203 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019656 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 232294841 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 68093775 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55871823 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 712867 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 336544 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 329026 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 58291729 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 382740 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 634925 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1345105 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3404 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 20302 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 587155 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1322411 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3516 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 20331 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 573217 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 18243 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 442853 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 18302 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 483316 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 584855 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 48003305 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1105875 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 64465821 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 144286 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10430513 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6961741 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1886655 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 45598 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 856452 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 20302 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 189944 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 410798 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 600742 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56947023 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10338131 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 592757 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 583150 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 47678109 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 871068 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 64398227 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 142430 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10414999 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6951257 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1888726 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 44438 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 623782 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 20331 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 186400 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 411798 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 598198 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56961347 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10364061 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 589204 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3706829 # number of nop insts executed -system.cpu.iew.exec_refs 17011176 # number of memory reference insts executed -system.cpu.iew.exec_branches 8976912 # Number of branches executed -system.cpu.iew.exec_stores 6673045 # Number of stores executed -system.cpu.iew.exec_rate 0.464599 # Inst execution rate -system.cpu.iew.wb_sent 56353404 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56212492 # cumulative count of insts written-back -system.cpu.iew.wb_producers 28792537 # num instructions producing a value -system.cpu.iew.wb_consumers 40027235 # num instructions consuming a value +system.cpu.iew.exec_nop 3703460 # number of nop insts executed +system.cpu.iew.exec_refs 17037134 # number of memory reference insts executed +system.cpu.iew.exec_branches 8968929 # Number of branches executed +system.cpu.iew.exec_stores 6673073 # Number of stores executed +system.cpu.iew.exec_rate 0.465854 # Inst execution rate +system.cpu.iew.wb_sent 56337909 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56200849 # cumulative count of insts written-back +system.cpu.iew.wb_producers 28756133 # num instructions producing a value +system.cpu.iew.wb_consumers 39912635 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.458607 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.719324 # average fanout of values written-back +system.cpu.iew.wb_rate 0.459635 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.720477 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8228560 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 661115 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 549076 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 115576332 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.485596 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.428292 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 8112704 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 661129 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 547326 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 115294268 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.487187 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.430320 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 95814381 82.90% 82.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7848857 6.79% 89.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4272055 3.70% 93.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2211253 1.91% 95.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1764306 1.53% 96.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 615369 0.53% 97.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 473669 0.41% 97.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 490996 0.42% 98.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2085446 1.80% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 95501177 82.83% 82.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7867272 6.82% 89.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4280982 3.71% 93.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2233083 1.94% 95.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1745854 1.51% 96.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 611445 0.53% 97.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 482985 0.42% 97.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 468960 0.41% 98.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2102510 1.82% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 115576332 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56123349 # Number of instructions committed -system.cpu.commit.committedOps 56123349 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 115294268 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56169836 # Number of instructions committed +system.cpu.commit.committedOps 56169836 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15459994 # Number of memory references committed -system.cpu.commit.loads 9085408 # Number of loads committed -system.cpu.commit.membars 226308 # Number of memory barriers committed -system.cpu.commit.branches 8435685 # Number of branches committed -system.cpu.commit.fp_insts 324451 # Number of committed floating point instructions. -system.cpu.commit.int_insts 51974864 # Number of committed integer instructions. -system.cpu.commit.function_calls 740049 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 3196057 5.69% 5.69% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 36183700 64.47% 70.17% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 60673 0.11% 70.27% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.27% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 38087 0.07% 70.34% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.34% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.34% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.34% # Class of committed instruction +system.cpu.commit.refs 15470628 # Number of memory references committed +system.cpu.commit.loads 9092588 # Number of loads committed +system.cpu.commit.membars 226333 # Number of memory barriers committed +system.cpu.commit.branches 8440353 # Number of branches committed +system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. +system.cpu.commit.int_insts 52019375 # Number of committed integer instructions. +system.cpu.commit.function_calls 740552 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 3197996 5.69% 5.69% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 36217639 64.48% 70.17% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 60667 0.11% 70.28% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 38085 0.07% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction @@ -627,411 +618,417 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 9311716 16.59% 86.94% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 6380538 11.37% 98.31% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 948942 1.69% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 9318921 16.59% 86.95% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 6383992 11.37% 98.31% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 948900 1.69% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 56123349 # Class of committed instruction -system.cpu.commit.bw_lim_events 2085446 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 177593268 # The number of ROB reads -system.cpu.rob.rob_writes 130137832 # The number of ROB writes -system.cpu.timesIdled 572499 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5558352 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3599438779 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52934565 # Number of Instructions Simulated -system.cpu.committedOps 52934565 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.315545 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.315545 # CPI: Total CPI of All Threads -system.cpu.ipc 0.431864 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.431864 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 74599299 # number of integer regfile reads -system.cpu.int_regfile_writes 40560409 # number of integer regfile writes -system.cpu.fp_regfile_reads 167171 # number of floating regfile reads -system.cpu.fp_regfile_writes 167579 # number of floating regfile writes -system.cpu.misc_regfile_reads 2029670 # number of misc regfile reads -system.cpu.misc_regfile_writes 939349 # number of misc regfile writes -system.cpu.dcache.tags.replacements 1403663 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.994456 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 11858482 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1404175 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.445160 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 26416000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.994456 # Average occupied blocks per requestor +system.cpu.commit.op_class_0::total 56169836 # Class of committed instruction +system.cpu.commit.bw_lim_events 2102510 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 177224791 # The number of ROB reads +system.cpu.rob.rob_writes 129983616 # The number of ROB writes +system.cpu.timesIdled 573073 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5555835 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3599737842 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52979113 # Number of Instructions Simulated +system.cpu.committedOps 52979113 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.307945 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.307945 # CPI: Total CPI of All Threads +system.cpu.ipc 0.433286 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.433286 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 74622251 # number of integer regfile reads +system.cpu.int_regfile_writes 40551917 # number of integer regfile writes +system.cpu.fp_regfile_reads 167069 # number of floating regfile reads +system.cpu.fp_regfile_writes 167545 # number of floating regfile writes +system.cpu.misc_regfile_reads 2028916 # number of misc regfile reads +system.cpu.misc_regfile_writes 939321 # number of misc regfile writes +system.cpu.dcache.tags.replacements 1404299 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.994455 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 11844191 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1404811 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.431163 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 26393500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.994455 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 413 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 412 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63936372 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63936372 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7267066 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7267066 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4189300 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4189300 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 186111 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 186111 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 215710 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 215710 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 11456366 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11456366 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 11456366 # number of overall hits -system.cpu.dcache.overall_hits::total 11456366 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1796718 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1796718 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1954848 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1954848 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 23269 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 23269 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 27 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 27 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3751566 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3751566 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3751566 # number of overall misses -system.cpu.dcache.overall_misses::total 3751566 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 41841354315 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 41841354315 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 80890725520 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 80890725520 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 376182249 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 376182249 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 455005 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 455005 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 122732079835 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 122732079835 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 122732079835 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 122732079835 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9063784 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9063784 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6144148 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6144148 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209380 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 209380 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 215737 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 215737 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15207932 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15207932 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15207932 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15207932 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.198230 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.198230 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318164 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.318164 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.111133 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.111133 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000125 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000125 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.246685 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.246685 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.246685 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.246685 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23287.658005 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 23287.658005 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41379.547423 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41379.547423 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16166.670205 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16166.670205 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16852.037037 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16852.037037 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 32714.892883 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 32714.892883 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32714.892883 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 32714.892883 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 4477894 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2036 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 123579 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 23 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.235072 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 88.521739 # average number of cycles each access was blocked +system.cpu.dcache.tags.tag_accesses 63926076 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63926076 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7252822 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7252822 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4188714 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4188714 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 186644 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 186644 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 215706 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 215706 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 11441536 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 11441536 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 11441536 # number of overall hits +system.cpu.dcache.overall_hits::total 11441536 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1804157 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1804157 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1958890 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1958890 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 23354 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 23354 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 29 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 29 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3763047 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3763047 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3763047 # number of overall misses +system.cpu.dcache.overall_misses::total 3763047 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 41750233000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 41750233000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 80527676066 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 80527676066 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 377889000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 377889000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 498500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 498500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 122277909066 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 122277909066 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 122277909066 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 122277909066 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9056979 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9056979 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6147604 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6147604 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209998 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 209998 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 215735 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 215735 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15204583 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15204583 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15204583 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15204583 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.199201 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.199201 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318643 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.318643 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.111211 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.111211 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000134 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000134 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.247494 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.247494 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.247494 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.247494 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23141.130733 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 23141.130733 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41108.830034 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41108.830034 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16180.911193 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16180.911193 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 17189.655172 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 17189.655172 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32494.387943 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32494.387943 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32494.387943 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32494.387943 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4529793 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2677 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 135335 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 25 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 33.470965 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 107.080000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 842087 # number of writebacks -system.cpu.dcache.writebacks::total 842087 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 701160 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 701160 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1664055 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1664055 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5272 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5272 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2365215 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2365215 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2365215 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2365215 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1095558 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1095558 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290793 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 290793 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17997 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17997 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 27 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 27 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1386351 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1386351 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1386351 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1386351 # number of overall MSHR misses +system.cpu.dcache.writebacks::writebacks 842762 # number of writebacks +system.cpu.dcache.writebacks::total 842762 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 708195 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 708195 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1668077 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1668077 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5151 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5151 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2376272 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2376272 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2376272 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2376272 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1095962 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1095962 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290813 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 290813 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18203 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 18203 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 29 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 29 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1386775 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1386775 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1386775 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1386775 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9597 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 9597 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16527 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 16527 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29996933023 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 29996933023 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12482529124 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12482529124 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 214354001 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 214354001 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 414495 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 414495 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 42479462147 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 42479462147 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 42479462147 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 42479462147 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1433706500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1433706500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011966000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011966000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3445672500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3445672500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120872 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120872 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047328 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047328 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085954 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085954 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000125 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000125 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091160 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091160 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091160 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091160 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27380.506576 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27380.506576 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42925.823950 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42925.823950 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11910.540701 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11910.540701 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 15351.666667 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 15351.666667 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30641.202803 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 30641.202803 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30641.202803 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 30641.202803 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 206884.054834 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 206884.054834 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 209645.305825 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 209645.305825 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 208487.475041 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 208487.475041 # average overall mshr uncacheable latency +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30575992000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30575992000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12635842717 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12635842717 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 226273500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 226273500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 469500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 469500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 43211834717 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 43211834717 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 43211834717 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 43211834717 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1451037500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1451037500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2035928998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2035928998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3486966498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3486966498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.121007 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.121007 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047305 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047305 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086682 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086682 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000134 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000134 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091208 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091208 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091208 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091208 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27898.770213 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27898.770213 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43450.061438 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43450.061438 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12430.560897 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12430.560897 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16189.655172 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16189.655172 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31159.946435 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 31159.946435 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31159.946435 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 31159.946435 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209384.920635 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209384.920635 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212142.231739 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212142.231739 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 210986.053004 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 210986.053004 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1032757 # number of replacements -system.cpu.icache.tags.tagsinuse 509.197301 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7965141 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1033265 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.708711 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 28360334250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.197301 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.994526 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.994526 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1035158 # number of replacements +system.cpu.icache.tags.tagsinuse 509.238634 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7947846 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1035666 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.674140 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 28148361500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.238634 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.994607 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.994607 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 132 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 304 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 137 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 300 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 10084699 # Number of tag accesses -system.cpu.icache.tags.data_accesses 10084699 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 7965142 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7965142 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7965142 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7965142 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7965142 # number of overall hits -system.cpu.icache.overall_hits::total 7965142 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1086038 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1086038 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1086038 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1086038 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1086038 # number of overall misses -system.cpu.icache.overall_misses::total 1086038 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15222356868 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15222356868 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15222356868 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15222356868 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15222356868 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15222356868 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9051180 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9051180 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9051180 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9051180 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9051180 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9051180 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.119989 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.119989 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.119989 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.119989 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.119989 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.119989 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14016.412748 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14016.412748 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14016.412748 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14016.412748 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14016.412748 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14016.412748 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 5848 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 10073023 # Number of tag accesses +system.cpu.icache.tags.data_accesses 10073023 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 7947847 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7947847 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7947847 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7947847 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7947847 # number of overall hits +system.cpu.icache.overall_hits::total 7947847 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1089244 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1089244 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1089244 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1089244 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1089244 # number of overall misses +system.cpu.icache.overall_misses::total 1089244 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15223822993 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15223822993 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15223822993 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15223822993 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15223822993 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15223822993 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9037091 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9037091 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9037091 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9037091 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9037091 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9037091 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.120530 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.120530 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.120530 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.120530 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.120530 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.120530 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13976.503881 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13976.503881 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13976.503881 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13976.503881 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13976.503881 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13976.503881 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 5247 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 208 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 192 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 28.115385 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 27.328125 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 52519 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 52519 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 52519 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 52519 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 52519 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 52519 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1033519 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1033519 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1033519 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1033519 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1033519 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1033519 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13013904297 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 13013904297 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13013904297 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 13013904297 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13013904297 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 13013904297 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114186 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114186 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114186 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.114186 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114186 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.114186 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12591.838464 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12591.838464 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12591.838464 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12591.838464 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12591.838464 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12591.838464 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53312 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 53312 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 53312 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 53312 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 53312 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 53312 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1035932 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1035932 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1035932 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1035932 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1035932 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1035932 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13551519997 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 13551519997 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13551519997 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 13551519997 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13551519997 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 13551519997 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114631 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114631 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114631 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.114631 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114631 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.114631 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13081.476387 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13081.476387 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13081.476387 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13081.476387 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13081.476387 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13081.476387 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 338332 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65331.413764 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2572439 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 403497 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 6.375361 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 5986676750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 53648.492013 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 5347.510273 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6335.411477 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.818611 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081597 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.096671 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996878 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 338333 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65329.899668 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4170748 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 403498 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 10.336478 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 5937880000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 53646.073919 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 5370.196877 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6313.628872 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.818574 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081943 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.096338 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996855 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 65165 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 491 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3500 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3327 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 490 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3506 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3328 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2403 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55444 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55438 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994339 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 26943938 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 26943938 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 1018225 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 828726 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1846951 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 842087 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 842087 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 31 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 31 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 22 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 22 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 186337 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 186337 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1018225 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1015063 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2033288 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1018225 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1015063 # number of overall hits -system.cpu.l2cache.overall_hits::total 2033288 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 15127 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 273931 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 289058 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 48 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 48 # number of UpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 5 # number of SCUpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::total 5 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 115276 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 115276 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 15127 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 389207 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 404334 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 15127 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 389207 # number of overall misses -system.cpu.l2cache.overall_misses::total 404334 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1264836999 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 20020012000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 21284848999 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 395995 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 395995 # number of UpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 62498 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::total 62498 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10271399612 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 10271399612 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1264836999 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 30291411612 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 31556248611 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1264836999 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 30291411612 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 31556248611 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1033352 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1102657 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2136009 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 842087 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 842087 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 79 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 27 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 27 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 301613 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 301613 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1033352 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1404270 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2437622 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1033352 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1404270 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2437622 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014639 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248428 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.135326 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.607595 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.607595 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.185185 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.185185 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382198 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.382198 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014639 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.277160 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.165872 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014639 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.277160 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.165872 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 83614.530244 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73084.141627 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73635.218534 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 8249.895833 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 8249.895833 # average UpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 12499.600000 # average SCUpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 12499.600000 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89102.671953 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89102.671953 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83614.530244 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77828.537544 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 78045.003910 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83614.530244 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77828.537544 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 78045.003910 # average overall miss latency +system.cpu.l2cache.tags.tag_accesses 39732941 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 39732941 # Number of data accesses +system.cpu.l2cache.Writeback_hits::writebacks 842762 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 842762 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 29 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 29 # number of UpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 23 # number of SCUpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::total 23 # number of SCUpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 186220 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 186220 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1020652 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1020652 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 829426 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 829426 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1020652 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1015646 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2036298 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1020652 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1015646 # number of overall hits +system.cpu.l2cache.overall_hits::total 2036298 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 53 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 53 # number of UpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 6 # number of SCUpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::total 6 # number of SCUpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 115405 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 115405 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 15093 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 15093 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 273846 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 273846 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 15093 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 389251 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 404344 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 15093 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 389251 # number of overall misses +system.cpu.l2cache.overall_misses::total 404344 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 425000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 425000 # number of UpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 61000 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::total 61000 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10303208000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 10303208000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1257093500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 1257093500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 19996128500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 19996128500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1257093500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 30299336500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 31556430000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1257093500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 30299336500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 31556430000 # number of overall miss cycles +system.cpu.l2cache.Writeback_accesses::writebacks 842762 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 842762 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 82 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 82 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 29 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 29 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 301625 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 301625 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1035745 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1035745 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1103272 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1103272 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1035745 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1404897 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2440642 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1035745 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1404897 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2440642 # number of overall (read+write) accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.646341 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.646341 # miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.206897 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.206897 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382611 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.382611 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014572 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014572 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.248213 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.248213 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014572 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.277067 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.165671 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014572 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.277067 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.165671 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 8018.867925 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 8018.867925 # average UpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 10166.666667 # average SCUpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 10166.666667 # average SCUpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89278.696764 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89278.696764 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83289.836348 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83289.836348 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73019.611387 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73019.611387 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83289.836348 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77840.099319 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78043.522347 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83289.836348 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77840.099319 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78043.522347 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1040,130 +1037,141 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 75945 # number of writebacks -system.cpu.l2cache.writebacks::total 75945 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 76057 # number of writebacks +system.cpu.l2cache.writebacks::total 76057 # number of writebacks +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15126 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273931 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 289057 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 48 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 48 # number of UpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 5 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 5 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115276 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 115276 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 15126 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 389207 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 404333 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 15126 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 389207 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 404333 # number of overall MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 307 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 307 # number of CleanEvict MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 53 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 53 # number of UpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 6 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 6 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115405 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 115405 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 15092 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 15092 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 273846 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 273846 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 15092 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 389251 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 404343 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 15092 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 389251 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 404343 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9597 # number of WriteReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9597 # number of WriteReq MSHR uncacheable system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16527 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16527 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1075826749 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16607896000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17683722749 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1000544 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1000544 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 89005 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 89005 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8861643888 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8861643888 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1075826749 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25469539888 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26545366637 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1075826749 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25469539888 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26545366637 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1336686500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1336686500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1887182500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1887182500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3223869000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3223869000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014638 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248428 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.135326 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.607595 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.607595 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.185185 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.185185 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382198 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382198 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014638 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277160 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.165872 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014638 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277160 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.165872 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 71124.338821 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60628.026766 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61177.285964 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20844.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20844.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 17801 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17801 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76873.277074 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76873.277074 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71124.338821 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65439.572998 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65652.238717 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71124.338821 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65439.572998 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65652.238717 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 192884.054834 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 192884.054834 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 196642.961342 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 196642.961342 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 195066.799782 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 195066.799782 # average overall mshr uncacheable latency +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1250500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1250500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 124500 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 124500 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9149158000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9149158000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1106078000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1106078000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 17268105500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 17268105500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1106078000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26417263500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 27523341500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1106078000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26417263500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 27523341500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1364412500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1364412500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1925547500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1925547500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3289960000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3289960000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.646341 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.646341 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.206897 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.206897 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382611 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382611 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014571 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014571 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248213 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248213 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014571 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277067 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.165671 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014571 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277067 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.165671 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 23594.339623 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 23594.339623 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 20750 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20750 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79278.696764 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79278.696764 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73289.027299 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73289.027299 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63057.724049 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63057.724049 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73289.027299 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67866.912352 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68069.291418 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73289.027299 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67866.912352 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68069.291418 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196884.920635 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196884.920635 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200640.564760 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200640.564760 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199065.771162 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199065.771162 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2143279 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2143168 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2146205 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9597 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9597 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 842087 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41601 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 79 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 27 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 106 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 301613 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 301613 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 94 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2066871 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3684049 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5750920 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66134528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143814956 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 209949484 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 42097 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3338284 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.012514 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.111162 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::Writeback 960354 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1857372 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 82 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 29 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 111 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 301625 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 301625 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1035932 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1103445 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 85 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3106451 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4246137 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7352588 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66287680 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143898860 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 210186540 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 422109 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5318690 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.079299 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.270205 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3296510 98.75% 98.75% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 41774 1.25% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4896924 92.07% 92.07% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 421766 7.93% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3338284 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2495140999 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.snoop_fanout::total 5318690 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3296022500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1554402947 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1555343104 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2190379636 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2119169250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1180,8 +1188,7 @@ system.disk2.dma_write_txs 1 # Nu system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution system.iobus.trans_dist::WriteReq 51149 # Transaction distribution -system.iobus.trans_dist::WriteResp 9597 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.iobus.trans_dist::WriteResp 51149 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5050 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) @@ -1236,21 +1243,21 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 242053963 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 216065006 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23457000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42024003 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.259192 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.259177 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1711311066000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.259192 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 1711311931000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.259177 # Average occupied blocks per requestor system.iocache.tags.occ_percent::tsunami.ide 0.078699 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.078699 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -1260,49 +1267,49 @@ system.iocache.tags.tag_accesses 375525 # Nu system.iocache.tags.data_accesses 375525 # Number of data accesses system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21719383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21719383 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8765491577 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 8765491577 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21719383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21719383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21719383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21719383 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21637883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21637883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4909206123 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4909206123 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21637883 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21637883 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21637883 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21637883 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125545.566474 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125545.566474 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 210952.338684 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 210952.338684 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 125545.566474 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125545.566474 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 125545.566474 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125545.566474 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 73146 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125074.468208 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125074.468208 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118146.084978 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118146.084978 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 125074.468208 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125074.468208 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 125074.468208 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125074.468208 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10015 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.303645 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1310,84 +1317,86 @@ system.iocache.writebacks::writebacks 41512 # nu system.iocache.writebacks::total 41512 # number of writebacks system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12567383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12567383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6604781583 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6604781583 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12567383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12567383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12567383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12567383 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12987883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12987883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2831606123 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2831606123 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12987883 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12987883 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12987883 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12987883 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72643.832370 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72643.832370 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 158952.194431 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 158952.194431 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72643.832370 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72643.832370 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72643.832370 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72643.832370 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 75074.468208 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68146.084978 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68146.084978 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 75074.468208 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 75074.468208 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 296160 # Transaction distribution -system.membus.trans_dist::ReadResp 296066 # Transaction distribution +system.membus.trans_dist::ReadReq 6930 # Transaction distribution +system.membus.trans_dist::ReadResp 295956 # Transaction distribution system.membus.trans_dist::WriteReq 9597 # Transaction distribution system.membus.trans_dist::WriteResp 9597 # Transaction distribution -system.membus.trans_dist::Writeback 117457 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 187 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 5 # Transaction distribution -system.membus.trans_dist::UpgradeResp 192 # Transaction distribution -system.membus.trans_dist::ReadExReq 115137 # Transaction distribution -system.membus.trans_dist::ReadExResp 115137 # Transaction distribution -system.membus.trans_dist::BadAddressError 94 # Transaction distribution +system.membus.trans_dist::Writeback 117569 # Transaction distribution +system.membus.trans_dist::CleanEvict 261797 # Transaction distribution +system.membus.trans_dist::UpgradeReq 204 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 6 # Transaction distribution +system.membus.trans_dist::UpgradeResp 210 # Transaction distribution +system.membus.trans_dist::ReadExReq 115254 # Transaction distribution +system.membus.trans_dist::ReadExResp 115254 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 289111 # Transaction distribution +system.membus.trans_dist::BadAddressError 85 # Transaction distribution +system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33054 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884252 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 188 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917494 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1042298 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1146198 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 170 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1179422 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1304239 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30705344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30749484 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36066540 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30712960 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30757100 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33414828 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 435 # Total snoops (count) -system.membus.snoop_fanout::samples 580180 # Request fanout histogram +system.membus.snoop_fanout::samples 842203 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 580180 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 842203 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 580180 # Request fanout histogram -system.membus.reqLayer0.occupancy 29181000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 842203 # Request fanout histogram +system.membus.reqLayer0.occupancy 29160500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1226050062 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1313577675 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 118000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 109500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2139458813 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2139558790 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 42497997 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 72030935 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -1421,28 +1430,28 @@ system.tsunami.ethernet.coalescedTotal nan # av system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6445 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 210982 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74654 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6442 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 210978 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74652 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105549 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182213 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73287 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 105547 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182209 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73285 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73287 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148584 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1817355802000 97.65% 97.65% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 62075500 0.00% 97.66% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 532990500 0.03% 97.69% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 43053863500 2.31% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1861004731500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981689 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73285 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148580 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1817522630000 97.66% 97.66% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 62579500 0.00% 97.67% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 533633500 0.03% 97.70% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 42885651500 2.30% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1861004494500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981688 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694341 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815441 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694335 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815437 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1478,11 +1487,11 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4177 2.18% 2.18% # number of callpals executed +system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175098 91.22% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6783 3.53% 96.97% # number of callpals executed +system.cpu.kern.callpal::swpipl 175094 91.22% 93.43% # number of callpals executed +system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed @@ -1490,20 +1499,20 @@ system.cpu.kern.callpal::whami 2 0.00% 96.98% # nu system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191942 # number of callpals executed +system.cpu.kern.callpal::total 191938 # number of callpals executed system.cpu.kern.mode_switch::kernel 5850 # number of protection mode switches -system.cpu.kern.mode_switch::user 1741 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1911 -system.cpu.kern.mode_good::user 1741 +system.cpu.kern.mode_switch::user 1737 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1907 +system.cpu.kern.mode_good::user 1737 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326667 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.325983 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.394509 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29153631500 1.57% 1.57% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2692582500 0.14% 1.71% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1829158509500 98.29% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4178 # number of times the context was actually changed +system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.393886 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29174464500 1.57% 1.57% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2684090500 0.14% 1.71% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1829145931500 98.29% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index e143de192..8b67c053c 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,131 +1,131 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.841539 # Number of seconds simulated -sim_ticks 1841538755500 # Number of ticks simulated -final_tick 1841538755500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.841548 # Number of seconds simulated +sim_ticks 1841548033500 # Number of ticks simulated +final_tick 1841548033500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 221997 # Simulator instruction rate (inst/s) -host_op_rate 221997 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5796715531 # Simulator tick rate (ticks/s) -host_mem_usage 374488 # Number of bytes of host memory used -host_seconds 317.69 # Real time elapsed on the host -sim_insts 70525499 # Number of instructions simulated -sim_ops 70525499 # Number of ops (including micro ops) simulated +host_inst_rate 218310 # Simulator instruction rate (inst/s) +host_op_rate 218310 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5702515722 # Simulator tick rate (ticks/s) +host_mem_usage 375536 # Number of bytes of host memory used +host_seconds 322.94 # Real time elapsed on the host +sim_insts 70500110 # Number of instructions simulated +sim_ops 70500110 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 467648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 20091072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 147008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2148032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 308096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2634304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 465600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 20057408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 147136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2156416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 307456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2656704 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25797120 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 467648 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 147008 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 308096 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 922752 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7481856 # Number of bytes written to this memory -system.physmem.bytes_written::total 7481856 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7307 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 313923 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2297 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 33563 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4814 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 41161 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25791680 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 465600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 147136 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 307456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 920192 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7484672 # Number of bytes written to this memory +system.physmem.bytes_written::total 7484672 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7275 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 313397 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2299 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 33694 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4804 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 41511 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 403080 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116904 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116904 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 253944 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 10909937 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 79829 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1166433 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 167304 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1430491 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 402995 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116948 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116948 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 252831 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 10891602 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 79898 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1170980 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 166955 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1442647 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 521 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14008459 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 253944 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 79829 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 167304 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 501077 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4062828 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4062828 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4062828 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 253944 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 10909937 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 79829 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1166433 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 167304 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1430491 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 14005434 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 252831 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 79898 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 166955 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 499684 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4064337 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4064337 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4064337 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 252831 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10891602 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 79898 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1170980 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 166955 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1442647 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 521 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18071287 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 81850 # Number of read requests accepted -system.physmem.writeReqs 64472 # Number of write requests accepted -system.physmem.readBursts 81850 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 64472 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5236928 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 1472 # Total number of bytes read from write queue -system.physmem.bytesWritten 3416192 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5238400 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4126208 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 23 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 11076 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 49 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 4878 # Per bank write bursts -system.physmem.perBankRdBursts::1 4919 # Per bank write bursts -system.physmem.perBankRdBursts::2 4947 # Per bank write bursts -system.physmem.perBankRdBursts::3 4947 # Per bank write bursts -system.physmem.perBankRdBursts::4 5010 # Per bank write bursts -system.physmem.perBankRdBursts::5 5136 # Per bank write bursts -system.physmem.perBankRdBursts::6 5318 # Per bank write bursts -system.physmem.perBankRdBursts::7 5111 # Per bank write bursts -system.physmem.perBankRdBursts::8 5349 # Per bank write bursts -system.physmem.perBankRdBursts::9 4830 # Per bank write bursts -system.physmem.perBankRdBursts::10 5530 # Per bank write bursts -system.physmem.perBankRdBursts::11 5119 # Per bank write bursts -system.physmem.perBankRdBursts::12 4880 # Per bank write bursts +system.physmem.bw_total::total 18069771 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 82323 # Number of read requests accepted +system.physmem.writeReqs 47461 # Number of write requests accepted +system.physmem.readBursts 82323 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 47461 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5267264 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 1408 # Total number of bytes read from write queue +system.physmem.bytesWritten 3035584 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5268672 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 3037504 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 22 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 17348 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 4998 # Per bank write bursts +system.physmem.perBankRdBursts::1 5047 # Per bank write bursts +system.physmem.perBankRdBursts::2 4951 # Per bank write bursts +system.physmem.perBankRdBursts::3 4902 # Per bank write bursts +system.physmem.perBankRdBursts::4 5135 # Per bank write bursts +system.physmem.perBankRdBursts::5 5137 # Per bank write bursts +system.physmem.perBankRdBursts::6 5321 # Per bank write bursts +system.physmem.perBankRdBursts::7 5238 # Per bank write bursts +system.physmem.perBankRdBursts::8 5355 # Per bank write bursts +system.physmem.perBankRdBursts::9 4827 # Per bank write bursts +system.physmem.perBankRdBursts::10 5539 # Per bank write bursts +system.physmem.perBankRdBursts::11 5124 # Per bank write bursts +system.physmem.perBankRdBursts::12 4881 # Per bank write bursts system.physmem.perBankRdBursts::13 5044 # Per bank write bursts -system.physmem.perBankRdBursts::14 5637 # Per bank write bursts -system.physmem.perBankRdBursts::15 5172 # Per bank write bursts -system.physmem.perBankWrBursts::0 3097 # Per bank write bursts -system.physmem.perBankWrBursts::1 3264 # Per bank write bursts -system.physmem.perBankWrBursts::2 3389 # Per bank write bursts -system.physmem.perBankWrBursts::3 3378 # Per bank write bursts -system.physmem.perBankWrBursts::4 3165 # Per bank write bursts -system.physmem.perBankWrBursts::5 3060 # Per bank write bursts -system.physmem.perBankWrBursts::6 3647 # Per bank write bursts -system.physmem.perBankWrBursts::7 3165 # Per bank write bursts -system.physmem.perBankWrBursts::8 3847 # Per bank write bursts -system.physmem.perBankWrBursts::9 3079 # Per bank write bursts -system.physmem.perBankWrBursts::10 3680 # Per bank write bursts -system.physmem.perBankWrBursts::11 3339 # Per bank write bursts -system.physmem.perBankWrBursts::12 2997 # Per bank write bursts -system.physmem.perBankWrBursts::13 3248 # Per bank write bursts -system.physmem.perBankWrBursts::14 3739 # Per bank write bursts -system.physmem.perBankWrBursts::15 3284 # Per bank write bursts +system.physmem.perBankRdBursts::14 5631 # Per bank write bursts +system.physmem.perBankRdBursts::15 5171 # Per bank write bursts +system.physmem.perBankWrBursts::0 2712 # Per bank write bursts +system.physmem.perBankWrBursts::1 2869 # Per bank write bursts +system.physmem.perBankWrBursts::2 2967 # Per bank write bursts +system.physmem.perBankWrBursts::3 2927 # Per bank write bursts +system.physmem.perBankWrBursts::4 2992 # Per bank write bursts +system.physmem.perBankWrBursts::5 2769 # Per bank write bursts +system.physmem.perBankWrBursts::6 3293 # Per bank write bursts +system.physmem.perBankWrBursts::7 2918 # Per bank write bursts +system.physmem.perBankWrBursts::8 3398 # Per bank write bursts +system.physmem.perBankWrBursts::9 2634 # Per bank write bursts +system.physmem.perBankWrBursts::10 3325 # Per bank write bursts +system.physmem.perBankWrBursts::11 2913 # Per bank write bursts +system.physmem.perBankWrBursts::12 2642 # Per bank write bursts +system.physmem.perBankWrBursts::13 2800 # Per bank write bursts +system.physmem.perBankWrBursts::14 3388 # Per bank write bursts +system.physmem.perBankWrBursts::15 2884 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 18 # Number of times write queue was full causing retry -system.physmem.totGap 1840526879500 # Total gap between requests +system.physmem.numWrRetry 11 # Number of times write queue was full causing retry +system.physmem.totGap 1840536161000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 81850 # Read request sizes (log2) +system.physmem.readPktSize::6 82323 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 64472 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 63937 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7813 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5603 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 4447 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see +system.physmem.writePktSize::6 47461 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 64278 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 7820 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5619 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 4551 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 22 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see @@ -153,9 +153,9 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 47 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 41 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 41 # What write queue length does an incoming req see @@ -164,185 +164,194 @@ system.physmem.wrQLenPdf::7 39 # Wh system.physmem.wrQLenPdf::8 38 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 37 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 37 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 624 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1857 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 1968 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 2081 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 2163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 2250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 2237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 3058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 2378 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2548 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 3121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 2483 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 2270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 446 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 605 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 525 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 416 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 690 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 660 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 899 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1014 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 889 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 532 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 310 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 27 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 22135 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 390.924780 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 222.627349 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 384.024543 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 7145 32.28% 32.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 4994 22.56% 54.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 1972 8.91% 63.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1000 4.52% 68.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 834 3.77% 72.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 471 2.13% 74.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 534 2.41% 76.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 337 1.52% 78.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4848 21.90% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 22135 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 1909 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 42.863279 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 1017.016663 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 1907 99.90% 99.90% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::13 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 945 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 2418 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 2764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 2856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 3843 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 3517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 2960 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 3353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 2671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 2656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 3003 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2408 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 2268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 2164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 26 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 21805 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 380.777253 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 217.097266 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 378.211296 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 7203 33.03% 33.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 4880 22.38% 55.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 2010 9.22% 64.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1038 4.76% 69.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 857 3.93% 73.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 538 2.47% 75.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 425 1.95% 77.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 372 1.71% 79.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4482 20.55% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 21805 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 2075 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 39.654458 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 980.113813 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 2073 99.90% 99.90% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.05% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.05% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 1909 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 1909 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.961236 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.965205 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 62.780578 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-15 45 2.36% 2.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 1768 92.61% 94.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 14 0.73% 95.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 2 0.10% 95.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 2 0.10% 95.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 1 0.05% 95.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 1 0.05% 96.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 2 0.10% 96.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 11 0.58% 96.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 12 0.63% 97.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 5 0.26% 97.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 8 0.42% 98.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 1 0.05% 98.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 1 0.05% 98.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 2 0.10% 98.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 2 0.10% 98.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 6 0.31% 98.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 5 0.26% 98.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 2 0.10% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 2 0.10% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::400-415 1 0.05% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::448-463 1 0.05% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 2 0.10% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 2 0.10% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 3 0.16% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 4 0.21% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::560-575 1 0.05% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::640-655 1 0.05% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::656-671 2 0.10% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 1909 # Writes before turning the bus around for reads -system.physmem.totQLat 884680000 # Total ticks spent queuing -system.physmem.totMemAccLat 2418936250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 409135000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10811.59 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 2075 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 2075 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.858313 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.353134 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 24.870235 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 34 1.64% 1.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 7 0.34% 1.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 2 0.10% 2.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 5 0.24% 2.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 1736 83.66% 85.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 36 1.73% 87.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 80 3.86% 91.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 17 0.82% 92.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 12 0.58% 92.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 17 0.82% 93.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 5 0.24% 94.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 1 0.05% 94.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.05% 94.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.10% 94.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 3 0.14% 94.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 1 0.05% 94.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.19% 94.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 1 0.05% 94.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 2 0.10% 94.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.05% 94.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 3 0.14% 94.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 9 0.43% 95.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 4 0.19% 95.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 65 3.13% 98.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 3 0.14% 98.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 3 0.14% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.05% 99.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 2 0.10% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.05% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.05% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.05% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 2 0.10% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 2 0.10% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 2 0.10% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 1 0.05% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 3 0.14% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 1 0.05% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 4 0.19% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 2075 # Writes before turning the bus around for reads +system.physmem.totQLat 914891250 # Total ticks spent queuing +system.physmem.totMemAccLat 2458035000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 411505000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11116.41 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29561.59 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.84 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.86 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.84 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.24 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29866.41 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.86 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.65 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.86 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.65 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 11.99 # Average write queue length when enqueuing -system.physmem.readRowHits 70087 # Number of row buffer hits during reads -system.physmem.writeRowHits 42983 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.65 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.50 # Row buffer hit rate for writes -system.physmem.avgGap 12578606.63 # Average gap between requests -system.physmem.pageHitRate 83.62 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 81814320 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 44558250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 314074800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 169549200 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 89055975840 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 35647575705 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 798651060750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 923964608865 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.989912 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1309028017250 # Time in different power states -system.physmem_0.memoryStateTime::REF 45529640000 # Time in different power states +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 2.86 # Average write queue length when enqueuing +system.physmem.readRowHits 70476 # Number of row buffer hits during reads +system.physmem.writeRowHits 37451 # Number of row buffer hits during writes +system.physmem.readRowHitRate 85.63 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.91 # Row buffer hit rate for writes +system.physmem.avgGap 14181533.63 # Average gap between requests +system.physmem.pageHitRate 83.17 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 81194400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 44195250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 317686200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 151936560 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 89056992960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 35637705585 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 799850646000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 925140356955 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.881529 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1309035077000 # Time in different power states +system.physmem_0.memoryStateTime::REF 45530160000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 9101184500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 9110965500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 85526280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 46513500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 324175800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 176340240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 89055975840 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 35475772860 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 801505403250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 926669707770 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.770193 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1309231204000 # Time in different power states -system.physmem_1.memoryStateTime::REF 45529640000 # Time in different power states +system.physmem_1.actEnergy 83651400 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 45474000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 324261600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 155416320 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 89056992960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 35441943930 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 803933138250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 929040878460 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.556246 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1309294919000 # Time in different power states +system.physmem_1.memoryStateTime::REF 45530160000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 8903896000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 8868165750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4781172 # DTB read hits -system.cpu0.dtb.read_misses 6058 # DTB read misses -system.cpu0.dtb.read_acv 118 # DTB read access violations -system.cpu0.dtb.read_accesses 428328 # DTB read accesses -system.cpu0.dtb.write_hits 3391530 # DTB write hits -system.cpu0.dtb.write_misses 675 # DTB write misses -system.cpu0.dtb.write_acv 82 # DTB write access violations -system.cpu0.dtb.write_accesses 163639 # DTB write accesses -system.cpu0.dtb.data_hits 8172702 # DTB hits -system.cpu0.dtb.data_misses 6733 # DTB misses -system.cpu0.dtb.data_acv 200 # DTB access violations -system.cpu0.dtb.data_accesses 591967 # DTB accesses -system.cpu0.itb.fetch_hits 2720050 # ITB hits -system.cpu0.itb.fetch_misses 3046 # ITB misses -system.cpu0.itb.fetch_acv 99 # ITB acv -system.cpu0.itb.fetch_accesses 2723096 # ITB accesses +system.cpu0.dtb.read_hits 4775602 # DTB read hits +system.cpu0.dtb.read_misses 5966 # DTB read misses +system.cpu0.dtb.read_acv 109 # DTB read access violations +system.cpu0.dtb.read_accesses 428378 # DTB read accesses +system.cpu0.dtb.write_hits 3387346 # DTB write hits +system.cpu0.dtb.write_misses 667 # DTB write misses +system.cpu0.dtb.write_acv 80 # DTB write access violations +system.cpu0.dtb.write_accesses 163776 # DTB write accesses +system.cpu0.dtb.data_hits 8162948 # DTB hits +system.cpu0.dtb.data_misses 6633 # DTB misses +system.cpu0.dtb.data_acv 189 # DTB access violations +system.cpu0.dtb.data_accesses 592154 # DTB accesses +system.cpu0.itb.fetch_hits 2717036 # ITB hits +system.cpu0.itb.fetch_misses 3019 # ITB misses +system.cpu0.itb.fetch_acv 97 # ITB acv +system.cpu0.itb.fetch_accesses 2720055 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -355,87 +364,87 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 930048733 # number of cpu cycles simulated +system.cpu0.numCycles 930055234 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 31504183 # Number of instructions committed -system.cpu0.committedOps 31504183 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 29439494 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 162688 # Number of float alu accesses -system.cpu0.num_func_calls 792913 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4107229 # number of instructions that are conditional controls -system.cpu0.num_int_insts 29439494 # number of integer instructions -system.cpu0.num_fp_insts 162688 # number of float instructions -system.cpu0.num_int_register_reads 41004383 # number of times the integer registers were read -system.cpu0.num_int_register_writes 21582488 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 84172 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 85625 # number of times the floating registers were written -system.cpu0.num_mem_refs 8202083 # number of memory refs -system.cpu0.num_load_insts 4802046 # Number of load instructions -system.cpu0.num_store_insts 3400037 # Number of store instructions -system.cpu0.num_idle_cycles 907048310.649553 # Number of idle cycles -system.cpu0.num_busy_cycles 23000422.350447 # Number of busy cycles -system.cpu0.not_idle_fraction 0.024730 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.975270 # Percentage of idle cycles -system.cpu0.Branches 5154717 # Number of branches fetched -system.cpu0.op_class::No_OpClass 1560474 4.95% 4.95% # Class of executed instruction -system.cpu0.op_class::IntAlu 21056937 66.82% 71.78% # Class of executed instruction -system.cpu0.op_class::IntMult 31354 0.10% 71.88% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 71.88% # Class of executed instruction -system.cpu0.op_class::FloatAdd 12843 0.04% 71.92% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 71.92% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 71.92% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 71.92% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1601 0.01% 71.92% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 71.92% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 71.92% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 71.92% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 71.92% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 71.92% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 71.92% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 71.92% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 71.92% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 71.92% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 71.92% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.92% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 71.92% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.92% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.92% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.92% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.92% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.92% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.92% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 71.92% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.92% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.92% # Class of executed instruction -system.cpu0.op_class::MemRead 4932088 15.65% 87.57% # Class of executed instruction -system.cpu0.op_class::MemWrite 3403118 10.80% 98.37% # Class of executed instruction -system.cpu0.op_class::IprAccess 512701 1.63% 100.00% # Class of executed instruction +system.cpu0.committedInsts 31475732 # Number of instructions committed +system.cpu0.committedOps 31475732 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 29412106 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 162586 # Number of float alu accesses +system.cpu0.num_func_calls 792411 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4104277 # number of instructions that are conditional controls +system.cpu0.num_int_insts 29412106 # number of integer instructions +system.cpu0.num_fp_insts 162586 # number of float instructions +system.cpu0.num_int_register_reads 40967178 # number of times the integer registers were read +system.cpu0.num_int_register_writes 21562005 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 84110 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 85570 # number of times the floating registers were written +system.cpu0.num_mem_refs 8192042 # number of memory refs +system.cpu0.num_load_insts 4796241 # Number of load instructions +system.cpu0.num_store_insts 3395801 # Number of store instructions +system.cpu0.num_idle_cycles 907058327.289346 # Number of idle cycles +system.cpu0.num_busy_cycles 22996906.710654 # Number of busy cycles +system.cpu0.not_idle_fraction 0.024726 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.975274 # Percentage of idle cycles +system.cpu0.Branches 5151040 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1559860 4.95% 4.95% # Class of executed instruction +system.cpu0.op_class::IntAlu 21040910 66.83% 71.79% # Class of executed instruction +system.cpu0.op_class::IntMult 31347 0.10% 71.89% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 71.89% # Class of executed instruction +system.cpu0.op_class::FloatAdd 12827 0.04% 71.93% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 71.93% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 71.93% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 71.93% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1598 0.01% 71.93% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 71.93% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 71.93% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 71.93% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 71.93% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 71.93% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 71.93% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 71.93% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 71.93% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 71.93% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 71.93% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.93% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 71.93% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.93% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.93% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.93% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.93% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.93% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.93% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 71.93% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.93% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.93% # Class of executed instruction +system.cpu0.op_class::MemRead 4926196 15.65% 87.58% # Class of executed instruction +system.cpu0.op_class::MemWrite 3398883 10.80% 98.38% # Class of executed instruction +system.cpu0.op_class::IprAccess 510933 1.62% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 31511116 # Class of executed instruction +system.cpu0.op_class::total 31482554 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6421 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211361 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 74795 40.97% 40.97% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6422 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211358 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 74794 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1878 1.03% 42.11% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 105682 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182558 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 73428 49.30% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::31 105680 57.89% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 182555 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 73427 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 73428 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 148937 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1818811073000 98.77% 98.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 38572000 0.00% 98.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 355311500 0.02% 98.79% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22333065000 1.21% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1841538021500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_good::31 73427 49.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 148935 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1818800243000 98.76% 98.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 38808500 0.00% 98.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 357216000 0.02% 98.79% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22351032000 1.21% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1841547299500 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694801 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815834 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694805 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815836 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -474,7 +483,7 @@ system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu0.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175301 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175298 91.20% 93.41% # number of callpals executed system.cpu0.kern.callpal::rdps 6782 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed @@ -483,7 +492,7 @@ system.cpu0.kern.callpal::whami 2 0.00% 96.95% # nu system.cpu0.kern.callpal::rti 5175 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192212 # number of callpals executed +system.cpu0.kern.callpal::total 192209 # number of callpals executed system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches system.cpu0.kern.mode_switch::user 1737 # number of protection mode switches system.cpu0.kern.mode_switch::idle 2093 # number of protection mode switches @@ -494,429 +503,429 @@ system.cpu0.kern.mode_switch_good::kernel 0.321851 # f system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle 0.080745 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total 0.390894 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29730845000 1.61% 1.61% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2571229000 0.14% 1.75% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1809235945500 98.25% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::kernel 29750547000 1.62% 1.62% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2575384000 0.14% 1.76% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1809221366500 98.24% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 4175 # number of times the context was actually changed -system.cpu0.dcache.tags.replacements 1393219 # number of replacements +system.cpu0.dcache.tags.replacements 1393348 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997816 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 13266024 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1393731 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.518353 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 13255372 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1393860 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.509830 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 178.252416 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 164.663502 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 169.081899 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.348149 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.321608 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.330238 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 177.816582 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 164.221248 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 169.959986 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.347298 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.320745 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.331953 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63377040 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63377040 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 3961674 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1077685 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 2542197 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7581556 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3105087 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 828848 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 1366589 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5300524 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 113741 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19662 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 51148 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 184551 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 122328 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21764 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 55225 # number of StoreCondReq hits +system.cpu0.dcache.tags.tag_accesses 63362265 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63362265 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 3956098 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 1080024 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 2536463 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7572585 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3101293 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 830391 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 1367001 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5298685 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 113681 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19703 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 51298 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 184682 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 122268 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21809 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 55240 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 199317 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 7066761 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 1906533 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 3908786 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12882080 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 7066761 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 1906533 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 3908786 # number of overall hits -system.cpu0.dcache.overall_hits::total 12882080 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 706841 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 96965 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 557653 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1361459 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 162721 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 43998 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 642629 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 849348 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9135 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2231 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7695 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 19061 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu2.data 11 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 11 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 869562 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 140963 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1200282 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2210807 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 869562 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 140963 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1200282 # number of overall misses -system.cpu0.dcache.overall_misses::total 2210807 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2267399500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 8210771504 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 10478171004 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1754611010 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 19498280034 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 21252891044 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 29510000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 125540000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 155050000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 185002 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 185002 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 4022010510 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 27709051538 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 31731062048 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 4022010510 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 27709051538 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 31731062048 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 4668515 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1174650 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 3099850 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8943015 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3267808 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 872846 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 2009218 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6149872 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 122876 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 21893 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 58843 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 203612 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 122328 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21764 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 55236 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 199328 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 7936323 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 2047496 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 5109068 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 15092887 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 7936323 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 2047496 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 5109068 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 15092887 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.151406 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.082548 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.179897 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.152237 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049795 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.050408 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.319840 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.138108 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.074343 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.101905 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.130772 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.093614 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000199 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000055 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.109567 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.068847 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.234932 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.146480 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.109567 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.068847 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.234932 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.146480 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 23383.689991 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14723.800471 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 7696.280978 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 39879.335652 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30341.425666 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 25022.595031 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13227.252353 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 16314.489929 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 8134.410577 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 16818.363636 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16818.363636 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 28532.384455 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 23085.451201 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 14352.705617 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 28532.384455 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 23085.451201 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 14352.705617 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 977120 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 1794 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 54184 # number of cycles access was blocked +system.cpu0.dcache.demand_hits::cpu0.data 7057391 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 1910415 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 3903464 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12871270 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 7057391 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 1910415 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 3903464 # number of overall hits +system.cpu0.dcache.overall_hits::total 12871270 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 706776 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 97332 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 562527 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1366635 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 162364 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 44132 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 644654 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 851150 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9134 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2235 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7668 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 19037 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu2.data 10 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 10 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 869140 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 141464 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 1207181 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2217785 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 869140 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 141464 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 1207181 # number of overall misses +system.cpu0.dcache.overall_misses::total 2217785 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2268250000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 8231829500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 10500079500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1752940000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 19634310548 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 21387250548 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 29559000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 124972000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 154531000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 170500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 170500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 4021190000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 27866140048 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 31887330048 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 4021190000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 27866140048 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 31887330048 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 4662874 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 1177356 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 3098990 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8939220 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 3263657 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 874523 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 2011655 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 6149835 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 122815 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 21938 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 58966 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 203719 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 122268 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21809 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 55250 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 199327 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 7926531 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 2051879 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 5110645 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 15089055 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 7926531 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 2051879 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 5110645 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 15089055 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.151575 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.082670 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.181519 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.152881 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049749 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.050464 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.320460 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.138402 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.074372 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.101878 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.130041 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.093447 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000181 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000050 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.109649 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.068944 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.236209 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.146980 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.109649 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.068944 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.236209 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.146980 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 23304.257593 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14633.661140 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 7683.163025 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 39720.384302 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30457.129791 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 25127.475237 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13225.503356 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 16297.861242 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 8117.402952 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 17050 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 17050 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 28425.535825 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 23083.646983 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 14378.007809 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 28425.535825 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 23083.646983 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 14378.007809 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 1019885 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 1764 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 60259 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 18 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 18.033368 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 99.666667 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 16.925024 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 98 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 835707 # number of writebacks -system.cpu0.dcache.writebacks::total 835707 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 287560 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 287560 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 546849 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 546849 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1691 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1691 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 834409 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 834409 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 834409 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 834409 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 96965 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 270093 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 367058 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 43998 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 95780 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 139778 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2231 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 6004 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8235 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 11 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 11 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 140963 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 365873 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 506836 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 140963 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 365873 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 506836 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 1102 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 1563 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 2665 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 1382 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 2131 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 3513 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 2484 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 3694 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 6178 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2114965000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4270329509 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6385294509 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1680467990 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3020406043 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4700874033 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 26161500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 72039750 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 98201250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 168498 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 168498 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3795432990 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7290735552 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 11086168542 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3795432990 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 7290735552 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 11086168542 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 222473500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 331326000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 553799500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 293979000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 446199000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 740178000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 516452500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 777525000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1293977500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.082548 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.087131 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041044 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.050408 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047670 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022729 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.101905 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.102034 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.040445 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000199 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000055 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.068847 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071612 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.033581 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.068847 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071612 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.033581 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 21811.633063 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15810.589349 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17395.873429 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38194.190418 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 31534.830267 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33631.000823 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11726.355894 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11998.625916 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11924.863388 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 15318 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15318 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 26925.029901 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19926.957037 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21873.285524 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 26925.029901 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19926.957037 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21873.285524 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 201881.578947 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 211980.806142 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 207804.690432 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 212719.971056 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 209384.795870 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 210696.840307 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 207911.634461 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 210483.216026 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 209449.255422 # average overall mshr uncacheable latency +system.cpu0.dcache.writebacks::writebacks 835740 # number of writebacks +system.cpu0.dcache.writebacks::total 835740 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 292598 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 292598 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 548626 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 548626 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1690 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1690 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 841224 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 841224 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 841224 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 841224 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 97332 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 269929 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 367261 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 44132 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 96028 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 140160 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2235 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 5978 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8213 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 10 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 10 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 141464 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 365957 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 507421 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 141464 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 365957 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 507421 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 1108 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 1559 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 2667 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 1387 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 2128 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 3515 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 2495 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 3687 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 6182 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2170918000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4426676000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6597594000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1708808000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3106661815 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4815469815 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 27324000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 74701500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 102025500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 160500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 160500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3879726000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7533337815 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11413063815 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3879726000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 7533337815 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11413063815 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 226454500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 334463500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 560918000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 298425500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 450956500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 749382000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 524880000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 785420000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1310300000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.082670 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.087102 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041084 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.050464 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047736 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022791 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.101878 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.101380 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.040315 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000181 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000050 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.068944 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071607 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.033628 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.068944 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071607 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.033628 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 22304.257593 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16399.408733 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17964.319653 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38720.384302 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32351.624682 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34356.947881 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12225.503356 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12496.068919 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12422.440034 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 16050 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 16050 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27425.535825 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20585.308697 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22492.296959 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 27425.535825 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20585.308697 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22492.296959 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 204381.317690 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 214537.203335 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210317.960255 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 215158.976208 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 211915.648496 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 213195.448080 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 210372.745491 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 213024.138866 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 211954.060175 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 964809 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.919385 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 41279952 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 965320 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 42.762972 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 10189587250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 147.730782 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 136.243694 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 226.944909 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.288537 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.266101 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.443252 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997889 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 965393 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.914113 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 41264625 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 965904 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 42.721249 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 10188445500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 146.904249 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 135.394605 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 228.615259 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.286922 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.264443 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.446514 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997879 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 447 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 43227698 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 43227698 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 31004099 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 7794052 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2481801 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 41279952 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 31004099 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 7794052 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2481801 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 41279952 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 31004099 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 7794052 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2481801 # number of overall hits -system.cpu0.icache.overall_hits::total 41279952 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 507017 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 128848 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 346369 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 982234 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 507017 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 128848 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 346369 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 982234 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 507017 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 128848 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 346369 # number of overall misses -system.cpu0.icache.overall_misses::total 982234 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1839260250 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4838788318 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6678048568 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1839260250 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4838788318 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6678048568 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1839260250 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4838788318 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6678048568 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 31511116 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 7922900 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 2828170 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 42262186 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 31511116 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 7922900 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 2828170 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 42262186 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 31511116 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 7922900 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 2828170 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 42262186 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016090 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016263 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122471 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.023241 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016090 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016263 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122471 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.023241 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016090 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016263 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122471 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.023241 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14274.651139 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13970.038652 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 6798.836701 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14274.651139 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13970.038652 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 6798.836701 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14274.651139 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13970.038652 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 6798.836701 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4002 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 43213951 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 43213951 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 30975792 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 7803098 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 2485735 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 41264625 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 30975792 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 7803098 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 2485735 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 41264625 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 30975792 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 7803098 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 2485735 # number of overall hits +system.cpu0.icache.overall_hits::total 41264625 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 506762 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 129019 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 347436 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 983217 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 506762 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 129019 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 347436 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 983217 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 506762 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 129019 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 347436 # number of overall misses +system.cpu0.icache.overall_misses::total 983217 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1839982500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4838575988 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 6678558488 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 1839982500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 4838575988 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 6678558488 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 1839982500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 4838575988 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 6678558488 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 31482554 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 7932117 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 2833171 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 42247842 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 31482554 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 7932117 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 2833171 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 42247842 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 31482554 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 7932117 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 2833171 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 42247842 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016097 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016265 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122631 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.023273 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016097 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016265 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122631 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.023273 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016097 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016265 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122631 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.023273 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14261.329727 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13926.524563 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 6792.557989 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14261.329727 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13926.524563 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 6792.557989 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14261.329727 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13926.524563 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 6792.557989 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 3935 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 225 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 210 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.786667 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.738095 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16722 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 16722 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 16722 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 16722 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 16722 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 16722 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 128848 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 329647 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 458495 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 128848 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 329647 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 458495 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 128848 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 329647 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 458495 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1645092750 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4148478396 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 5793571146 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1645092750 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4148478396 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 5793571146 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1645092750 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4148478396 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5793571146 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016263 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116558 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010849 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016263 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116558 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.010849 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016263 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116558 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.010849 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12767.701090 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12584.608372 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12636.061780 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12767.701090 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12584.608372 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12636.061780 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12767.701090 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12584.608372 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12636.061780 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 17108 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 17108 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 17108 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 17108 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 17108 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 17108 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 129019 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 330328 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 459347 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 129019 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 330328 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 459347 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 129019 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 330328 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 459347 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1710963500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4315526491 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 6026489991 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1710963500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4315526491 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 6026489991 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1710963500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4315526491 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 6026489991 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016265 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116593 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010873 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016265 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116593 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.010873 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016265 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116593 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.010873 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13261.329727 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13064.367813 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13119.689453 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13261.329727 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13064.367813 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13119.689453 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13261.329727 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13064.367813 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13119.689453 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1194215 # DTB read hits -system.cpu1.dtb.read_misses 1316 # DTB read misses +system.cpu1.dtb.read_hits 1196955 # DTB read hits +system.cpu1.dtb.read_misses 1325 # DTB read misses system.cpu1.dtb.read_acv 35 # DTB read access violations -system.cpu1.dtb.read_accesses 141030 # DTB read accesses -system.cpu1.dtb.write_hits 894755 # DTB write hits +system.cpu1.dtb.read_accesses 141268 # DTB read accesses +system.cpu1.dtb.write_hits 896481 # DTB write hits system.cpu1.dtb.write_misses 169 # DTB write misses system.cpu1.dtb.write_acv 22 # DTB write access violations -system.cpu1.dtb.write_accesses 57515 # DTB write accesses -system.cpu1.dtb.data_hits 2088970 # DTB hits -system.cpu1.dtb.data_misses 1485 # DTB misses +system.cpu1.dtb.write_accesses 57742 # DTB write accesses +system.cpu1.dtb.data_hits 2093436 # DTB hits +system.cpu1.dtb.data_misses 1494 # DTB misses system.cpu1.dtb.data_acv 57 # DTB access violations -system.cpu1.dtb.data_accesses 198545 # DTB accesses -system.cpu1.itb.fetch_hits 856400 # ITB hits -system.cpu1.itb.fetch_misses 653 # ITB misses -system.cpu1.itb.fetch_acv 34 # ITB acv -system.cpu1.itb.fetch_accesses 857053 # ITB accesses +system.cpu1.dtb.data_accesses 199010 # DTB accesses +system.cpu1.itb.fetch_hits 858438 # ITB hits +system.cpu1.itb.fetch_misses 659 # ITB misses +system.cpu1.itb.fetch_acv 35 # ITB acv +system.cpu1.itb.fetch_accesses 859097 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -929,64 +938,64 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953255662 # number of cpu cycles simulated +system.cpu1.numCycles 953273349 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7921357 # Number of instructions committed -system.cpu1.committedOps 7921357 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 7380748 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 45896 # Number of float alu accesses -system.cpu1.num_func_calls 207012 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1022630 # number of instructions that are conditional controls -system.cpu1.num_int_insts 7380748 # number of integer instructions -system.cpu1.num_fp_insts 45896 # number of float instructions -system.cpu1.num_int_register_reads 10351742 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5363285 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 24726 # number of times the floating registers were read +system.cpu1.committedInsts 7930565 # Number of instructions committed +system.cpu1.committedOps 7930565 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 7389333 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 45920 # Number of float alu accesses +system.cpu1.num_func_calls 207460 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1022605 # number of instructions that are conditional controls +system.cpu1.num_int_insts 7389333 # number of integer instructions +system.cpu1.num_fp_insts 45920 # number of float instructions +system.cpu1.num_int_register_reads 10362144 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5369975 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 24736 # number of times the floating registers were read system.cpu1.num_fp_register_writes 25085 # number of times the floating registers were written -system.cpu1.num_mem_refs 2096070 # number of memory refs -system.cpu1.num_load_insts 1198996 # Number of load instructions -system.cpu1.num_store_insts 897074 # Number of store instructions -system.cpu1.num_idle_cycles 923177922.874727 # Number of idle cycles -system.cpu1.num_busy_cycles 30077739.125273 # Number of busy cycles -system.cpu1.not_idle_fraction 0.031553 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.968447 # Percentage of idle cycles -system.cpu1.Branches 1296149 # Number of branches fetched -system.cpu1.op_class::No_OpClass 410448 5.18% 5.18% # Class of executed instruction -system.cpu1.op_class::IntAlu 5236817 66.10% 71.28% # Class of executed instruction -system.cpu1.op_class::IntMult 8727 0.11% 71.39% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 71.39% # Class of executed instruction -system.cpu1.op_class::FloatAdd 5162 0.07% 71.45% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::FloatDiv 810 0.01% 71.46% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 71.46% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 71.46% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 71.46% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 71.46% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 71.46% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 71.46% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 71.46% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 71.46% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 71.46% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 71.46% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 71.46% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 71.46% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 71.46% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 71.46% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 71.46% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 71.46% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 71.46% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 71.46% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 71.46% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 71.46% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 71.46% # Class of executed instruction -system.cpu1.op_class::MemRead 1228055 15.50% 86.96% # Class of executed instruction -system.cpu1.op_class::MemWrite 898300 11.34% 98.30% # Class of executed instruction -system.cpu1.op_class::IprAccess 134580 1.70% 100.00% # Class of executed instruction +system.cpu1.num_mem_refs 2100568 # number of memory refs +system.cpu1.num_load_insts 1201762 # Number of load instructions +system.cpu1.num_store_insts 898806 # Number of store instructions +system.cpu1.num_idle_cycles 922154358.750069 # Number of idle cycles +system.cpu1.num_busy_cycles 31118990.249931 # Number of busy cycles +system.cpu1.not_idle_fraction 0.032644 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.967356 # Percentage of idle cycles +system.cpu1.Branches 1296677 # Number of branches fetched +system.cpu1.op_class::No_OpClass 410840 5.18% 5.18% # Class of executed instruction +system.cpu1.op_class::IntAlu 5240708 66.07% 71.25% # Class of executed instruction +system.cpu1.op_class::IntMult 8731 0.11% 71.36% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 71.36% # Class of executed instruction +system.cpu1.op_class::FloatAdd 5176 0.07% 71.42% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 71.42% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 71.42% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 71.42% # Class of executed instruction +system.cpu1.op_class::FloatDiv 810 0.01% 71.43% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 71.43% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 71.43% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 71.43% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 71.43% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 71.43% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 71.43% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 71.43% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 71.43% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 71.43% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 71.43% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 71.43% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 71.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 71.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 71.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 71.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 71.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 71.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 71.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 71.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 71.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 71.43% # Class of executed instruction +system.cpu1.op_class::MemRead 1230901 15.52% 86.95% # Class of executed instruction +system.cpu1.op_class::MemWrite 900034 11.35% 98.30% # Class of executed instruction +system.cpu1.op_class::IprAccess 134916 1.70% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 7922899 # Class of executed instruction +system.cpu1.op_class::total 7932116 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed @@ -1004,35 +1013,35 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu2.branchPred.lookups 10412478 # Number of BP lookups -system.cpu2.branchPred.condPredicted 9668294 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 126557 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 8251745 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 6275895 # Number of BTB hits +system.cpu2.branchPred.lookups 10402334 # Number of BP lookups +system.cpu2.branchPred.condPredicted 9657881 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 126933 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 8330137 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 6272162 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 76.055368 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 302998 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 7851 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 75.294824 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 302639 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 7723 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3529660 # DTB read hits -system.cpu2.dtb.read_misses 12347 # DTB read misses -system.cpu2.dtb.read_acv 141 # DTB read access violations -system.cpu2.dtb.read_accesses 225697 # DTB read accesses -system.cpu2.dtb.write_hits 2155841 # DTB write hits -system.cpu2.dtb.write_misses 2820 # DTB write misses -system.cpu2.dtb.write_acv 143 # DTB write access violations -system.cpu2.dtb.write_accesses 84900 # DTB write accesses -system.cpu2.dtb.data_hits 5685501 # DTB hits -system.cpu2.dtb.data_misses 15167 # DTB misses -system.cpu2.dtb.data_acv 284 # DTB access violations -system.cpu2.dtb.data_accesses 310597 # DTB accesses -system.cpu2.itb.fetch_hits 538073 # ITB hits -system.cpu2.itb.fetch_misses 5955 # ITB misses -system.cpu2.itb.fetch_acv 169 # ITB acv -system.cpu2.itb.fetch_accesses 544028 # ITB accesses +system.cpu2.dtb.read_hits 3549115 # DTB read hits +system.cpu2.dtb.read_misses 12776 # DTB read misses +system.cpu2.dtb.read_acv 157 # DTB read access violations +system.cpu2.dtb.read_accesses 225358 # DTB read accesses +system.cpu2.dtb.write_hits 2157791 # DTB write hits +system.cpu2.dtb.write_misses 2831 # DTB write misses +system.cpu2.dtb.write_acv 142 # DTB write access violations +system.cpu2.dtb.write_accesses 84650 # DTB write accesses +system.cpu2.dtb.data_hits 5706906 # DTB hits +system.cpu2.dtb.data_misses 15607 # DTB misses +system.cpu2.dtb.data_acv 299 # DTB access violations +system.cpu2.dtb.data_accesses 310008 # DTB accesses +system.cpu2.itb.fetch_hits 538598 # ITB hits +system.cpu2.itb.fetch_misses 5991 # ITB misses +system.cpu2.itb.fetch_acv 159 # ITB acv +system.cpu2.itb.fetch_accesses 544589 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1045,304 +1054,304 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 30702821 # number of cpu cycles simulated +system.cpu2.numCycles 30759536 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9319148 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 39738878 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 10412478 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 6578893 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 19243837 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 412304 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 656 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 9648 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1927 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 233877 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 108804 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 445 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2828172 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 93139 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 29124256 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.364460 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.368556 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9338114 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 39735788 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 10402334 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 6574801 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 19282744 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 413720 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 277 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 9678 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1944 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 234903 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 108900 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 473 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2833173 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 93993 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 29183655 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.361577 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.367035 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 20002999 68.68% 68.68% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 306830 1.05% 69.74% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 477568 1.64% 71.37% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 4658363 15.99% 87.37% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 855343 2.94% 90.31% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 200502 0.69% 90.99% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 234860 0.81% 91.80% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 433547 1.49% 93.29% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1954244 6.71% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 20063773 68.75% 68.75% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 307542 1.05% 69.80% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 477296 1.64% 71.44% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 4654234 15.95% 87.39% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 859104 2.94% 90.33% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 198525 0.68% 91.01% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 235442 0.81% 91.82% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 432653 1.48% 93.30% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1955086 6.70% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 29124256 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.339138 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.294307 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 7666487 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 12991565 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 7744961 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 527663 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 193001 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 177358 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 13514 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36364188 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 42851 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 193001 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 7942048 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 4601261 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 6305683 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 7969678 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 2112012 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 35538074 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 62867 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 396006 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 59218 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 1045972 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 23773076 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 44310063 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 44249815 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 56335 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 21846032 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1927044 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 532665 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 63556 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3796199 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3529311 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2248768 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 470664 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 333419 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 32987424 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 681806 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 32666998 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 16031 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2569271 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1151235 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 487594 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 29124256 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.121642 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.623821 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 29183655 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.338182 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.291820 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 7672062 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 13049396 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 7739525 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 528158 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 193789 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 177139 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 13443 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36353966 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 42512 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 193789 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 7950274 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 4574250 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 6325048 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 7961138 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 2178432 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 35523870 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 60190 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 394243 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 57916 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 1115509 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 23763436 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 44289897 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 44229633 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 56339 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 21842362 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1921074 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 535035 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 63809 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3839801 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3528507 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2250963 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 468940 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 330687 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 32977065 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 683079 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 32678030 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 15337 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2566331 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1147551 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 488786 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 29183655 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.119737 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.624192 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 17381860 59.68% 59.68% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 2746661 9.43% 69.11% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1371662 4.71% 73.82% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 5386342 18.49% 92.32% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 1029310 3.53% 95.85% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 605779 2.08% 97.93% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 390861 1.34% 99.27% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 167562 0.58% 99.85% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 44219 0.15% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 17436459 59.75% 59.75% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 2753806 9.44% 69.18% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1377159 4.72% 73.90% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 5375832 18.42% 92.32% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 1030141 3.53% 95.85% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 601956 2.06% 97.92% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 392573 1.35% 99.26% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 169204 0.58% 99.84% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 46525 0.16% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 29124256 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 29183655 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 85214 22.02% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 179569 46.41% 68.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 122132 31.57% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 85386 21.51% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 184726 46.54% 68.05% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 126802 31.95% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 2450 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 26477502 81.05% 81.06% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 21078 0.06% 81.12% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.12% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 20355 0.06% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1225 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3659635 11.20% 92.39% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2180799 6.68% 99.07% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 303954 0.93% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 2456 0.01% 0.01% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 26465043 80.99% 80.99% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 21101 0.06% 81.06% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.06% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 20515 0.06% 81.12% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.12% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.12% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.12% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1228 0.00% 81.13% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 81.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 81.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 81.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 81.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 81.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 81.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 81.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 81.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 81.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 81.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 81.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 81.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 81.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 81.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 81.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 81.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 81.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.13% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3679518 11.26% 92.39% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2182790 6.68% 99.07% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 305379 0.93% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 32666998 # Type of FU issued -system.cpu2.iq.rate 1.063974 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 386915 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.011844 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 94607462 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 36124516 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 32054290 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 253736 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 119890 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 117198 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 32915380 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 136083 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 205891 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 32678030 # Type of FU issued +system.cpu2.iq.rate 1.062371 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 396914 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.012146 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 94697637 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 36112111 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 32047154 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 254329 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 120282 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 117366 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 32936079 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 136409 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 206083 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 443704 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1465 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 6049 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 180746 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 440040 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1257 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 6058 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 180485 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5094 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 200289 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5073 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 225988 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 193001 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 3976817 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 219021 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 35063617 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 53776 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3529311 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2248768 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 606766 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 12977 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 164349 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 6049 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 63932 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 135830 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 199762 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 32464526 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3550760 # Number of load instructions executed +system.cpu2.iew.iewSquashCycles 193789 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 3993186 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 173385 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 35054322 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 55127 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3528507 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2250963 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 608084 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 13021 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 119091 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 6058 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 64339 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 136180 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 200519 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 32475558 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3570784 # Number of load instructions executed system.cpu2.iew.iewExecSquashedInsts 202472 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1394387 # number of nop insts executed -system.cpu2.iew.exec_refs 5714159 # number of memory reference insts executed -system.cpu2.iew.exec_branches 7350868 # Number of branches executed -system.cpu2.iew.exec_stores 2163399 # Number of stores executed -system.cpu2.iew.exec_rate 1.057379 # Inst execution rate -system.cpu2.iew.wb_sent 32215343 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 32171488 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 18756374 # num instructions producing a value -system.cpu2.iew.wb_consumers 22505351 # num instructions consuming a value +system.cpu2.iew.exec_nop 1394178 # number of nop insts executed +system.cpu2.iew.exec_refs 5736169 # number of memory reference insts executed +system.cpu2.iew.exec_branches 7344406 # Number of branches executed +system.cpu2.iew.exec_stores 2165385 # Number of stores executed +system.cpu2.iew.exec_rate 1.055788 # Inst execution rate +system.cpu2.iew.wb_sent 32207740 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 32164520 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 18733989 # num instructions producing a value +system.cpu2.iew.wb_consumers 22461298 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.047835 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.833418 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.045676 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.834056 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 2693673 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 194212 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 181849 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 28653786 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.128143 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.870801 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 2690484 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 194293 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 182480 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 28713100 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.125605 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.869287 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 18143596 63.32% 63.32% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2243135 7.83% 71.15% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1187950 4.15% 75.29% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 5112990 17.84% 93.14% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 566123 1.98% 95.11% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 201198 0.70% 95.82% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 164794 0.58% 96.39% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 163684 0.57% 96.96% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 870316 3.04% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 18196306 63.37% 63.37% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2254505 7.85% 71.22% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1188955 4.14% 75.37% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 5110402 17.80% 93.16% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 563606 1.96% 95.13% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 199238 0.69% 95.82% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 165515 0.58% 96.40% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 164290 0.57% 96.97% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 870283 3.03% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 28653786 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 32325567 # Number of instructions committed -system.cpu2.commit.committedOps 32325567 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 28713100 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 32319619 # Number of instructions committed +system.cpu2.commit.committedOps 32319619 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 5153629 # Number of memory references committed -system.cpu2.commit.loads 3085607 # Number of loads committed -system.cpu2.commit.membars 68228 # Number of memory barriers committed -system.cpu2.commit.branches 7176692 # Number of branches committed -system.cpu2.commit.fp_insts 115672 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 30802580 # Number of committed integer instructions. -system.cpu2.commit.function_calls 241655 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 1228058 3.80% 3.80% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 25528107 78.97% 82.77% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 20647 0.06% 82.83% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 82.83% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 20076 0.06% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 1225 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 3153835 9.76% 92.66% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 2069665 6.40% 99.06% # Class of committed instruction -system.cpu2.commit.op_class_0::IprAccess 303954 0.94% 100.00% # Class of committed instruction +system.cpu2.commit.refs 5158945 # Number of memory references committed +system.cpu2.commit.loads 3088467 # Number of loads committed +system.cpu2.commit.membars 68233 # Number of memory barriers committed +system.cpu2.commit.branches 7171529 # Number of branches committed +system.cpu2.commit.fp_insts 115750 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 30796114 # Number of committed integer instructions. +system.cpu2.commit.function_calls 241665 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 1228262 3.80% 3.80% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 25515212 78.95% 82.75% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 20642 0.06% 82.81% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 82.81% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 20078 0.06% 82.87% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 82.87% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 82.87% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 82.87% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 1228 0.00% 82.88% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 82.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 82.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 82.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 82.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 82.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 82.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 82.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 82.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 82.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 82.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 82.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 82.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 82.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 82.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 82.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 82.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 82.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 82.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 82.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 82.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 82.88% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 3156700 9.77% 92.64% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 2072118 6.41% 99.06% # Class of committed instruction +system.cpu2.commit.op_class_0::IprAccess 305379 0.94% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 32325567 # Class of committed instruction -system.cpu2.commit.bw_lim_events 870316 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 62726939 # The number of ROB reads -system.cpu2.rob.rob_writes 70507401 # The number of ROB writes -system.cpu2.timesIdled 178497 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1578565 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1745106872 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 31099959 # Number of Instructions Simulated -system.cpu2.committedOps 31099959 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 0.987230 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.987230 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.012935 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.012935 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 42640475 # number of integer regfile reads -system.cpu2.int_regfile_writes 22658201 # number of integer regfile writes -system.cpu2.fp_regfile_reads 70901 # number of floating regfile reads -system.cpu2.fp_regfile_writes 71243 # number of floating regfile writes -system.cpu2.misc_regfile_reads 5010785 # number of misc regfile reads -system.cpu2.misc_regfile_writes 273099 # number of misc regfile writes +system.cpu2.commit.op_class_0::total 32319619 # Class of committed instruction +system.cpu2.commit.bw_lim_events 870283 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 62775514 # The number of ROB reads +system.cpu2.rob.rob_writes 70489103 # The number of ROB writes +system.cpu2.timesIdled 177769 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1575881 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1745050657 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 31093813 # Number of Instructions Simulated +system.cpu2.committedOps 31093813 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 0.989249 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.989249 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.010867 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.010867 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 42649325 # number of integer regfile reads +system.cpu2.int_regfile_writes 22654905 # number of integer regfile writes +system.cpu2.fp_regfile_reads 71051 # number of floating regfile reads +system.cpu2.fp_regfile_writes 71293 # number of floating regfile writes +system.cpu2.misc_regfile_reads 5005090 # number of misc regfile reads +system.cpu2.misc_regfile_writes 273836 # number of misc regfile writes system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1358,8 +1367,7 @@ system.disk2.dma_write_txs 1 # Nu system.iobus.trans_dist::ReadReq 7317 # Transaction distribution system.iobus.trans_dist::ReadResp 7317 # Transaction distribution system.iobus.trans_dist::WriteReq 51362 # Transaction distribution -system.iobus.trans_dist::WriteResp 9810 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.iobus.trans_dist::WriteResp 51362 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5192 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) @@ -1398,7 +1406,7 @@ system.iobus.reqLayer1.occupancy 105000 # La system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer22.occupancy 48000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5364000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 5370000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 1863000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) @@ -1408,21 +1416,21 @@ system.iobus.reqLayer27.occupancy 7000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 14000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 100878274 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 89820170 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 8843000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 8849000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17495500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 17468000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.254165 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.254241 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1693892917000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.254165 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078385 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078385 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1693892852000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.254241 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078390 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078390 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1430,49 +1438,49 @@ system.iocache.tags.tag_accesses 375525 # Nu system.iocache.tags.data_accesses 375525 # Number of data accesses system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 9444962 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 9444962 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 3667270812 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 3667270812 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 9444962 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 9444962 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 9444962 # number of overall miss cycles -system.iocache.overall_miss_latency::total 9444962 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 9418962 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 9418962 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 2040792208 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 2040792208 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 9418962 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 9418962 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 9418962 # number of overall miss cycles +system.iocache.overall_miss_latency::total 9418962 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54595.156069 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 54595.156069 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 88257.383808 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 88257.383808 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 54595.156069 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 54595.156069 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 54595.156069 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 54595.156069 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 31008 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54444.867052 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 54444.867052 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 49114.175202 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 49114.175202 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 54444.867052 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 54444.867052 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 54444.867052 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 54444.867052 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 4243 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.308037 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1480,237 +1488,243 @@ system.iocache.writebacks::writebacks 41512 # nu system.iocache.writebacks::total 41512 # number of writebacks system.iocache.ReadReq_mshr_misses::tsunami.ide 70 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 17280 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 17280 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::tsunami.ide 17280 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 17280 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::tsunami.ide 70 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 70 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 70 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 70 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5749962 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 5749962 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2768710812 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2768710812 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 5749962 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 5749962 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 5749962 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 5749962 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5918962 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 5918962 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 1176792208 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 1176792208 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 5918962 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 5918962 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 5918962 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 5918962 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 0.404624 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.415864 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.415864 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 0.415864 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.415864 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 0.404624 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 0.404624 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82142.314286 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 82142.314286 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 160226.320139 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 160226.320139 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 82142.314286 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 82142.314286 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 82142.314286 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 82142.314286 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 84556.600000 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 84556.600000 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68101.400926 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68101.400926 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 84556.600000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 84556.600000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 84556.600000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 84556.600000 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 337569 # number of replacements -system.l2c.tags.tagsinuse 65419.566617 # Cycle average of tags in use -system.l2c.tags.total_refs 2487366 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 402731 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.176247 # Average number of references to valid blocks. +system.l2c.tags.replacements 337481 # number of replacements +system.l2c.tags.tagsinuse 65419.198683 # Cycle average of tags in use +system.l2c.tags.total_refs 4010491 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 402643 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 9.960414 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 54619.974232 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2262.532885 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2731.767010 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 536.522208 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 599.592732 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2415.786794 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 2253.390757 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.833435 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.034524 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.041683 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.008187 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.009149 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.036862 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.034384 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.998223 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 54563.896309 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2274.571035 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2764.017947 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 537.574504 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 599.716909 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2426.240023 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 2253.181956 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.832579 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.034707 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.042176 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.008203 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.009151 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.037021 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.034381 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.998218 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 974 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 6067 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 2636 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55307 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 1020 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 5977 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 2679 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55308 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 26265257 # Number of tag accesses -system.l2c.tags.data_accesses 26265257 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 499689 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 475179 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 126551 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 83555 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 324793 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 258988 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1768755 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 835707 # number of Writeback hits -system.l2c.Writeback_hits::total 835707 # number of Writeback hits +system.l2c.tags.tag_accesses 38452030 # Number of tag accesses +system.l2c.tags.data_accesses 38452030 # Number of data accesses +system.l2c.Writeback_hits::writebacks 835740 # number of Writeback hits +system.l2c.Writeback_hits::total 835740 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 8 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 12 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu2.data 9 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 9 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 89325 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 26026 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 71615 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 186966 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 499689 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 564504 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 126551 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 109581 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 324793 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 330603 # number of demand (read+write) hits -system.l2c.demand_hits::total 1955721 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 499689 # number of overall hits -system.l2c.overall_hits::cpu0.data 564504 # number of overall hits -system.l2c.overall_hits::cpu1.inst 126551 # number of overall hits -system.l2c.overall_hits::cpu1.data 109581 # number of overall hits -system.l2c.overall_hits::cpu2.inst 324793 # number of overall hits -system.l2c.overall_hits::cpu2.data 330603 # number of overall hits -system.l2c.overall_hits::total 1955721 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 7307 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 240797 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2297 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 15641 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 4814 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 16829 # number of ReadReq misses -system.l2c.ReadReq_misses::total 287685 # number of ReadReq misses +system.l2c.UpgradeReq_hits::cpu2.data 9 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 13 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu2.data 8 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 8 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 89227 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 26157 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 71638 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 187022 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 499466 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 126720 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu2.inst 325465 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 951651 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 475379 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 83798 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu2.data 258654 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 817831 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.inst 499466 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 564606 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 126720 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 109955 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 325465 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 330292 # number of demand (read+write) hits +system.l2c.demand_hits::total 1956504 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 499466 # number of overall hits +system.l2c.overall_hits::cpu0.data 564606 # number of overall hits +system.l2c.overall_hits::cpu1.inst 126720 # number of overall hits +system.l2c.overall_hits::cpu1.data 109955 # number of overall hits +system.l2c.overall_hits::cpu2.inst 325465 # number of overall hits +system.l2c.overall_hits::cpu2.data 330292 # number of overall hits +system.l2c.overall_hits::total 1956504 # number of overall hits system.l2c.UpgradeReq_misses::cpu0.data 8 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 11 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 19 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 22 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 30 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu2.data 2 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 73385 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 17971 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 24427 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 115783 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 7307 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 314182 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2297 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 33612 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 4814 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 41256 # number of demand (read+write) misses -system.l2c.demand_misses::total 403468 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 7307 # number of overall misses -system.l2c.overall_misses::cpu0.data 314182 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2297 # number of overall misses -system.l2c.overall_misses::cpu1.data 33612 # number of overall misses -system.l2c.overall_misses::cpu2.inst 4814 # number of overall misses -system.l2c.overall_misses::cpu2.data 41256 # number of overall misses -system.l2c.overall_misses::total 403468 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu1.inst 187459250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 1164603000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 400569000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 1256121750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 3008753000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2.data 337497 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 337497 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu2.data 62998 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 62998 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1363186490 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 2153546721 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 3516733211 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu1.inst 187459250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 2527789490 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 400569000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 3409668471 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 6525486211 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu1.inst 187459250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 2527789490 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 400569000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 3409668471 # number of overall miss cycles -system.l2c.overall_miss_latency::total 6525486211 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 506996 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 715976 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 128848 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 99196 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 329607 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 275817 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2056440 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 835707 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 835707 # number of Writeback accesses(hits+misses) +system.l2c.ReadExReq_misses::cpu0.data 73126 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 17974 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 24645 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 115745 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 7275 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 2299 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu2.inst 4804 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 14378 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 240531 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 15769 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu2.data 16968 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 273268 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.inst 7275 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 313657 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2299 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 33743 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 4804 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 41613 # number of demand (read+write) misses +system.l2c.demand_misses::total 403391 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 7275 # number of overall misses +system.l2c.overall_misses::cpu0.data 313657 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2299 # number of overall misses +system.l2c.overall_misses::cpu1.data 33743 # number of overall misses +system.l2c.overall_misses::cpu2.inst 4804 # number of overall misses +system.l2c.overall_misses::cpu2.data 41613 # number of overall misses +system.l2c.overall_misses::total 403391 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu2.data 332500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 332500 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu2.data 61500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 61500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 1367951000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 2193367000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 3561318000 # number of ReadExReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu1.inst 186458500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu2.inst 394826500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 581285000 # number of ReadCleanReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 1169012500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu2.data 1264906000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 2433918500 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu1.inst 186458500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 2536963500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 394826500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 3458273000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 6576521500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu1.inst 186458500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 2536963500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 394826500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 3458273000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 6576521500 # number of overall miss cycles +system.l2c.Writeback_accesses::writebacks 835740 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 835740 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 11 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 1 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 19 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 31 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu2.data 11 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 11 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 162710 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 43997 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 96042 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 302749 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 506996 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 878686 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 128848 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 143193 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 329607 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 371859 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2359189 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 506996 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 878686 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 128848 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 143193 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 329607 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 371859 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2359189 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.014412 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.336320 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.017827 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.157678 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.014605 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.061015 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.139895 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_accesses::cpu2.data 31 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 43 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu2.data 10 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 10 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 162353 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 44131 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 96283 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 302767 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 506741 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 129019 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu2.inst 330269 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 966029 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 715910 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 99567 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu2.data 275622 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 1091099 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 506741 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 878263 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 129019 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 143698 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 330269 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 371905 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2359895 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 506741 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 878263 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 129019 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 143698 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 330269 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 371905 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2359895 # number of overall (read+write) accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.727273 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 0.578947 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.612903 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu2.data 0.181818 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.181818 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.451017 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.408460 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 0.254337 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.382439 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.014412 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.357559 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.017827 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.234732 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.014605 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.110945 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.171020 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.014412 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.357559 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.017827 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.234732 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.014605 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.110945 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.171020 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 81610.470178 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 74458.346653 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 83209.181554 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 74640.308396 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 10458.498010 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 30681.545455 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 17763 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu2.data 31499 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 31499 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75854.793278 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 88162.554591 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 30373.484976 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 81610.470178 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 75204.971141 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 83209.181554 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 82646.608275 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 16173.491357 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 81610.470178 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 75204.971141 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 83209.181554 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 82646.608275 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 16173.491357 # average overall miss latency +system.l2c.UpgradeReq_miss_rate::cpu2.data 0.709677 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.697674 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu2.data 0.200000 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.200000 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.450414 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.407287 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 0.255964 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.382291 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.014356 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.017819 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.014546 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.014884 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.335979 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.158376 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.061563 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.250452 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.014356 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.357133 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.017819 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.234819 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.014546 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.111891 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.170936 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.014356 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.357133 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.017819 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.234819 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.014546 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.111891 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.170936 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 15113.636364 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 11083.333333 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu2.data 30750 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 30750 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 76107.210415 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 88998.458105 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 30768.655233 # average ReadExReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 81104.175729 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 82187.031640 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 40428.780081 # average ReadCleanReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 74133.584882 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 74546.558227 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 8906.708799 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 81104.175729 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 75184.882791 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 82187.031640 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 83105.592002 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 16303.094268 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 81104.175729 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 75184.882791 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 82187.031640 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 83105.592002 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 16303.094268 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1719,209 +1733,222 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 75392 # number of writebacks -system.l2c.writebacks::total 75392 # number of writebacks -system.l2c.ReadReq_mshr_misses::cpu1.inst 2297 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 15641 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 4814 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 16829 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 39581 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 11 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 11 # number of UpgradeReq MSHR misses +system.l2c.writebacks::writebacks 75436 # number of writebacks +system.l2c.writebacks::total 75436 # number of writebacks +system.l2c.CleanEvict_mshr_misses::writebacks 185 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 185 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 22 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 22 # number of UpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu2.data 2 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 17971 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 24427 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 42398 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 2297 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 33612 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 4814 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 41256 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 81979 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 2297 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 33612 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 4814 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 41256 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 81979 # number of overall MSHR misses -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 1102 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu2.data 1563 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 2665 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 1382 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu2.data 2131 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 3513 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 2484 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu2.data 3694 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 6178 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 158665250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 968947500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 340372000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 1046522250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 2514507000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 347508 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 347508 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data 36002 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 36002 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1138484010 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1854617279 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 2993101289 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 158665250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 2107431510 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 340372000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 2901139529 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 5507608289 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 158665250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 2107431510 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 340372000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 2901139529 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 5507608289 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 207045500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 309444000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 516489500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 276013000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 418496000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 694509000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 483058500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 727940000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 1210998500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.017827 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.157678 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.014605 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.061015 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.019247 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.578947 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.354839 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.181818 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.181818 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.408460 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.254337 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.140043 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.017827 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.234732 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014605 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.110945 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.034749 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.017827 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.234732 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014605 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.110945 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.034749 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69074.989116 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 61949.204015 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 70704.611550 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 62185.646800 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 63528.132185 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 31591.636364 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 31591.636364 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 18001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 18001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63351.177453 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 75924.889630 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 70595.341502 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69074.989116 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62698.783470 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 70704.611550 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 70320.426823 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 67183.160187 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69074.989116 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62698.783470 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 70704.611550 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 70320.426823 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 67183.160187 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 187881.578947 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 197980.806142 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 193804.690432 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 199719.971056 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 196384.795870 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 197696.840307 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 194467.995169 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 197060.097455 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 196017.886047 # average overall mshr uncacheable latency +system.l2c.ReadExReq_mshr_misses::cpu1.data 17974 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 24645 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 42619 # number of ReadExReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 2299 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 4804 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::total 7103 # number of ReadCleanReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 15769 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu2.data 16968 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 32737 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 2299 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 33743 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 4804 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 41613 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 82459 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 2299 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 33743 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 4804 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 41613 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 82459 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 1108 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu2.data 1559 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 2667 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 1387 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu2.data 2128 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 3515 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 2495 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu2.data 3687 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 6182 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 607000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 607000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data 41500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 41500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1188211000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1946917000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 3135128000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 163468500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 346786500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 510255000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 1011322500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 1095840500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 2107163000 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 163468500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 2199533500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 346786500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 3042757500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 5752546000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 163468500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 2199533500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 346786500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 3042757500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 5752546000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 212604500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 314976000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 527580500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 282475000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 426484500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 708959500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 495079500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 741460500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1236540000 # number of overall MSHR uncacheable cycles +system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.709677 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.511628 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.200000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.200000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.407287 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.255964 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.140765 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.017819 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.014546 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.007353 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.158376 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.061563 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.030004 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.017819 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.234819 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014546 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.111891 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.034942 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.017819 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.234819 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014546 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.111891 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.034942 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 27590.909091 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 27590.909091 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 20750 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20750 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 66107.210415 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 78998.458105 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 73561.744762 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 71104.175729 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 72187.031640 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 71836.547937 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 64133.584882 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 64582.773456 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 64366.404985 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71104.175729 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65184.882791 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 72187.031640 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 73120.359022 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 69762.500152 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71104.175729 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65184.882791 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 72187.031640 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 73120.359022 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 69762.500152 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 191881.317690 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 202037.203335 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197817.960255 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 203658.976208 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 200415.648496 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 201695.448080 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 198428.657315 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 201101.301871 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 200022.646393 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 295002 # Transaction distribution -system.membus.trans_dist::ReadResp 294996 # Transaction distribution +system.membus.trans_dist::ReadReq 7144 # Transaction distribution +system.membus.trans_dist::ReadResp 294958 # Transaction distribution system.membus.trans_dist::WriteReq 9810 # Transaction distribution system.membus.trans_dist::WriteResp 9810 # Transaction distribution -system.membus.trans_dist::Writeback 116904 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 145 # Transaction distribution +system.membus.trans_dist::Writeback 116948 # Transaction distribution +system.membus.trans_dist::CleanEvict 262295 # Transaction distribution +system.membus.trans_dist::UpgradeReq 165 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 147 # Transaction distribution -system.membus.trans_dist::ReadExReq 115657 # Transaction distribution -system.membus.trans_dist::ReadExResp 115657 # Transaction distribution -system.membus.trans_dist::BadAddressError 6 # Transaction distribution +system.membus.trans_dist::UpgradeResp 167 # Transaction distribution +system.membus.trans_dist::ReadExReq 115610 # Transaction distribution +system.membus.trans_dist::ReadExResp 115610 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 287819 # Transaction distribution +system.membus.trans_dist::BadAddressError 5 # Transaction distribution +system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 33908 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 882256 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 12 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 916176 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124907 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124907 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1041083 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1144349 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 10 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1178267 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125023 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 125023 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1303290 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 45568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30632256 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 30677824 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5323648 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 5323648 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36001472 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30629632 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 30675200 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2664320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2664320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33339520 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 157 # Total snoops (count) -system.membus.snoop_fanout::samples 579090 # Request fanout histogram +system.membus.snoop_fanout::samples 841413 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 579090 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 841413 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 579090 # Request fanout histogram -system.membus.reqLayer0.occupancy 11072500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 841413 # Request fanout histogram +system.membus.reqLayer0.occupancy 11052000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 412860298 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 394258327 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 7000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 438835201 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 441332932 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 17657500 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 29902743 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 2063715 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2063694 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 7144 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2064402 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 9810 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 9810 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 835707 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 17293 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 31 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 42 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 302749 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 302749 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 6 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1930984 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3657230 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5588214 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 61790208 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142733184 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 204523392 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 41934 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3253691 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.012828 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.112532 # Request fanout histogram +system.toL2Bus.trans_dist::Writeback 883212 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1574760 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 43 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 10 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 53 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 302767 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 302767 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 966109 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1091169 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 5 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 17280 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2897413 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4214892 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7112305 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 61827200 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142743552 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 204570752 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 141567 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 4877075 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.028983 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.167759 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 3211953 98.72% 98.72% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 41738 1.28% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 4735723 97.10% 97.10% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 141352 2.90% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3253691 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1080719000 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 4877075 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1372572500 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 82500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 689338845 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 689392754 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 790311532 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 777864461 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index c18c16475..b25b92aa6 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -1,160 +1,164 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.846034 # Number of seconds simulated -sim_ticks 2846033690500 # Number of ticks simulated -final_tick 2846033690500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.846047 # Number of seconds simulated +sim_ticks 2846047385500 # Number of ticks simulated +final_tick 2846047385500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 166502 # Simulator instruction rate (inst/s) -host_op_rate 201645 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3701777010 # Simulator tick rate (ticks/s) -host_mem_usage 652712 # Number of bytes of host memory used -host_seconds 768.83 # Real time elapsed on the host -sim_insts 128011279 # Number of instructions simulated -sim_ops 155030352 # Number of ops (including micro ops) simulated +host_inst_rate 159625 # Simulator instruction rate (inst/s) +host_op_rate 193311 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3563510303 # Simulator tick rate (ticks/s) +host_mem_usage 654020 # Number of bytes of host memory used +host_seconds 798.66 # Real time elapsed on the host +sim_insts 127487011 # Number of instructions simulated +sim_ops 154390534 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 8384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 7424 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1665600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1328952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8468032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 219456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 635604 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 399104 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1468992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1221616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8255360 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 2560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 381888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 706136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 588160 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12726924 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1665600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 219456 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1885056 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8843968 # Number of bytes written to this memory +system.physmem.bytes_read::total 12633224 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1468992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 381888 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1850880 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8928128 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8861532 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 131 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8945692 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 116 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 26025 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 21289 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 132313 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 12 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3429 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 9952 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 6236 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 22953 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 19610 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 128990 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 40 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5967 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 11055 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 9190 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 199403 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 138187 # Number of write requests responded to by this memory +system.physmem.num_reads::total 197938 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 139502 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142578 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2946 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 143893 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2609 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 585236 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 466949 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2975380 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 270 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 77109 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 223330 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 140232 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 516152 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 429232 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2900640 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 899 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 22 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 134182 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 248111 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 206659 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4471811 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 585236 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 77109 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 662345 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3107471 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4438866 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 516152 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 134182 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 650334 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3137027 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6157 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3113643 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3107471 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2946 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3143199 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3137027 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2609 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 585236 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 473106 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2975380 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 270 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 77109 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 223344 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 140232 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 516152 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 435390 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2900640 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 899 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 134182 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 248125 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 206659 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7585453 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 199403 # Number of read requests accepted -system.physmem.writeReqs 178802 # Number of write requests accepted -system.physmem.readBursts 199403 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 178802 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12754816 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6976 # Total number of bytes read from write queue -system.physmem.bytesWritten 9923392 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12726924 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 11179868 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 109 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 23728 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 14293 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12446 # Per bank write bursts -system.physmem.perBankRdBursts::1 12462 # Per bank write bursts -system.physmem.perBankRdBursts::2 12648 # Per bank write bursts -system.physmem.perBankRdBursts::3 12635 # Per bank write bursts -system.physmem.perBankRdBursts::4 15144 # Per bank write bursts -system.physmem.perBankRdBursts::5 12384 # Per bank write bursts -system.physmem.perBankRdBursts::6 13114 # Per bank write bursts -system.physmem.perBankRdBursts::7 13234 # Per bank write bursts -system.physmem.perBankRdBursts::8 12297 # Per bank write bursts -system.physmem.perBankRdBursts::9 12473 # Per bank write bursts -system.physmem.perBankRdBursts::10 12152 # Per bank write bursts -system.physmem.perBankRdBursts::11 11219 # Per bank write bursts -system.physmem.perBankRdBursts::12 11569 # Per bank write bursts -system.physmem.perBankRdBursts::13 12199 # Per bank write bursts -system.physmem.perBankRdBursts::14 11629 # Per bank write bursts -system.physmem.perBankRdBursts::15 11689 # Per bank write bursts -system.physmem.perBankWrBursts::0 9980 # Per bank write bursts -system.physmem.perBankWrBursts::1 10101 # Per bank write bursts -system.physmem.perBankWrBursts::2 10187 # Per bank write bursts -system.physmem.perBankWrBursts::3 9953 # Per bank write bursts -system.physmem.perBankWrBursts::4 9212 # Per bank write bursts -system.physmem.perBankWrBursts::5 9585 # Per bank write bursts -system.physmem.perBankWrBursts::6 10195 # Per bank write bursts -system.physmem.perBankWrBursts::7 10328 # Per bank write bursts -system.physmem.perBankWrBursts::8 9559 # Per bank write bursts -system.physmem.perBankWrBursts::9 9737 # Per bank write bursts -system.physmem.perBankWrBursts::10 9778 # Per bank write bursts -system.physmem.perBankWrBursts::11 9524 # Per bank write bursts -system.physmem.perBankWrBursts::12 9387 # Per bank write bursts -system.physmem.perBankWrBursts::13 9312 # Per bank write bursts -system.physmem.perBankWrBursts::14 9249 # Per bank write bursts -system.physmem.perBankWrBursts::15 8966 # Per bank write bursts +system.physmem.bw_total::total 7582065 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 197938 # Number of read requests accepted +system.physmem.writeReqs 143893 # Number of write requests accepted +system.physmem.readBursts 197938 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 143893 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12658432 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9600 # Total number of bytes read from write queue +system.physmem.bytesWritten 8958080 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12633224 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8945692 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 150 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3897 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 51249 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 12124 # Per bank write bursts +system.physmem.perBankRdBursts::1 12298 # Per bank write bursts +system.physmem.perBankRdBursts::2 12956 # Per bank write bursts +system.physmem.perBankRdBursts::3 12344 # Per bank write bursts +system.physmem.perBankRdBursts::4 15465 # Per bank write bursts +system.physmem.perBankRdBursts::5 12573 # Per bank write bursts +system.physmem.perBankRdBursts::6 12691 # Per bank write bursts +system.physmem.perBankRdBursts::7 13082 # Per bank write bursts +system.physmem.perBankRdBursts::8 12243 # Per bank write bursts +system.physmem.perBankRdBursts::9 12357 # Per bank write bursts +system.physmem.perBankRdBursts::10 11723 # Per bank write bursts +system.physmem.perBankRdBursts::11 11147 # Per bank write bursts +system.physmem.perBankRdBursts::12 12049 # Per bank write bursts +system.physmem.perBankRdBursts::13 11871 # Per bank write bursts +system.physmem.perBankRdBursts::14 11344 # Per bank write bursts +system.physmem.perBankRdBursts::15 11521 # Per bank write bursts +system.physmem.perBankWrBursts::0 8574 # Per bank write bursts +system.physmem.perBankWrBursts::1 8801 # Per bank write bursts +system.physmem.perBankWrBursts::2 9504 # Per bank write bursts +system.physmem.perBankWrBursts::3 8801 # Per bank write bursts +system.physmem.perBankWrBursts::4 8786 # Per bank write bursts +system.physmem.perBankWrBursts::5 8838 # Per bank write bursts +system.physmem.perBankWrBursts::6 9085 # Per bank write bursts +system.physmem.perBankWrBursts::7 9267 # Per bank write bursts +system.physmem.perBankWrBursts::8 8941 # Per bank write bursts +system.physmem.perBankWrBursts::9 8908 # Per bank write bursts +system.physmem.perBankWrBursts::10 8524 # Per bank write bursts +system.physmem.perBankWrBursts::11 8283 # Per bank write bursts +system.physmem.perBankWrBursts::12 8972 # Per bank write bursts +system.physmem.perBankWrBursts::13 8287 # Per bank write bursts +system.physmem.perBankWrBursts::14 8306 # Per bank write bursts +system.physmem.perBankWrBursts::15 8093 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 44 # Number of times write queue was full causing retry -system.physmem.totGap 2846033184500 # Total gap between requests +system.physmem.numWrRetry 26 # Number of times write queue was full causing retry +system.physmem.totGap 2846046899000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 555 # Read request sizes (log2) +system.physmem.readPktSize::2 554 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 198820 # Read request sizes (log2) +system.physmem.readPktSize::6 197356 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 174411 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 98514 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 48367 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13227 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9811 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7788 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6331 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5269 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4641 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3767 # What read queue length does an incoming req see +system.physmem.writePktSize::6 139502 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 97008 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 48975 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 12438 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9719 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7811 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6380 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5314 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4715 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3822 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 751 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 267 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 262 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 163 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 134 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 280 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 267 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 162 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 133 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -184,195 +188,191 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3752 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5374 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6525 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7029 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7429 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8469 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10884 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8455 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7898 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1553 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1516 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2621 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1870 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1722 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2069 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1894 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1948 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1965 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1529 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1415 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1463 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1090 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 724 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 387 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4836 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6014 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6576 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8463 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8832 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 10148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9569 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8822 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9294 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10498 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8607 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 332 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 49 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 62 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 91619 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 247.526648 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 138.939609 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 308.892335 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 48258 52.67% 52.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17913 19.55% 72.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6311 6.89% 79.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3675 4.01% 83.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2817 3.07% 86.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1472 1.61% 87.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1018 1.11% 88.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1004 1.10% 90.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9151 9.99% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 91619 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6524 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 30.547670 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 556.789065 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6523 99.98% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6524 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6524 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.766554 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.625948 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 41.024429 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 6179 94.71% 94.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 85 1.30% 96.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 25 0.38% 96.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 12 0.18% 96.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 31 0.48% 97.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 34 0.52% 97.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 24 0.37% 97.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 11 0.17% 98.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 15 0.23% 98.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 5 0.08% 98.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 12 0.18% 98.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 17 0.26% 98.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 13 0.20% 99.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 5 0.08% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 4 0.06% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 3 0.05% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 4 0.06% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 2 0.03% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 4 0.06% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 3 0.05% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 3 0.05% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 16 0.25% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 1 0.02% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 3 0.05% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 2 0.03% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 2 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 4 0.06% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::560-575 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::640-655 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::704-719 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::880-895 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6524 # Writes before turning the bus around for reads -system.physmem.totQLat 5653495532 # Total ticks spent queuing -system.physmem.totMemAccLat 9390258032 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 996470000 # Total ticks spent in databus transfers -system.physmem.avgQLat 28367.62 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::63 93 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 90544 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 238.739707 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 135.462322 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 300.134416 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 48559 53.63% 53.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17642 19.48% 73.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6276 6.93% 80.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3581 3.95% 84.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2857 3.16% 87.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1437 1.59% 88.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 927 1.02% 89.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1107 1.22% 90.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8158 9.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 90544 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6994 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.279525 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 555.958801 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6993 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6994 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6994 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.012868 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.560049 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.293161 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5872 83.96% 83.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 361 5.16% 89.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 205 2.93% 92.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 59 0.84% 92.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 60 0.86% 93.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 157 2.24% 96.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 22 0.31% 96.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 8 0.11% 96.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 14 0.20% 96.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 7 0.10% 96.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 6 0.09% 96.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 8 0.11% 96.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 162 2.32% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 3 0.04% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 7 0.10% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 9 0.13% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 3 0.04% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.01% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.01% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.01% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.01% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.01% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 12 0.17% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 2 0.03% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 3 0.04% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 6 0.09% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 2 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6994 # Writes before turning the bus around for reads +system.physmem.totQLat 5635724944 # Total ticks spent queuing +system.physmem.totMemAccLat 9344249944 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 988940000 # Total ticks spent in databus transfers +system.physmem.avgQLat 28493.77 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47117.62 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.48 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.49 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.47 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.93 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 47243.77 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.45 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.15 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.44 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.14 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage -system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.06 # Average write queue length when enqueuing -system.physmem.readRowHits 165654 # Number of row buffer hits during reads -system.physmem.writeRowHits 97073 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.12 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 62.60 # Row buffer hit rate for writes -system.physmem.avgGap 7525107.24 # Average gap between requests -system.physmem.pageHitRate 74.14 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 361662840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 197335875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 811722600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 515425680 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 185888851200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 83071861560 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1634748153750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1905595013505 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.562437 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2719423686494 # Time in different power states -system.physmem_0.memoryStateTime::REF 95035200000 # Time in different power states +system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.58 # Average write queue length when enqueuing +system.physmem.readRowHits 164502 # Number of row buffer hits during reads +system.physmem.writeRowHits 82711 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.17 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 59.08 # Row buffer hit rate for writes +system.physmem.avgGap 8325888.81 # Average gap between requests +system.physmem.pageHitRate 73.19 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 356257440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 194386500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 807557400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 464330880 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 185889868320 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 83150566875 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1634688457500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1905551424915 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.543458 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2719326804644 # Time in different power states +system.physmem_0.memoryStateTime::REF 95035720000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 31571473506 # Time in different power states +system.physmem_0.memoryStateTime::ACT 31683407856 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 330976800 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 180592500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 742762800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 489317760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 185888851200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 82401250860 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1635336408750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1905370160670 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.483431 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2720410023695 # Time in different power states -system.physmem_1.memoryStateTime::REF 95035200000 # Time in different power states +system.physmem_1.actEnergy 328255200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 179107500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 735181200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 442674720 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 185889868320 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 82066427730 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1635639456750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1905280971420 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.448430 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2720915660225 # Time in different power states +system.physmem_1.memoryStateTime::REF 95035720000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30588353805 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30095909775 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.bytes_read::cpu0.inst 448 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 1216 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 448 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 768 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 1216 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 7 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 19 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 157 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 270 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 427 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 157 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 270 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 427 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 157 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 270 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 427 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 832 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 1344 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 512 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 832 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 1344 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 21 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 180 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 292 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 472 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 180 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 292 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 472 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 180 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 292 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 472 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 20699653 # Number of BP lookups -system.cpu0.branchPred.condPredicted 13612367 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1051860 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 13249801 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 9339959 # Number of BTB hits +system.cpu0.branchPred.lookups 19568417 # Number of BP lookups +system.cpu0.branchPred.condPredicted 12741959 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 982246 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 12413476 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 8819135 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 70.491315 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 3411685 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 215338 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 71.044847 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 3284365 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 198035 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -403,58 +403,58 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 70748 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 70748 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 47364 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 23384 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 70748 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 70748 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 70748 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 6854 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 9215.640648 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 8072.361115 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 6078.265155 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 6652 97.05% 97.05% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 190 2.77% 99.82% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 4 0.06% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-98303 6 0.09% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::212992-229375 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 6854 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 328505000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 328505000 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 328505000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5278 77.01% 77.01% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1576 22.99% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6854 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 70748 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 67683 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 67683 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 45041 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 22642 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 67683 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 67683 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 67683 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 6748 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 10568.612922 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 9555.209008 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 5781.304513 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 6579 97.50% 97.50% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 156 2.31% 99.81% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 6 0.09% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 4 0.06% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-114687 2 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 6748 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 327753000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 327753000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 327753000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 5177 76.72% 76.72% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1571 23.28% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6748 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 67683 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 70748 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6854 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 67683 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6748 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6854 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 77602 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6748 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 74431 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 17365788 # DTB read hits -system.cpu0.dtb.read_misses 64419 # DTB read misses -system.cpu0.dtb.write_hits 14563883 # DTB write hits -system.cpu0.dtb.write_misses 6329 # DTB write misses +system.cpu0.dtb.read_hits 16473000 # DTB read hits +system.cpu0.dtb.read_misses 62137 # DTB read misses +system.cpu0.dtb.write_hits 13870452 # DTB write hits +system.cpu0.dtb.write_misses 5546 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3519 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1310 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1951 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3508 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1130 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1591 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 572 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 17430207 # DTB read accesses -system.cpu0.dtb.write_accesses 14570212 # DTB write accesses +system.cpu0.dtb.perms_faults 561 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 16535137 # DTB read accesses +system.cpu0.dtb.write_accesses 13875998 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31929671 # DTB hits -system.cpu0.dtb.misses 70748 # DTB misses -system.cpu0.dtb.accesses 32000419 # DTB accesses +system.cpu0.dtb.hits 30343452 # DTB hits +system.cpu0.dtb.misses 67683 # DTB misses +system.cpu0.dtb.accesses 30411135 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -484,39 +484,36 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 3844 # Table walker walks requested -system.cpu0.itb.walker.walksShort 3844 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walks 3854 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3854 # Table walker walks initiated with short descriptors system.cpu0.itb.walker.walksShortTerminationLevel::Level1 307 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3537 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 3844 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 3844 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 3844 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2412 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 9287.312604 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 8105.691907 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 5199.777734 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 996 41.29% 41.29% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1373 56.92% 98.22% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 5 0.21% 98.42% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 35 1.45% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::40960-49151 2 0.08% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2412 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 328041000 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 328041000 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 328041000 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2112 87.56% 87.56% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 300 12.44% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2412 # Table walker page sizes translated +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3547 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3854 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3854 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3854 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2418 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 10984.077750 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 9918.433232 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 7783.469031 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 2416 99.92% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::294912-327679 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2418 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 327059500 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 327059500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 327059500 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 2118 87.59% 87.59% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 300 12.41% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2418 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3844 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3844 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3854 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3854 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2412 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2412 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 6256 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 38673096 # ITB inst hits -system.cpu0.itb.inst_misses 3844 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2418 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2418 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 6272 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 36667532 # ITB inst hits +system.cpu0.itb.inst_misses 3854 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -525,131 +522,131 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2215 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2221 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 7305 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 7326 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 38676940 # ITB inst accesses -system.cpu0.itb.hits 38673096 # DTB hits -system.cpu0.itb.misses 3844 # DTB misses -system.cpu0.itb.accesses 38676940 # DTB accesses -system.cpu0.numCycles 164345884 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 36671386 # ITB inst accesses +system.cpu0.itb.hits 36667532 # DTB hits +system.cpu0.itb.misses 3854 # DTB misses +system.cpu0.itb.accesses 36671386 # DTB accesses +system.cpu0.numCycles 154642199 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 79729346 # Number of instructions committed -system.cpu0.committedOps 95953153 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 5189304 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 1865 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 5527748141 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.061297 # CPI: cycles per instruction -system.cpu0.ipc 0.485131 # IPC: instructions per cycle +system.cpu0.committedInsts 75578579 # Number of instructions committed +system.cpu0.committedOps 90977347 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 4937651 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 2060 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 5537489017 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.046111 # CPI: cycles per instruction +system.cpu0.ipc 0.488732 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1866 # number of quiesce instructions executed -system.cpu0.tickCycles 127709647 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 36636237 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 716917 # number of replacements -system.cpu0.dcache.tags.tagsinuse 500.984031 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 30425669 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 717429 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 42.409310 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 346166500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.984031 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.978484 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.978484 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 2062 # number of quiesce instructions executed +system.cpu0.tickCycles 120829876 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 33812323 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 679563 # number of replacements +system.cpu0.dcache.tags.tagsinuse 486.133146 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 28909958 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 680075 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 42.509956 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 345411000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 486.133146 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.949479 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.949479 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 342 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 316 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 61 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63847334 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63847334 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 15827695 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 15827695 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 13439418 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 13439418 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 321505 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 321505 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365521 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 365521 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361496 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 361496 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 29267113 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 29267113 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 29588618 # number of overall hits -system.cpu0.dcache.overall_hits::total 29588618 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 465920 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 465920 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 577900 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 577900 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 136723 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 136723 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21141 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21141 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20265 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20265 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1043820 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1043820 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1180543 # number of overall misses -system.cpu0.dcache.overall_misses::total 1180543 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6144584831 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 6144584831 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 9172351028 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 9172351028 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 319190979 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 319190979 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 453656289 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 453656289 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 133500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 133500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 15316935859 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 15316935859 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 15316935859 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 15316935859 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 16293615 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 16293615 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 14017318 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 14017318 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 458228 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 458228 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386662 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 386662 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381761 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 381761 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 30310933 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 30310933 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 30769161 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 30769161 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028595 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.028595 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041228 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.041228 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.298373 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.298373 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054676 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054676 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053083 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053083 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.034437 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.034437 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.038368 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.038368 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13188.068404 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13188.068404 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15871.865423 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 15871.865423 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15098.196821 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15098.196821 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22386.197335 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22386.197335 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 60679422 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 60679422 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 14995018 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 14995018 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 12788335 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 12788335 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 306891 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 306891 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 356622 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 356622 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 352102 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 352102 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 27783353 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 27783353 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 28090244 # number of overall hits +system.cpu0.dcache.overall_hits::total 28090244 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 441719 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 441719 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 557349 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 557349 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 131939 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 131939 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21205 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21205 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21309 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 21309 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 999068 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 999068 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1131007 # number of overall misses +system.cpu0.dcache.overall_misses::total 1131007 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5838844500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5838844500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8827018500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 8827018500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 323291000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 323291000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 480994000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 480994000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 412000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 412000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 14665863000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 14665863000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 14665863000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 14665863000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 15436737 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 15436737 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 13345684 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 13345684 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 438830 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 438830 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 377827 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 377827 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 373411 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 373411 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 28782421 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 28782421 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 29221251 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 29221251 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028615 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.028615 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041762 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.041762 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.300661 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.300661 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056124 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056124 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.057066 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.057066 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.034711 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.034711 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.038705 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.038705 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13218.459020 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13218.459020 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15837.506661 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 15837.506661 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15245.979722 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15245.979722 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22572.340326 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22572.340326 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14673.924488 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 14673.924488 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12974.483656 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 12974.483656 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14679.544335 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 14679.544335 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12967.084200 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 12967.084200 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -658,149 +655,149 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 515635 # number of writebacks -system.cpu0.dcache.writebacks::total 515635 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 72452 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 72452 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 253659 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 253659 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14673 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14673 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 326111 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 326111 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 326111 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 326111 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 393468 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 393468 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 324241 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 324241 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 103543 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 103543 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6468 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6468 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20265 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 20265 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 717709 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 717709 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 821252 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 821252 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20388 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20388 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19084 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19084 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39472 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39472 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4430984378 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4430984378 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4926577100 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4926577100 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1621170703 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1621170703 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 96485758 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 96485758 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 422555211 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 422555211 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 127500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 127500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9357561478 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9357561478 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10978732181 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10978732181 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4278812500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4278812500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3259105000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3259105000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7537917500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7537917500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024149 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024149 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023131 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023131 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225964 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225964 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016728 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016728 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053083 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053083 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023678 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.023678 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026691 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.026691 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11261.358936 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11261.358936 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15194.183031 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15194.183031 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15656.980221 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15656.980221 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14917.402288 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14917.402288 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20851.478460 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20851.478460 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 493293 # number of writebacks +system.cpu0.dcache.writebacks::total 493293 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 69842 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 69842 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 244235 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 244235 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15018 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15018 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 314077 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 314077 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 314077 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 314077 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 371877 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 371877 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 313114 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 313114 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 99356 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 99356 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6187 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6187 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21309 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 21309 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 684991 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 684991 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 784347 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 784347 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 18002 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 18002 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16758 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 16758 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 34760 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 34760 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4380232500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4380232500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4918203500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4918203500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1623471000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1623471000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 94288500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 94288500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 459695000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 459695000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 402000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 402000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9298436000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9298436000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10921907000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10921907000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3751545500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3751545500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2725656000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2725656000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6477201500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6477201500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024090 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024090 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023462 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023462 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.226411 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.226411 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016375 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016375 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.057066 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.057066 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023799 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.023799 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026842 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.026842 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11778.713123 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11778.713123 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15707.389321 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15707.389321 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16339.939209 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16339.939209 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15239.776952 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15239.776952 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21572.809611 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21572.809611 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13038.099673 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13038.099673 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13368.286690 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13368.286690 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209869.163233 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209869.163233 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170776.828757 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 170776.828757 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 190968.724666 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 190968.724666 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13574.537476 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13574.537476 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13924.840664 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13924.840664 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208396.039329 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208396.039329 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162648.048693 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 162648.048693 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 186340.664557 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 186340.664557 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1965366 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.785087 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 36699580 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1965878 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 18.668290 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6403533250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.785087 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999580 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999580 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 1878063 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.785549 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 34781277 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1878575 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 18.514713 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6156628000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.785549 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999581 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999581 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 228 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 102 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 179 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 79296841 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 79296841 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 36699580 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 36699580 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 36699580 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 36699580 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 36699580 # number of overall hits -system.cpu0.icache.overall_hits::total 36699580 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1965894 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1965894 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1965894 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1965894 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1965894 # number of overall misses -system.cpu0.icache.overall_misses::total 1965894 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18549717200 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 18549717200 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 18549717200 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 18549717200 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 18549717200 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 18549717200 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 38665474 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 38665474 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 38665474 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 38665474 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 38665474 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 38665474 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050844 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.050844 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050844 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.050844 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050844 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.050844 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9435.766730 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9435.766730 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9435.766730 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9435.766730 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9435.766730 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9435.766730 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 75198332 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 75198332 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 34781277 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 34781277 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 34781277 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 34781277 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 34781277 # number of overall hits +system.cpu0.icache.overall_hits::total 34781277 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1878593 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1878593 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1878593 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1878593 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1878593 # number of overall misses +system.cpu0.icache.overall_misses::total 1878593 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 17494191500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 17494191500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 17494191500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 17494191500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 17494191500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 17494191500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 36659870 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 36659870 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 36659870 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 36659870 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 36659870 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 36659870 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.051244 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.051244 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.051244 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.051244 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.051244 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.051244 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9312.390443 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9312.390443 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9312.390443 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9312.390443 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9312.390443 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9312.390443 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -809,426 +806,463 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1965894 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1965894 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1965894 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1965894 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1965894 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1965894 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3367 # number of ReadReq MSHR uncacheable -system.cpu0.icache.ReadReq_mshr_uncacheable::total 3367 # number of ReadReq MSHR uncacheable -system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3367 # number of overall MSHR uncacheable misses -system.cpu0.icache.overall_mshr_uncacheable_misses::total 3367 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 16574456804 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 16574456804 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 16574456804 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 16574456804 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 16574456804 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 16574456804 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 310652000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 310652000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 310652000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 310652000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.050844 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.050844 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.050844 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.050844 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.050844 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.050844 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8431.002284 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8431.002284 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8431.002284 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 8431.002284 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8431.002284 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 8431.002284 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92263.736264 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92263.736264 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92263.736264 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92263.736264 # average overall mshr uncacheable latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1878593 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1878593 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1878593 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1878593 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1878593 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1878593 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3426 # number of ReadReq MSHR uncacheable +system.cpu0.icache.ReadReq_mshr_uncacheable::total 3426 # number of ReadReq MSHR uncacheable +system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3426 # number of overall MSHR uncacheable misses +system.cpu0.icache.overall_mshr_uncacheable_misses::total 3426 # number of overall MSHR uncacheable misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 16554895500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 16554895500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 16554895500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 16554895500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 16554895500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 16554895500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 314279000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 314279000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 314279000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 314279000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.051244 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.051244 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.051244 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.051244 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.051244 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.051244 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8812.390709 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8812.390709 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8812.390709 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 8812.390709 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8812.390709 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 8812.390709 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 91733.508465 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 91733.508465 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 91733.508465 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 91733.508465 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1838784 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1838936 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 132 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1765882 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1765970 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 77 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 233824 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 299625 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16147.057230 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 2915503 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 315876 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 9.229897 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 224118 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 286262 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16059.277635 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 4797112 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 302498 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 15.858326 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 6737.365934 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 57.298987 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.096459 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5766.699762 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1949.490017 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1636.106070 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.411216 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003497 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000006 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.351971 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.118987 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.099860 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.985538 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1040 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15197 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 14 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 337 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 404 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 285 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_blocks::writebacks 8723.236364 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 43.341002 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.066911 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4602.822845 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1559.466000 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1130.344513 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.532424 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002645 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.280934 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.095182 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.068991 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.980181 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1044 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 15 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15177 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 13 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 332 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 429 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 270 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 285 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4113 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7946 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2792 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.063477 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.927551 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 55342545 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 55342545 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 81587 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3892 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1894938 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 403004 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 2383421 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 515632 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 515632 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28611 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 28611 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1830 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 1830 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 223241 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 223241 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 81587 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3892 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1894938 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 626245 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 2606662 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 81587 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3892 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1894938 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 626245 # number of overall hits -system.cpu0.l2cache.overall_hits::total 2606662 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 835 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 121 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 70956 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 100469 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 172381 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26947 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 26947 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18435 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 18435 # number of SCUpgradeReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 45449 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 45449 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 835 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 121 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 70956 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 145918 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 217830 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 835 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 121 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 70956 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 145918 # number of overall misses -system.cpu0.l2cache.overall_misses::total 217830 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 28533998 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2724498 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 3265841724 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 3007886164 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 6304986384 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 501041294 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 501041294 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 372688311 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 372688311 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 123500 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 123500 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2240726575 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 2240726575 # number of ReadExReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 28533998 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2724498 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3265841724 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 5248612739 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 8545712959 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 28533998 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2724498 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3265841724 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 5248612739 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 8545712959 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 82422 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4013 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1965894 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 503473 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 2555802 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 515632 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 515632 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55558 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 55558 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20265 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 20265 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 268690 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 268690 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 82422 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4013 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 1965894 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 772163 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 2824492 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 82422 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4013 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 1965894 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 772163 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 2824492 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.010131 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.030152 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.036094 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.199552 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.067447 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.485025 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.485025 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.909697 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.909697 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.169150 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.169150 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.010131 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.030152 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.036094 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.188973 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.077122 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.010131 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.030152 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.036094 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.188973 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.077122 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 34172.452695 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22516.512397 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 46026.294098 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 29938.450308 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 36575.877759 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18593.583479 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18593.583479 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20216.344508 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20216.344508 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data inf # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 49301.999494 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 49301.999494 # average ReadExReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 34172.452695 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22516.512397 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 46026.294098 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35969.604429 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 39231.111229 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 34172.452695 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22516.512397 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 46026.294098 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35969.604429 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 39231.111229 # average overall miss latency -system.cpu0.l2cache.blocked_cycles::no_mshrs 33 # number of cycles access was blocked +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4328 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7768 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2750 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.063721 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000916 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.926331 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 85339399 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 85339399 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 80048 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4433 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 84481 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 493290 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 493290 # number of Writeback hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28251 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 28251 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1773 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 1773 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 213027 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 213027 # number of ReadExReq hits +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1814336 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadCleanReq_hits::total 1814336 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 376020 # number of ReadSharedReq hits +system.cpu0.l2cache.ReadSharedReq_hits::total 376020 # number of ReadSharedReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 80048 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4433 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1814336 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 589047 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 2487864 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 80048 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4433 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1814336 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 589047 # number of overall hits +system.cpu0.l2cache.overall_hits::total 2487864 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 723 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 114 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 837 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 27851 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 27851 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19535 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 19535 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 43989 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 43989 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 64257 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 64257 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 101397 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 101397 # number of ReadSharedReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 723 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 114 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 64257 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 145386 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 210480 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 723 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 114 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 64257 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 145386 # number of overall misses +system.cpu0.l2cache.overall_misses::total 210480 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 24794500 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2781500 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 27576000 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 513504000 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 513504000 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 395434500 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 395434500 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 385999 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 385999 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2149567499 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 2149567499 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2872366000 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2872366000 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2916301996 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2916301996 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 24794500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2781500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2872366000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 5065869495 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 7965811495 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 24794500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2781500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2872366000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 5065869495 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 7965811495 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 80771 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4547 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 85318 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 493290 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 493290 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 56102 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 56102 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 21308 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 21308 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 257016 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 257016 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1878593 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::total 1878593 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 477417 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::total 477417 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 80771 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4547 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 1878593 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 734433 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 2698344 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 80771 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4547 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 1878593 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 734433 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 2698344 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.008951 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.025071 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.009810 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.496435 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.496435 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.916792 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.916792 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.171153 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.171153 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.034205 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.034205 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.212387 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.212387 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.008951 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.025071 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.034205 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.197957 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.078003 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.008951 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.025071 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.034205 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.197957 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.078003 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 34293.914246 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24399.122807 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32946.236559 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18437.542638 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18437.542638 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20242.359867 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20242.359867 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 385999 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 385999 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 48866.023301 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 48866.023301 # average ReadExReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 44701.215432 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 44701.215432 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 28761.225638 # average ReadSharedReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 28761.225638 # average ReadSharedReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 34293.914246 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24399.122807 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 44701.215432 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 34844.273142 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 37845.930706 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 34293.914246 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24399.122807 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 44701.215432 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 34844.273142 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 37845.930706 # average overall miss latency +system.cpu0.l2cache.blocked_cycles::no_mshrs 68 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu0.l2cache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 33 # average number of cycles each access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 200378 # number of writebacks -system.cpu0.l2cache.writebacks::total 200378 # number of writebacks -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 74 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 391 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::total 465 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 3005 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 3005 # number of ReadExReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 74 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3396 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 3470 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 74 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3396 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 3470 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 835 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 121 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 70882 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 100078 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 171916 # number of ReadReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 245909 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 245909 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 26947 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 26947 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 18435 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 18435 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 42444 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 42444 # number of ReadExReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 835 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 121 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 70882 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 142522 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 214360 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 835 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 121 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 70882 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 142522 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 245909 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 460269 # number of overall MSHR misses -system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3367 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 20388 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 23755 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 19084 # number of WriteReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 19084 # number of WriteReq MSHR uncacheable -system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3367 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 39472 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 42839 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 23091000 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1937000 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2794111276 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 2333241113 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 5152380389 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 14425244211 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 14425244211 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 543842959 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 543842959 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 270479823 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 270479823 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 97500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 97500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1625124729 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1625124729 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 23091000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1937000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2794111276 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3958365842 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 6777505118 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 23091000 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1937000 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2794111276 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3958365842 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14425244211 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 21202749329 # number of overall MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 282144500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4115441500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4397586000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3115690500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3115690500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 282144500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7231132000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7513276500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.010131 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.030152 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.036056 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.198775 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.067265 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.writebacks::writebacks 196466 # number of writebacks +system.cpu0.l2cache.writebacks::total 196466 # number of writebacks +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 2877 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 2877 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 67 # number of ReadCleanReq MSHR hits +system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 67 # number of ReadCleanReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 395 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 395 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 67 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3272 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 3339 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 67 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3272 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 3339 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 723 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 114 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 837 # number of ReadReq MSHR misses +system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 9399 # number of CleanEvict MSHR misses +system.cpu0.l2cache.CleanEvict_mshr_misses::total 9399 # number of CleanEvict MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 235023 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 235023 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 27851 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 27851 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19535 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19535 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 1 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41112 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 41112 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 64190 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 64190 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 101002 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 101002 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 723 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 114 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 64190 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 142114 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 207141 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 723 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 114 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 64190 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 142114 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 235023 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 442164 # number of overall MSHR misses +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3426 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 18002 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 21428 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 16758 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 16758 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3426 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 34760 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 38186 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 20456500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2097500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 22554000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 14138051507 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 14138051507 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 556929500 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 556929500 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 298503500 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 298503500 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 325999 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 325999 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1579585500 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1579585500 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 2485678500 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2485678500 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2287922496 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2287922496 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 20456500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2097500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2485678500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3867507996 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 6375740496 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 20456500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2097500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2485678500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3867507996 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14138051507 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 20513792003 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 286870500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 3607450000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 3894320500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2599707500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2599707500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 286870500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6207157500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6494028000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.008951 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.025071 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.009810 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.485025 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.485025 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.909697 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.909697 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.157966 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.157966 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.010131 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.030152 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.036056 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.184575 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.075893 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.010131 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.030152 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.036056 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.184575 # mshr miss rate for overall accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.496435 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.496435 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.916792 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.916792 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.159959 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.159959 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.034169 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.034169 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.211559 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.211559 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.008951 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.025071 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.034169 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.193502 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.076766 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.008951 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.025071 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.034169 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.193502 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.162956 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27653.892216 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16008.264463 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 39419.193533 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 23314.226034 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 29970.336612 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58660.903875 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 58660.903875 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20181.948232 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20181.948232 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14672.081530 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14672.081530 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38288.679884 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38288.679884 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27653.892216 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16008.264463 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 39419.193533 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27773.718037 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31617.396520 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27653.892216 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16008.264463 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 39419.193533 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27773.718037 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58660.903875 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46065.994731 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83797.000297 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201856.067294 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 185122.542623 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 163261.920981 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 163261.920981 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83797.000297 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 183196.493717 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 175384.030906 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.163865 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28293.914246 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18399.122807 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26946.236559 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60156.033695 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 60156.033695 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19996.750566 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19996.750566 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15280.445354 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15280.445354 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 325999 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 325999 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38421.519264 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38421.519264 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 38723.765384 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 38723.765384 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 22652.249421 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 22652.249421 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28293.914246 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18399.122807 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 38723.765384 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27214.123844 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30779.712833 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28293.914246 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18399.122807 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 38723.765384 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27214.123844 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60156.033695 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46394.080031 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83733.362522 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200391.623153 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 181739.803061 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 155132.324860 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 155132.324860 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83733.362522 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 178571.849827 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 170063.059760 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 2719039 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 2643816 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 31019 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 19084 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 515632 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 304029 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36259 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 89544 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42988 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 112734 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 6 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 10 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 297842 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 284446 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3938521 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2392407 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11394 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 176554 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 6518876 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 126032640 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86683880 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 16052 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 329688 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 213062260 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 679431 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 4036359 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 1.164506 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.370735 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 136409 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 2524037 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 31171 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 16758 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 866064 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 2177189 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 293784 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 92828 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43742 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 114509 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 19 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 285377 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 271332 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1878593 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 603707 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 5608538 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2465365 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11948 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 171096 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 8256947 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 120449152 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 82718835 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 18188 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 323084 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 203509259 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 1215113 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 6486372 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 1.185022 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.388316 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 3372352 83.55% 83.55% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 664007 16.45% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 5286248 81.50% 81.50% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 1200124 18.50% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 4036359 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 2262112239 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 6486372 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 3193659992 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 115872000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 113350499 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 2959359198 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 2823287977 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1234268849 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1167322846 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 7386992 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 7403495 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 94142746 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 90327994 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 19410315 # Number of BP lookups -system.cpu1.branchPred.condPredicted 6222605 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 754773 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 10046576 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 7244167 # Number of BTB hits +system.cpu1.branchPred.lookups 20515510 # Number of BP lookups +system.cpu1.branchPred.condPredicted 7101066 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 968769 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 10637682 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 7757881 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 72.105830 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 8699318 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 540404 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 72.928303 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 8827818 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 689615 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1258,60 +1292,60 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 26225 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 26225 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19144 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7081 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 26225 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 26225 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 26225 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 2726 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 9368.766324 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 8408.351420 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 5475.622761 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 1046 38.37% 38.37% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1544 56.64% 95.01% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 68 2.49% 97.51% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 59 2.16% 99.67% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-40959 2 0.07% 99.74% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 5 0.18% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::90112-98303 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walks 30617 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 30617 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 22895 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7722 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 30617 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 30617 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 30617 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 2694 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 10773.014105 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 9833.978032 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6170.794386 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 858 31.85% 31.85% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1697 62.99% 94.84% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 63 2.34% 97.18% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 63 2.34% 99.52% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 7 0.26% 99.78% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-57343 1 0.04% 99.81% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::90112-98303 4 0.15% 99.96% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 2726 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 1584726764 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1584726764 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 1584726764 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 2009 73.70% 73.70% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 717 26.30% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2726 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 26225 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkCompletionTime::total 2694 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1565807264 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1565807264 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1565807264 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 2001 74.28% 74.28% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 693 25.72% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2694 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 30617 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 26225 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2726 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 30617 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2694 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2726 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 28951 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2694 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 33311 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 11340769 # DTB read hits -system.cpu1.dtb.read_misses 24844 # DTB read misses -system.cpu1.dtb.write_hits 7074140 # DTB write hits -system.cpu1.dtb.write_misses 1381 # DTB write misses +system.cpu1.dtb.read_hits 12131046 # DTB read hits +system.cpu1.dtb.read_misses 27925 # DTB read misses +system.cpu1.dtb.write_hits 7724726 # DTB write hits +system.cpu1.dtb.write_misses 2692 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu1.dtb.flush_entries 2067 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 202 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 452 # Number of TLB faults due to prefetch +system.cpu1.dtb.align_faults 318 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 531 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 283 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 11365613 # DTB read accesses -system.cpu1.dtb.write_accesses 7075521 # DTB write accesses +system.cpu1.dtb.perms_faults 287 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 12158971 # DTB read accesses +system.cpu1.dtb.write_accesses 7727418 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 18414909 # DTB hits -system.cpu1.dtb.misses 26225 # DTB misses -system.cpu1.dtb.accesses 18441134 # DTB accesses +system.cpu1.dtb.hits 19855772 # DTB hits +system.cpu1.dtb.misses 30617 # DTB misses +system.cpu1.dtb.accesses 19886389 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1341,42 +1375,39 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 2259 # Table walker walks requested -system.cpu1.itb.walker.walksShort 2259 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 181 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2078 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 2259 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 2259 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 2259 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1118 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 9560.375671 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 8643.967571 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 4716.413998 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-4095 181 16.19% 16.19% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 171 15.30% 31.48% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 489 43.74% 75.22% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 245 21.91% 97.14% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 1 0.09% 97.23% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 15 1.34% 98.57% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 14 1.25% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 1 0.09% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.09% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1118 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1584152264 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1584152264 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1584152264 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 950 84.97% 84.97% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 168 15.03% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1118 # Table walker page sizes translated +system.cpu1.itb.walker.walks 2297 # Table walker walks requested +system.cpu1.itb.walker.walksShort 2297 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 182 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2115 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 2297 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 2297 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 2297 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1122 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 10860.516934 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 10080.267537 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5206.907244 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-8191 274 24.42% 24.42% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-16383 814 72.55% 96.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-24575 4 0.36% 97.33% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-32767 27 2.41% 99.73% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-49151 2 0.18% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::90112-98303 1 0.09% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 1122 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1565238764 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1565238764 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1565238764 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 953 84.94% 84.94% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 169 15.06% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1122 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2259 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2259 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2297 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2297 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1118 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1118 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 3377 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 39752348 # ITB inst hits -system.cpu1.itb.inst_misses 2259 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1122 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1122 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 3419 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 41950603 # ITB inst hits +system.cpu1.itb.inst_misses 2297 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1385,130 +1416,130 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1156 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1160 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1892 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1848 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 39754607 # ITB inst accesses -system.cpu1.itb.hits 39752348 # DTB hits -system.cpu1.itb.misses 2259 # DTB misses -system.cpu1.itb.accesses 39754607 # DTB accesses -system.cpu1.numCycles 114648497 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 41952900 # ITB inst accesses +system.cpu1.itb.hits 41950603 # DTB hits +system.cpu1.itb.misses 2297 # DTB misses +system.cpu1.itb.accesses 41952900 # DTB accesses +system.cpu1.numCycles 125141481 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 48281933 # Number of instructions committed -system.cpu1.committedOps 59077199 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 5147990 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 2790 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 5576811814 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.374563 # CPI: cycles per instruction -system.cpu1.ipc 0.421130 # IPC: instructions per cycle +system.cpu1.committedInsts 51908432 # Number of instructions committed +system.cpu1.committedOps 63413187 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 5363692 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 2715 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 5566331294 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.410812 # CPI: cycles per instruction +system.cpu1.ipc 0.414798 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2790 # number of quiesce instructions executed -system.cpu1.tickCycles 97744251 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 16904246 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.replacements 195096 # number of replacements -system.cpu1.dcache.tags.tagsinuse 474.102569 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 17976294 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 195460 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 91.969170 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 90457158500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 474.102569 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.925982 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.925982 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 364 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 314 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 50 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.710938 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 36856215 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 36856215 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 10952474 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 10952474 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 6779584 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 6779584 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50047 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 50047 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 80034 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 80034 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71497 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 71497 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 17732058 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 17732058 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 17782105 # number of overall hits -system.cpu1.dcache.overall_hits::total 17782105 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 158503 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 158503 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 144597 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 144597 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30804 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30804 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16970 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 16970 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23713 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23713 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 303100 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 303100 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 333904 # number of overall misses -system.cpu1.dcache.overall_misses::total 333904 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2370328398 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2370328398 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3872727461 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 3872727461 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 316464239 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 316464239 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 558424163 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 558424163 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 271500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 271500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 6243055859 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 6243055859 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 6243055859 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 6243055859 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 11110977 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 11110977 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 6924181 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 6924181 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80851 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 80851 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97004 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 97004 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95210 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 95210 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 18035158 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 18035158 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 18116009 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 18116009 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.014265 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.014265 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.020883 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.020883 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380997 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380997 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.174941 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.174941 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.249060 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.249060 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.016806 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.016806 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.018431 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.018431 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14954.470250 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14954.470250 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26782.903248 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 26782.903248 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18648.452504 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18648.452504 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23549.283642 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23549.283642 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 2717 # number of quiesce instructions executed +system.cpu1.tickCycles 105428618 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 19712863 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.replacements 231919 # number of replacements +system.cpu1.dcache.tags.tagsinuse 484.812111 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 19337078 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 232252 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 83.259038 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 90437090000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 484.812111 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.946899 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.946899 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 333 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 279 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 54 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.650391 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 39720944 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 39720944 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 11670097 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 11670097 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 7386354 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 7386354 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 66295 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 66295 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 88787 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 88787 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 80732 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 80732 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 19056451 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 19056451 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 19122746 # number of overall hits +system.cpu1.dcache.overall_hits::total 19122746 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 184750 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 184750 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 167503 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 167503 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 35001 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 35001 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17741 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 17741 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23478 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23478 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 352253 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 352253 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 387254 # number of overall misses +system.cpu1.dcache.overall_misses::total 387254 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2719987000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2719987000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4150031500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 4150031500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 326839500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 326839500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 548823500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 548823500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 416500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 416500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 6870018500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 6870018500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 6870018500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 6870018500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 11854847 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 11854847 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 7553857 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 7553857 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 101296 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 101296 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 106528 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 106528 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 104210 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 104210 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 19408704 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 19408704 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 19510000 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 19510000 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.015584 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.015584 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.022174 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.022174 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.345532 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.345532 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.166538 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.166538 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.225295 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.225295 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.018149 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.018149 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.019849 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.019849 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14722.527740 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14722.527740 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24775.863716 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 24775.863716 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18422.834113 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18422.834113 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23376.075475 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23376.075475 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20597.346945 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 20597.346945 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18697.158042 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 18697.158042 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19503.080172 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 19503.080172 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17740.342256 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 17740.342256 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1517,148 +1548,148 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 119832 # number of writebacks -system.cpu1.dcache.writebacks::total 119832 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 16048 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 16048 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 52216 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 52216 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12045 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12045 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 68264 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 68264 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 68264 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 68264 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 142455 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 142455 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 92381 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 92381 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29949 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 29949 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4925 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4925 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23713 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23713 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 234836 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 234836 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 264785 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 264785 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14604 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14604 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11935 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11935 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 26539 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 26539 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1925101376 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1925101376 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2304194019 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2304194019 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 483540014 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 483540014 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 80690501 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 80690501 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 521529337 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 521529337 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 262500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 262500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4229295395 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4229295395 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4712835409 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4712835409 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2321932001 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2321932001 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1843920001 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1843920001 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4165852002 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4165852002 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.012821 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.012821 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013342 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.013342 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.370422 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.370422 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050771 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050771 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.249060 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.249060 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.013021 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.013021 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.014616 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.014616 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13513.750841 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13513.750841 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24942.293534 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24942.293534 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16145.447728 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16145.447728 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16383.858071 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16383.858071 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21993.393371 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21993.393371 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 138789 # number of writebacks +system.cpu1.dcache.writebacks::total 138789 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 18309 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 18309 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 62144 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 62144 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12262 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12262 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 80453 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 80453 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 80453 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 80453 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 166441 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 166441 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105359 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 105359 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 33489 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 33489 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5479 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5479 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23478 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23478 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 271800 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 271800 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 305289 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 305289 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 17142 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 17142 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 14413 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 14413 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 31555 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 31555 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2292018500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2292018500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2517101000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2517101000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 540422500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 540422500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 93861500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 93861500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 525354500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 525354500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 407500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 407500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4809119500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4809119500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5349542000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5349542000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2935336500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2935336500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2447202500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2447202500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 5382539000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 5382539000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014040 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.014040 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013948 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.013948 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.330605 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.330605 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051432 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051432 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.225295 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.225295 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014004 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.014004 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015648 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.015648 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13770.756604 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13770.756604 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23890.707011 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23890.707011 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16137.313745 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16137.313745 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17131.137069 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17131.137069 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22376.458813 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22376.458813 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18009.570062 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18009.570062 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17798.725037 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17798.725037 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 158992.878732 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 158992.878732 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 154496.858065 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 154496.858065 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 156970.948491 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 156970.948491 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17693.596394 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17693.596394 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17522.878322 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17522.878322 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171236.524326 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171236.524326 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169791.334212 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169791.334212 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 170576.422120 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 170576.422120 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 948604 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.330921 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 38801180 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 949116 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 40.881389 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 72079277000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.330921 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975256 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.975256 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 1046573 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.334165 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 40901496 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 1047085 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 39.062250 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 72079197500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.334165 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975262 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.975262 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 467 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 45 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 461 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 51 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 80449708 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 80449708 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 38801180 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 38801180 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 38801180 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 38801180 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 38801180 # number of overall hits -system.cpu1.icache.overall_hits::total 38801180 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 949116 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 949116 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 949116 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 949116 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 949116 # number of overall misses -system.cpu1.icache.overall_misses::total 949116 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8198295158 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8198295158 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8198295158 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8198295158 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8198295158 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8198295158 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 39750296 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 39750296 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 39750296 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 39750296 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 39750296 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 39750296 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023877 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.023877 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023877 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.023877 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023877 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.023877 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8637.822098 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8637.822098 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8637.822098 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8637.822098 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8637.822098 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8637.822098 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 84944247 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 84944247 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 40901496 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 40901496 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 40901496 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 40901496 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 40901496 # number of overall hits +system.cpu1.icache.overall_hits::total 40901496 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 1047085 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 1047085 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 1047085 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 1047085 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 1047085 # number of overall misses +system.cpu1.icache.overall_misses::total 1047085 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 9273780500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 9273780500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 9273780500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 9273780500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 9273780500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 9273780500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 41948581 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 41948581 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 41948581 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 41948581 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 41948581 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 41948581 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024961 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024961 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024961 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024961 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024961 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024961 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8856.759957 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8856.759957 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8856.759957 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8856.759957 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8856.759957 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8856.759957 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1667,423 +1698,451 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 949116 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 949116 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 949116 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 949116 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 949116 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 949116 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable -system.cpu1.icache.ReadReq_mshr_uncacheable::total 112 # number of ReadReq MSHR uncacheable -system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses -system.cpu1.icache.overall_mshr_uncacheable_misses::total 112 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7247841842 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7247841842 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7247841842 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7247841842 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7247841842 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7247841842 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10378250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10378250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10378250 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 10378250 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023877 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023877 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023877 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.023877 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023877 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.023877 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7636.413085 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7636.413085 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7636.413085 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 7636.413085 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7636.413085 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 7636.413085 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92662.946429 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92662.946429 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92662.946429 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92662.946429 # average overall mshr uncacheable latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 1047085 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 1047085 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 1047085 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 1047085 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 1047085 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 1047085 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 113 # number of ReadReq MSHR uncacheable +system.cpu1.icache.ReadReq_mshr_uncacheable::total 113 # number of ReadReq MSHR uncacheable +system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 113 # number of overall MSHR uncacheable misses +system.cpu1.icache.overall_mshr_uncacheable_misses::total 113 # number of overall MSHR uncacheable misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8750238000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 8750238000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8750238000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 8750238000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8750238000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 8750238000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10154500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10154500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10154500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 10154500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024961 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024961 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024961 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024961 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024961 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024961 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8356.759957 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8356.759957 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8356.759957 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8356.759957 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8356.759957 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8356.759957 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 89862.831858 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 89862.831858 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 89862.831858 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 89862.831858 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 197332 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 197391 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 51 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 270311 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 270335 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 21 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 58593 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 54928 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15357.291554 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1177888 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 69820 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 16.870352 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 70297 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 69395 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15632.228782 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 2434679 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 84293 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 28.883525 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 7821.827388 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 38.231580 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.097899 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4362.380441 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2262.649841 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 872.104404 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.477406 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002333 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000006 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.266259 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.138101 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.053229 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.937335 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1066 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 49 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13777 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 657 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 409 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 6105.214353 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 60.591846 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.935526 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 5648.623425 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2320.323151 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1496.540481 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.372633 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003698 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000057 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.344765 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.141621 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.091342 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.954116 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1218 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 62 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13618 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 8 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 684 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 526 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 13 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 18 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 303 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6108 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 7366 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.065063 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002991 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.840881 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 22523169 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 22523169 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 28304 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2558 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 928097 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 105681 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 1064640 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 119832 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 119832 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1525 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 1525 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 984 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 984 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27488 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 27488 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 28304 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2558 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 928097 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 133169 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 1092128 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 28304 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2558 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 928097 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 133169 # number of overall hits -system.cpu1.l2cache.overall_hits::total 1092128 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 652 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 213 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 21019 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 71648 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 93532 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28424 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 28424 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22729 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22729 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34944 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 34944 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 652 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 213 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 21019 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 106592 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 128476 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 652 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 213 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 21019 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 106592 # number of overall misses -system.cpu1.l2cache.overall_misses::total 128476 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 14243728 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4276499 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 737905240 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1619303994 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 2375729461 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 539163396 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 539163396 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 459339096 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 459339096 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 256500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 256500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1382755927 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1382755927 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 14243728 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4276499 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 737905240 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 3002059921 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 3758485388 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 14243728 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4276499 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 737905240 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 3002059921 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 3758485388 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 28956 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2771 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 949116 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 177329 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 1158172 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 119832 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 119832 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29949 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 29949 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23713 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 23713 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 62432 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 62432 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 28956 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2771 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 949116 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 239761 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 1220604 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 28956 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2771 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 949116 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 239761 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 1220604 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.022517 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.076868 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.022146 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.404040 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.080758 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.949080 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.949080 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.958504 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.958504 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.559713 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.559713 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.022517 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.076868 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.022146 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.444576 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.105256 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.022517 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.076868 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.022146 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.444576 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.105256 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21846.208589 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20077.460094 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 35106.581664 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 22600.826178 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 25400.178132 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18968.596820 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18968.596820 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20209.384311 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20209.384311 # average SCUpgradeReq miss latency +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 21 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 28 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 315 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6069 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 7234 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.074341 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003784 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.831177 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 43042452 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 43042452 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 33942 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2703 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 36645 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 138788 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 138788 # number of Writeback hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2017 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 2017 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1035 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 1035 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 37928 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 37928 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 1019439 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 1019439 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 131721 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 131721 # number of ReadSharedReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 33942 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2703 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 1019439 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 169649 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 1225733 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 33942 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2703 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 1019439 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 169649 # number of overall hits +system.cpu1.l2cache.overall_hits::total 1225733 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 703 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 221 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 924 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29293 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 29293 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22443 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 22443 # number of SCUpgradeReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 36124 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 36124 # number of ReadExReq misses +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 27646 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadCleanReq_misses::total 27646 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 73685 # number of ReadSharedReq misses +system.cpu1.l2cache.ReadSharedReq_misses::total 73685 # number of ReadSharedReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 703 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 221 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 27646 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 109809 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 138379 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 703 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 221 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 27646 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 109809 # number of overall misses +system.cpu1.l2cache.overall_misses::total 138379 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 17833500 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4520500 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 22354000 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 553092500 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 553092500 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 450276000 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 450276000 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 393500 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 393500 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1418705500 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 1418705500 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 1071948000 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::total 1071948000 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1752324498 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1752324498 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 17833500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4520500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 1071948000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 3171029998 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 4265331998 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 17833500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4520500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 1071948000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 3171029998 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 4265331998 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 34645 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2924 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 37569 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 138788 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 138788 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 31310 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 31310 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23478 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 23478 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 74052 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 74052 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 1047085 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::total 1047085 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 205406 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::total 205406 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 34645 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2924 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 1047085 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 279458 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 1364112 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 34645 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2924 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 1047085 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 279458 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 1364112 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.020292 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.075581 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.024595 # miss rate for ReadReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.935580 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.935580 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.955916 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.955916 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.487819 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.487819 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.026403 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.026403 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.358729 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.358729 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.020292 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.075581 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026403 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.392936 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.101443 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.020292 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.075581 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026403 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.392936 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.101443 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 25367.709815 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20454.751131 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 24192.640693 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18881.388045 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18881.388045 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20063.093169 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20063.093169 # average SCUpgradeReq miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39570.625200 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39570.625200 # average ReadExReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21846.208589 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20077.460094 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35106.581664 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 28164.026578 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 29254.377378 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21846.208589 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20077.460094 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35106.581664 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 28164.026578 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 29254.377378 # average overall miss latency -system.cpu1.l2cache.blocked_cycles::no_mshrs 106 # number of cycles access was blocked +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39273.211715 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39273.211715 # average ReadExReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 38774.072199 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 38774.072199 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23781.291959 # average ReadSharedReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23781.291959 # average ReadSharedReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 25367.709815 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20454.751131 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 38774.072199 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 28877.687603 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 30823.549802 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 25367.709815 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20454.751131 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 38774.072199 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 28877.687603 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 30823.549802 # average overall miss latency +system.cpu1.l2cache.blocked_cycles::no_mshrs 26 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu1.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 26.500000 # average number of cycles each access was blocked +system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 26 # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 32037 # number of writebacks -system.cpu1.l2cache.writebacks::total 32037 # number of writebacks -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 22 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 90 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::total 112 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 230 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 230 # number of ReadExReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 22 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 320 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 342 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 22 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 320 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 342 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 652 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 213 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 20997 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 71558 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 93420 # number of ReadReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 23227 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 23227 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28424 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28424 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22729 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22729 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34714 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 34714 # number of ReadExReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 652 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 213 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 20997 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 106272 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 128134 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 652 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 213 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 20997 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 106272 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 23227 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 151361 # number of overall MSHR misses -system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 14604 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 14716 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 11935 # number of WriteReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 11935 # number of WriteReq MSHR uncacheable -system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 26539 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 26651 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 9997244 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 2891999 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 599685760 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1151439996 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1764014999 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 924666076 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 924666076 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 453146005 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 453146005 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 343401219 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 343401219 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 217500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 217500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1124328801 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1124328801 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 9997244 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 2891999 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 599685760 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2275768797 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 2888343800 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 9997244 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 2891999 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 599685760 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2275768797 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 924666076 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 3813009876 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9435750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2205092749 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2214528499 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1754280499 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1754280499 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9435750 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3959373248 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3968808998 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.022517 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.076868 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.022123 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.403532 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.080662 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.writebacks::writebacks 36782 # number of writebacks +system.cpu1.l2cache.writebacks::total 36782 # number of writebacks +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 330 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 330 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 21 # number of ReadCleanReq MSHR hits +system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 21 # number of ReadCleanReq MSHR hits +system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 131 # number of ReadSharedReq MSHR hits +system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 131 # number of ReadSharedReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 21 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 461 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 482 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 21 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 461 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 482 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 703 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 221 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 924 # number of ReadReq MSHR misses +system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 3084 # number of CleanEvict MSHR misses +system.cpu1.l2cache.CleanEvict_mshr_misses::total 3084 # number of CleanEvict MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 35155 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 35155 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29293 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29293 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22443 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22443 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 35794 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 35794 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 27625 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 27625 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 73554 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 73554 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 703 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 221 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 27625 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 109348 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 137897 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 703 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 221 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 27625 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 109348 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 35155 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 173052 # number of overall MSHR misses +system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 113 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 17142 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 17255 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 14413 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 14413 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 113 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 31555 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 31668 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 13615500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3194500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 16810000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1287870547 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1287870547 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 501412999 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 501412999 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 348285500 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 348285500 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 339500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 339500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1165172000 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1165172000 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 905573000 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 905573000 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1306537498 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1306537498 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 13615500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3194500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 905573000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2471709498 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 3394092498 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 13615500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3194500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 905573000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2471709498 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1287870547 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 4681963045 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9250500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2798164000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2807414500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 2338978500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 2338978500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9250500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 5137142500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 5146393000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.020292 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.075581 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.024595 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.949080 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.949080 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.958504 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.958504 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.556029 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.556029 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022517 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.076868 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.022123 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.443241 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.104976 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022517 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.076868 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.022123 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.443241 # mshr miss rate for overall accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.935580 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.935580 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.955916 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.955916 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.483363 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.483363 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.026383 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.026383 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.358091 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.358091 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020292 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.075581 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.026383 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.391286 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.101089 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020292 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.075581 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.026383 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.391286 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.124005 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15333.196319 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13577.460094 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 28560.544840 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 16091.003046 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18882.626836 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39809.965816 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 39809.965816 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15942.372819 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15942.372819 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15108.505390 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15108.505390 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.126861 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 19367.709815 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14454.751131 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18192.640693 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36634.064770 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36634.064770 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17117.161062 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17117.161062 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15518.669518 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15518.669518 # average SCUpgradeReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32388.339027 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32388.339027 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15333.196319 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13577.460094 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28560.544840 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21414.566367 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22541.587713 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15333.196319 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13577.460094 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28560.544840 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21414.566367 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39809.965816 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25191.495009 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 84247.767857 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 150992.382156 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 150484.404662 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 146986.216925 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 146986.216925 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 84247.767857 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 149190.747504 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 148917.826648 # average overall mshr uncacheable latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32552.159580 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32552.159580 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32780.923077 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32780.923077 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17762.970036 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17762.970036 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 19367.709815 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14454.751131 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32780.923077 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22604.066814 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24613.243928 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 19367.709815 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14454.751131 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32780.923077 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22604.066814 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36634.064770 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 27055.237992 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 81862.831858 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163234.395053 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162701.506810 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 162282.557413 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162282.557413 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 81862.831858 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 162799.635557 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 162510.831123 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 1571398 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 1216942 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 31019 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 11935 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 119832 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 28997 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36259 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 76686 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42144 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 86299 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 10 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 85106 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 66899 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1898456 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 835008 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7108 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 62262 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2802834 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 60750592 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25843924 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11084 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 115824 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 86721424 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 645948 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1991449 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 1.302505 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.459343 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 81434 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 1353329 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 31171 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 14413 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 511562 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 1270278 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 44724 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 77037 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 43004 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 89317 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 19 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 97290 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 79982 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 1047085 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 561570 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 3121460 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 1041902 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7336 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 72984 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 4243682 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 67020672 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29874703 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11696 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 138580 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 97045651 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 1176077 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 3823827 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 1.296126 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.456547 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 1389026 69.75% 69.75% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 602423 30.25% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 2691491 70.39% 70.39% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 1132336 29.61% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1991449 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 839147473 # Layer occupancy (ticks) -system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 80233998 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 3823827 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 1513117496 # Layer occupancy (ticks) +system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu1.toL2Bus.snoopLayer0.occupancy 87426499 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1424533908 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 1570862868 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 411735495 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 471839695 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 4337999 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 4412000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 33317735 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 38355467 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31003 # Transaction distribution -system.iobus.trans_dist::ReadResp 31003 # Transaction distribution +system.iobus.trans_dist::ReadReq 31014 # Transaction distribution +system.iobus.trans_dist::ReadResp 31014 # Transaction distribution system.iobus.trans_dist::WriteReq 59422 # Transaction distribution -system.iobus.trans_dist::WriteResp 23198 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.iobus.trans_dist::WriteResp 59422 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 846 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -2099,16 +2158,16 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180850 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107912 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72960 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72960 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180872 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 447 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2124,10 +2183,10 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162796 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2483972 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 162794 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321280 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321280 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2484074 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 40091000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) @@ -2138,7 +2197,7 @@ system.iobus.reqLayer3.occupancy 12000 # La system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 504000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -2168,664 +2227,698 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 198974708 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 187550442 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84714000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36789763 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36784000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36433 # number of replacements -system.iocache.tags.tagsinuse 14.479314 # Cycle average of tags in use +system.iocache.tags.replacements 36446 # number of replacements +system.iocache.tags.tagsinuse 14.479147 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36449 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36462 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 270323444000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.479314 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.904957 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.904957 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 270355599000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.479147 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.904947 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.904947 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328203 # Number of tag accesses -system.iocache.tags.data_accesses 328203 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses -system.iocache.ReadReq_misses::total 243 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses -system.iocache.demand_misses::realview.ide 243 # number of demand (read+write) misses -system.iocache.demand_misses::total 243 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 243 # number of overall misses -system.iocache.overall_misses::total 243 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 31377127 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 31377127 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6657460818 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 6657460818 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 31377127 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 31377127 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 31377127 # number of overall miss cycles -system.iocache.overall_miss_latency::total 31377127 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 243 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 243 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 243 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 243 # number of overall (read+write) accesses +system.iocache.tags.tag_accesses 328320 # Number of tag accesses +system.iocache.tags.data_accesses 328320 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 256 # number of ReadReq misses +system.iocache.ReadReq_misses::total 256 # number of ReadReq misses +system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses +system.iocache.demand_misses::realview.ide 256 # number of demand (read+write) misses +system.iocache.demand_misses::total 256 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 256 # number of overall misses +system.iocache.overall_misses::total 256 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 32686877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 32686877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4278417565 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4278417565 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 32686877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 32686877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 32686877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 32686877 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 256 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 256 # number of ReadReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) +system.iocache.demand_accesses::realview.ide 256 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 256 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 256 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 256 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 129123.979424 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 129123.979424 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183785.910391 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 183785.910391 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 129123.979424 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 129123.979424 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 129123.979424 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 129123.979424 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 22685 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 127683.113281 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 127683.113281 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118110.025536 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118110.025536 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 127683.113281 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 127683.113281 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 127683.113281 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 127683.113281 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 21 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3423 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.627228 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 5.250000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 243 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 18676627 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 18676627 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4773786844 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4773786844 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 18676627 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 18676627 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 18676627 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 18676627 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_misses::realview.ide 256 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 256 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::realview.ide 256 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 256 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 256 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 256 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 19886877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 19886877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2467217565 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2467217565 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 19886877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 19886877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 19886877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 19886877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76858.547325 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76858.547325 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131785.193352 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131785.193352 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 76858.547325 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76858.547325 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 76858.547325 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76858.547325 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 77683.113281 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 77683.113281 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68110.025536 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68110.025536 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 77683.113281 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 77683.113281 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 77683.113281 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 77683.113281 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 135621 # number of replacements -system.l2c.tags.tagsinuse 64040.319526 # Cycle average of tags in use -system.l2c.tags.total_refs 379947 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 200130 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 1.898501 # Average number of references to valid blocks. +system.l2c.tags.replacements 135320 # number of replacements +system.l2c.tags.tagsinuse 64080.552826 # Cycle average of tags in use +system.l2c.tags.total_refs 445963 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 199765 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.232438 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 12350.088291 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 68.394364 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030949 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 8481.237345 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2821.026897 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35473.229907 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 8.484833 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2216.311582 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 599.378307 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2022.137051 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.188447 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001044 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.129413 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.043045 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.541279 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000129 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.033818 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.009146 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.030855 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.977178 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 29987 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 56 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 34466 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 143 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 5502 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 24342 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 55 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 307 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 3362 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 30784 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.457565 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.525909 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5285534 # Number of tag accesses -system.l2c.tags.data_accesses 5285534 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 409 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 68 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 48212 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 49449 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 47699 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 127 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 23 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 17668 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 9341 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 5522 # number of ReadReq hits -system.l2c.ReadReq_hits::total 178518 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 232415 # number of Writeback hits -system.l2c.Writeback_hits::total 232415 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 3312 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 786 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 4098 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 163 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 161 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 324 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 4321 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1657 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5978 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 409 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 68 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 48212 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 53770 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 47699 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 127 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 23 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 17668 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 10998 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 5522 # number of demand (read+write) hits -system.l2c.demand_hits::total 184496 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 409 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 68 # number of overall hits -system.l2c.overall_hits::cpu0.inst 48212 # number of overall hits -system.l2c.overall_hits::cpu0.data 53770 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 47699 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 127 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 23 # number of overall hits -system.l2c.overall_hits::cpu1.inst 17668 # number of overall hits -system.l2c.overall_hits::cpu1.data 10998 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 5522 # number of overall hits -system.l2c.overall_hits::total 184496 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 131 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 22670 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 9764 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 132484 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 12 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 3329 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1605 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 6236 # number of ReadReq misses -system.l2c.ReadReq_misses::total 176232 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 9270 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 2936 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 12206 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 679 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1284 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1963 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 11261 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 8349 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 19610 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 131 # number of demand (read+write) misses +system.l2c.tags.occ_blocks::writebacks 12788.353662 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 69.367527 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.034390 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7205.553479 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2096.784928 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 32107.700654 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 26.808299 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.851993 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4024.713832 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1527.951308 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4232.432754 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.195135 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001058 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.109948 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.031994 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.489925 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000409 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000013 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.061412 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.023315 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.064582 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.977792 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 29238 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 72 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 35135 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 119 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 5585 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 23534 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 72 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 319 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 3030 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 31767 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.446136 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.001099 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.536118 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 5845545 # Number of tag accesses +system.l2c.tags.data_accesses 5845545 # Number of data accesses +system.l2c.Writeback_hits::writebacks 233248 # number of Writeback hits +system.l2c.Writeback_hits::total 233248 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 3007 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 942 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 3949 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 254 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 81 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 335 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 4095 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 2177 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 6272 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 343 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 65 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 44646 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 47683 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 46675 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 154 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 31 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 21738 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 11221 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 8044 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 180600 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 343 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 65 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 44646 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 51778 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 46675 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 154 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 31 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 21738 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 13398 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 8044 # number of demand (read+write) hits +system.l2c.demand_hits::total 186872 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 343 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 65 # number of overall hits +system.l2c.overall_hits::cpu0.inst 44646 # number of overall hits +system.l2c.overall_hits::cpu0.data 51778 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 46675 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 154 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 31 # number of overall hits +system.l2c.overall_hits::cpu1.inst 21738 # number of overall hits +system.l2c.overall_hits::cpu1.data 13398 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 8044 # number of overall hits +system.l2c.overall_hits::total 186872 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 8773 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 4095 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 12868 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 811 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1218 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 2029 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 10812 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 8416 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 19228 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 116 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.inst 19540 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 8519 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 129160 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 40 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 5871 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 2660 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 9190 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 175098 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.dtb.walker 116 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 22670 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 21025 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 132484 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 12 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 3329 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 9954 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 6236 # number of demand (read+write) misses -system.l2c.demand_misses::total 195842 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 131 # number of overall misses +system.l2c.demand_misses::cpu0.inst 19540 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 19331 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 129160 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 40 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 5871 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 11076 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 9190 # number of demand (read+write) misses +system.l2c.demand_misses::total 194326 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 116 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 22670 # number of overall misses -system.l2c.overall_misses::cpu0.data 21025 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 132484 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 12 # number of overall misses -system.l2c.overall_misses::cpu1.inst 3329 # number of overall misses -system.l2c.overall_misses::cpu1.data 9954 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 6236 # number of overall misses -system.l2c.overall_misses::total 195842 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 11375500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 82500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 1826895022 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 860956862 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 13678177756 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1020250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 277468755 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 142082250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 821626642 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 17619685537 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 12058658 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 2910410 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 14969068 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1225966 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1472453 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 2698419 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 1034866909 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 686149232 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1721016141 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 11375500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 82500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1826895022 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 1895823771 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 13678177756 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 1020250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 277468755 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 828231482 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 821626642 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 19340701678 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 11375500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 82500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1826895022 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 1895823771 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 13678177756 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 1020250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 277468755 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 828231482 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 821626642 # number of overall miss cycles -system.l2c.overall_miss_latency::total 19340701678 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 540 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 69 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 70882 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 59213 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 180183 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 139 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 23 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 20997 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 10946 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 11758 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 354750 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 232415 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 232415 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 12582 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 3722 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 16304 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 842 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 1445 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2287 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 15582 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 10006 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 25588 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 540 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 69 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 70882 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 74795 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 180183 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 139 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 23 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 20997 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 20952 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11758 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 380338 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 540 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 69 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 70882 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 74795 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 180183 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 139 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 23 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 20997 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 20952 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11758 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 380338 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.242593 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.014493 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.319827 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.164896 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.735275 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.086331 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.158546 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.146629 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.530362 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.496778 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.736767 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.788823 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.748651 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.806413 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.888581 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.858330 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.722693 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.834399 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.766375 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.242593 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.014493 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.319827 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.281102 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.735275 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.086331 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.158546 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.475086 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.530362 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.514916 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.242593 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.014493 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.319827 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.281102 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.735275 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.086331 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.158546 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.475086 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.530362 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.514916 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 86835.877863 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 82500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80586.458844 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 88176.655264 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 103243.997434 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 85020.833333 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 83348.980174 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 88524.766355 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 131755.394804 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 99980.057748 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1300.826106 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 991.284060 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 1226.369654 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1805.546392 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1146.770249 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 1374.640346 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 91898.313560 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82183.403042 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 87762.169352 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 86835.877863 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 82500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 80586.458844 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 90169.977218 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 103243.997434 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 85020.833333 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 83348.980174 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 83205.895318 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 131755.394804 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 98756.659338 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 86835.877863 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 82500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 80586.458844 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 90169.977218 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 103243.997434 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 85020.833333 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 83348.980174 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 83205.895318 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 131755.394804 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 98756.659338 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.overall_misses::cpu0.inst 19540 # number of overall misses +system.l2c.overall_misses::cpu0.data 19331 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 129160 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 40 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu1.inst 5871 # number of overall misses +system.l2c.overall_misses::cpu1.data 11076 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 9190 # number of overall misses +system.l2c.overall_misses::total 194326 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0.data 9401500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 5084500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 14486000 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1177000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1665000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 2842000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 989600500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 687604500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1677205000 # number of ReadExReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 10015500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 303000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1567254000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 747042500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 13330410791 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 3705500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 82500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.inst 483609000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 234711500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 1119629067 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 17496763358 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 10015500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 303000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1567254000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 1736643000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 13330410791 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 3705500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 82500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 483609000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 922316000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1119629067 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 19173968358 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 10015500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 303000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 1567254000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 1736643000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 13330410791 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 3705500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 82500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 483609000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 922316000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1119629067 # number of overall miss cycles +system.l2c.overall_miss_latency::total 19173968358 # number of overall miss cycles +system.l2c.Writeback_accesses::writebacks 233248 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 233248 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 11780 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 5037 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 16817 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 1065 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 1299 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2364 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 14907 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 10593 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 25500 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 459 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 66 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.inst 64186 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 56202 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 175835 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 194 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 32 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.inst 27609 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 13881 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 17234 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 355698 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 459 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 66 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 64186 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 71109 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 175835 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 194 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 32 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 27609 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 24474 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 17234 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 381198 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 459 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 66 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 64186 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 71109 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 175835 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 194 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 32 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 27609 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 24474 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 17234 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 381198 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.744737 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.812984 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.765178 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.761502 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.937644 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.858291 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.725297 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.794487 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.754039 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.252723 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.015152 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.304428 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.151578 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.734552 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.206186 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.031250 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.212648 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.191629 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.533248 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.492266 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.252723 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.015152 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.304428 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.271850 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.734552 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.206186 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.031250 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.212648 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.452562 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.533248 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.509777 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.252723 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.015152 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.304428 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.271850 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.734552 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.206186 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.031250 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.212648 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.452562 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.533248 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.509777 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1071.640260 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1241.636142 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 1125.738265 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1451.294698 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1366.995074 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 1400.689995 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 91527.978172 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81702.055608 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 87227.220720 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 86340.517241 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 303000 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 80207.471853 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 87691.337011 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 103208.507208 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 92637.500000 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 82500 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 82372.508942 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 88237.406015 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 121831.236888 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 99925.546597 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 86340.517241 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 303000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 80207.471853 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 89837.204490 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 103208.507208 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 92637.500000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 82500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 82372.508942 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 83271.578187 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 121831.236888 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 98669.083694 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 86340.517241 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 303000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 80207.471853 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 89837.204490 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 103208.507208 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 92637.500000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 82500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 82372.508942 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 83271.578187 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 121831.236888 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 98669.083694 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 73 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 5 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 14.600000 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 101997 # number of writebacks -system.l2c.writebacks::total 101997 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 2 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits +system.l2c.writebacks::writebacks 103312 # number of writebacks +system.l2c.writebacks::total 103312 # number of writebacks +system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 2 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 4 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits system.l2c.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 2 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 2 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 131 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 22668 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 9764 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 132484 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 12 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 3329 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 1605 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 6236 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 176230 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 9270 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 2936 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 12206 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 679 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1284 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1963 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 11261 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 8349 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 19610 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 131 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 6 # number of overall MSHR hits +system.l2c.CleanEvict_mshr_misses::writebacks 3718 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 3718 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 8773 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 4095 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 12868 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 811 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1218 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 2029 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 10812 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 8416 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 19228 # number of ReadExReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 116 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 19538 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 8519 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 129160 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 40 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 5867 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 2660 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 9190 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 175092 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 116 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 22668 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 21025 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 132484 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 12 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 3329 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 9954 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6236 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 195840 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 131 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 19538 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 19331 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 129160 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 40 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 5867 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 11076 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 9190 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 194320 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 116 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 22668 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 21025 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 132484 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 12 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 3329 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 9954 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6236 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 195840 # number of overall MSHR misses -system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3367 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 20388 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 14601 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 38468 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 19084 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 11935 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 31019 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3367 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 39472 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 26536 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 69487 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 9728000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 70000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 1542775978 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 738824138 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 12045165114 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 870250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 235730745 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 121970250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 745216962 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 15440351437 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 165428726 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 52162926 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 217591652 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 12163677 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 22807281 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 34970958 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 895596591 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 581734768 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1477331359 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 9728000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 70000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 1542775978 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 1634420729 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 12045165114 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 870250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 235730745 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 703705018 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 745216962 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 16917682796 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 9728000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 70000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 1542775978 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 1634420729 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 12045165114 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 870250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 235730745 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 703705018 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 745216962 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 16917682796 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 204708000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3717048000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6862750 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1919952251 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 5848571001 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2762074500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1533074001 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 4295148501 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 204708000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 6479122500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6862750 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3453026252 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 10143719502 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.242593 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.014493 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.319799 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.164896 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735275 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.086331 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.158546 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.146629 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.530362 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.496772 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.736767 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.788823 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.748651 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.806413 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.888581 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.858330 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.722693 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.834399 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.766375 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.242593 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.014493 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.319799 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.281102 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735275 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.086331 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.158546 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.475086 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.530362 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.514910 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.242593 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.014493 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.319799 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.281102 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735275 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.086331 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.158546 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.475086 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.530362 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.514910 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 74259.541985 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 68059.642580 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 75668.182917 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90917.885284 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 72520.833333 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70811.278162 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 75993.925234 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119502.399294 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 87614.772950 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17845.601510 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17766.664169 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17826.614124 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17914.104566 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17762.679907 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17815.057565 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79530.822396 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69677.179063 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 75335.612392 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 74259.541985 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68059.642580 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77737.014459 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90917.885284 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 72520.833333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70811.278162 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70695.702029 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119502.399294 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 86385.226695 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 74259.541985 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68059.642580 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77737.014459 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90917.885284 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 72520.833333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70811.278162 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70695.702029 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119502.399294 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 86385.226695 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60798.336798 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182315.479694 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 61274.553571 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 131494.572358 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 152037.303759 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 144732.472228 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 128451.948136 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 138468.309778 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60798.336798 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 164144.773510 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 61274.553571 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 130126.102352 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 145980.104221 # average overall mshr uncacheable latency +system.l2c.overall_mshr_misses::cpu0.inst 19538 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 19331 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 129160 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 40 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 5867 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 11076 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 9190 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 194320 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3426 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 18002 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 113 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 17138 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 38679 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 16758 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 14413 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 31171 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3426 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 34760 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 113 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 31551 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 69850 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 182968000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 85020001 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 267988001 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 16936500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 25297000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 42233500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 881480500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 603444500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1484925000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 8855500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 293000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1371777500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 661852500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 12038810791 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 3305500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 72500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 424750500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 208111500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1027729067 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 15745558358 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 8855500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 293000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 1371777500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 1543333000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 12038810791 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 3305500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 72500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 424750500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 811556000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1027729067 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 17230483358 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 8855500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 293000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 1371777500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 1543333000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 12038810791 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 3305500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 72500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 424750500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 811556000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1027729067 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 17230483358 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 214924500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3283407500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6877000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2489619500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 5994828500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2314728500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2093956000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 4408684500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 214924500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5598136000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6877000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 4583575500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 10403513000 # number of overall MSHR uncacheable cycles +system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.744737 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.812984 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.765178 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.761502 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.937644 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.858291 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.725297 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.794487 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.754039 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.252723 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.015152 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.304397 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.151578 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.734552 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.206186 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.031250 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.212503 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.191629 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.533248 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.492249 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.252723 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.015152 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.304397 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.271850 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.734552 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.206186 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.031250 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.212503 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.452562 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.533248 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.509761 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.252723 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.015152 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.304397 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.271850 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.734552 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.206186 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.031250 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.212503 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.452562 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.533248 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.509761 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20855.807591 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20761.905006 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20825.924852 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20883.477189 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20769.293924 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20814.933465 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 81527.978172 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71702.055608 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 77227.220720 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 76340.517241 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 293000 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 70210.743167 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77691.337011 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 93208.507208 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 82637.500000 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 72500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 72396.539969 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 78237.406015 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111831.236888 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 89927.343100 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76340.517241 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 293000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 70210.743167 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 79837.204490 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 93208.507208 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 82637.500000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 72500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72396.539969 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73271.578187 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111831.236888 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 88670.663637 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76340.517241 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 293000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 70210.743167 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 79837.204490 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 93208.507208 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 82637.500000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 72500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72396.539969 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73271.578187 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111831.236888 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 88670.663637 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62733.362522 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182391.262082 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60858.407080 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145268.963706 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 154989.231883 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 138126.775272 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 145282.453341 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141435.452825 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62733.362522 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 161051.093211 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60858.407080 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 145275.125986 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 148940.773085 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 214941 # Transaction distribution -system.membus.trans_dist::ReadResp 214941 # Transaction distribution -system.membus.trans_dist::WriteReq 31019 # Transaction distribution -system.membus.trans_dist::WriteResp 31019 # Transaction distribution -system.membus.trans_dist::Writeback 138187 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 76766 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40830 # Transaction distribution -system.membus.trans_dist::UpgradeResp 14310 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 5 # Transaction distribution -system.membus.trans_dist::ReadExReq 39945 # Transaction distribution -system.membus.trans_dist::ReadExResp 19469 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14152 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 662279 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 784385 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108896 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108896 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 893281 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1216 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28304 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19271336 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19463652 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 24099108 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 124366 # Total snoops (count) -system.membus.snoop_fanout::samples 577962 # Request fanout histogram +system.membus.trans_dist::ReadReq 38679 # Transaction distribution +system.membus.trans_dist::ReadResp 214027 # Transaction distribution +system.membus.trans_dist::WriteReq 31171 # Transaction distribution +system.membus.trans_dist::WriteResp 31171 # Transaction distribution +system.membus.trans_dist::Writeback 139502 # Transaction distribution +system.membus.trans_dist::CleanEvict 18408 # Transaction distribution +system.membus.trans_dist::UpgradeReq 78648 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 41625 # Transaction distribution +system.membus.trans_dist::UpgradeResp 15041 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution +system.membus.trans_dist::ReadExReq 39591 # Transaction distribution +system.membus.trans_dist::ReadExResp 19084 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 175348 # Transaction distribution +system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107912 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 42 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14764 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 682494 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 805212 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108922 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108922 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 914134 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1344 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19261796 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 19455462 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 21772582 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 126350 # Total snoops (count) +system.membus.snoop_fanout::samples 599467 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 577962 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 599467 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 577962 # Request fanout histogram -system.membus.reqLayer0.occupancy 91190000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 599467 # Request fanout histogram +system.membus.reqLayer0.occupancy 91393000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 22828 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 24328 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 12300498 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 12942500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1168075116 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1014707988 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1171902830 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1166663343 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 37484237 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64473559 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2858,44 +2951,46 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 516760 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 516745 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 31019 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 31019 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 232415 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36259 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 80723 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 41154 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 121877 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 10 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 51826 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 51826 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1082609 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 339699 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1422308 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34055964 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5608584 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 39664548 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 289563 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 990166 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.036865 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.188429 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 38683 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 520875 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 31171 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 31171 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 372774 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 100063 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 82453 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 41960 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 124413 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 19 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 19 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 51599 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 51599 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 482207 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1095171 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 404182 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1499353 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 32852839 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6925951 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 39778790 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 466118 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 1289558 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.161505 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.367996 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 953664 96.31% 96.31% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 36502 3.69% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 1081288 83.85% 83.85% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 208270 16.15% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 990166 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 786658690 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 1289558 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 856703495 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 342000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 361500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 681591350 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 633166148 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 259907159 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 285761511 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt index 99269b180..4d6593456 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.852793 # Number of seconds simulated -sim_ticks 2852793222500 # Number of ticks simulated -final_tick 2852793222500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.852648 # Number of seconds simulated +sim_ticks 2852648357500 # Number of ticks simulated +final_tick 2852648357500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 170913 # Simulator instruction rate (inst/s) -host_op_rate 206647 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4363431399 # Simulator tick rate (ticks/s) -host_mem_usage 626396 # Number of bytes of host memory used -host_seconds 653.80 # Real time elapsed on the host -sim_insts 111742418 # Number of instructions simulated -sim_ops 135104867 # Number of ops (including micro ops) simulated +host_inst_rate 166579 # Simulator instruction rate (inst/s) +host_op_rate 201414 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4236074446 # Simulator tick rate (ticks/s) +host_mem_usage 625784 # Number of bytes of host memory used +host_seconds 673.42 # Real time elapsed on the host +sim_insts 112177181 # Number of instructions simulated +sim_ops 135636113 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 7552 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 8192 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1671744 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9171756 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1670464 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9187820 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10852140 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1671744 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1671744 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7973376 # Number of bytes written to this memory +system.physmem.bytes_read::total 10867564 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1670464 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1670464 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7983168 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 7990900 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 118 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8000692 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 128 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 26121 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 143830 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 26101 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 144081 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 170086 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 124584 # Number of write requests responded to by this memory +system.physmem.num_reads::total 170327 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 124737 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 128965 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 2647 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 129118 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 2872 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 45 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 586003 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3215009 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 585584 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3220804 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3804040 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 586003 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 586003 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2794937 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3809640 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 585584 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 585584 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2798511 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6143 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2801079 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2794937 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 2647 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2804654 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2798511 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 2872 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 586003 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3221152 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 585584 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3226947 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6605119 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 170086 # Number of read requests accepted -system.physmem.writeReqs 165189 # Number of write requests accepted -system.physmem.readBursts 170086 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 165189 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10878016 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7488 # Total number of bytes read from write queue -system.physmem.bytesWritten 9060544 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10852140 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10309236 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 117 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 23589 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4592 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10719 # Per bank write bursts -system.physmem.perBankRdBursts::1 10428 # Per bank write bursts -system.physmem.perBankRdBursts::2 10712 # Per bank write bursts -system.physmem.perBankRdBursts::3 10613 # Per bank write bursts -system.physmem.perBankRdBursts::4 13554 # Per bank write bursts -system.physmem.perBankRdBursts::5 10863 # Per bank write bursts -system.physmem.perBankRdBursts::6 10988 # Per bank write bursts -system.physmem.perBankRdBursts::7 10936 # Per bank write bursts -system.physmem.perBankRdBursts::8 10331 # Per bank write bursts -system.physmem.perBankRdBursts::9 10532 # Per bank write bursts -system.physmem.perBankRdBursts::10 10066 # Per bank write bursts -system.physmem.perBankRdBursts::11 9201 # Per bank write bursts -system.physmem.perBankRdBursts::12 10334 # Per bank write bursts -system.physmem.perBankRdBursts::13 10898 # Per bank write bursts -system.physmem.perBankRdBursts::14 9868 # Per bank write bursts -system.physmem.perBankRdBursts::15 9926 # Per bank write bursts -system.physmem.perBankWrBursts::0 8834 # Per bank write bursts -system.physmem.perBankWrBursts::1 8868 # Per bank write bursts -system.physmem.perBankWrBursts::2 9254 # Per bank write bursts -system.physmem.perBankWrBursts::3 9172 # Per bank write bursts -system.physmem.perBankWrBursts::4 8841 # Per bank write bursts -system.physmem.perBankWrBursts::5 9153 # Per bank write bursts -system.physmem.perBankWrBursts::6 9171 # Per bank write bursts -system.physmem.perBankWrBursts::7 9059 # Per bank write bursts -system.physmem.perBankWrBursts::8 9082 # Per bank write bursts -system.physmem.perBankWrBursts::9 9087 # Per bank write bursts -system.physmem.perBankWrBursts::10 8650 # Per bank write bursts -system.physmem.perBankWrBursts::11 8253 # Per bank write bursts -system.physmem.perBankWrBursts::12 8834 # Per bank write bursts -system.physmem.perBankWrBursts::13 9086 # Per bank write bursts -system.physmem.perBankWrBursts::14 8043 # Per bank write bursts -system.physmem.perBankWrBursts::15 8184 # Per bank write bursts +system.physmem.bw_total::total 6614294 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 170327 # Number of read requests accepted +system.physmem.writeReqs 129118 # Number of write requests accepted +system.physmem.readBursts 170327 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 129118 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10891072 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9856 # Total number of bytes read from write queue +system.physmem.bytesWritten 8012864 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10867564 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8000692 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 154 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 40818 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10912 # Per bank write bursts +system.physmem.perBankRdBursts::1 10835 # Per bank write bursts +system.physmem.perBankRdBursts::2 10722 # Per bank write bursts +system.physmem.perBankRdBursts::3 10734 # Per bank write bursts +system.physmem.perBankRdBursts::4 13360 # Per bank write bursts +system.physmem.perBankRdBursts::5 10814 # Per bank write bursts +system.physmem.perBankRdBursts::6 11148 # Per bank write bursts +system.physmem.perBankRdBursts::7 10988 # Per bank write bursts +system.physmem.perBankRdBursts::8 10136 # Per bank write bursts +system.physmem.perBankRdBursts::9 10280 # Per bank write bursts +system.physmem.perBankRdBursts::10 10233 # Per bank write bursts +system.physmem.perBankRdBursts::11 9195 # Per bank write bursts +system.physmem.perBankRdBursts::12 10314 # Per bank write bursts +system.physmem.perBankRdBursts::13 10738 # Per bank write bursts +system.physmem.perBankRdBursts::14 10036 # Per bank write bursts +system.physmem.perBankRdBursts::15 9728 # Per bank write bursts +system.physmem.perBankWrBursts::0 8115 # Per bank write bursts +system.physmem.perBankWrBursts::1 8199 # Per bank write bursts +system.physmem.perBankWrBursts::2 8378 # Per bank write bursts +system.physmem.perBankWrBursts::3 8308 # Per bank write bursts +system.physmem.perBankWrBursts::4 7548 # Per bank write bursts +system.physmem.perBankWrBursts::5 7862 # Per bank write bursts +system.physmem.perBankWrBursts::6 8189 # Per bank write bursts +system.physmem.perBankWrBursts::7 8102 # Per bank write bursts +system.physmem.perBankWrBursts::8 7754 # Per bank write bursts +system.physmem.perBankWrBursts::9 7814 # Per bank write bursts +system.physmem.perBankWrBursts::10 7662 # Per bank write bursts +system.physmem.perBankWrBursts::11 7060 # Per bank write bursts +system.physmem.perBankWrBursts::12 7768 # Per bank write bursts +system.physmem.perBankWrBursts::13 7969 # Per bank write bursts +system.physmem.perBankWrBursts::14 7379 # Per bank write bursts +system.physmem.perBankWrBursts::15 7094 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 57 # Number of times write queue was full causing retry -system.physmem.totGap 2852792816500 # Total gap between requests +system.physmem.numWrRetry 5 # Number of times write queue was full causing retry +system.physmem.totGap 2852647955000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 543 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 169529 # Read request sizes (log2) +system.physmem.readPktSize::6 169770 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 160808 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 162438 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7239 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 280 # What read queue length does an incoming req see +system.physmem.writePktSize::6 124737 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 163101 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 6778 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 282 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -159,190 +159,187 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1512 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1780 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5363 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5964 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5965 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6462 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6631 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8774 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7460 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1027 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1399 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2382 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2359 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1582 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1683 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 683 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 415 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 161 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 61793 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 322.665933 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 189.077551 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 338.586947 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22269 36.04% 36.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14610 23.64% 59.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6509 10.53% 70.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3452 5.59% 75.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2793 4.52% 80.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1471 2.38% 82.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1217 1.97% 84.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1102 1.78% 86.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8370 13.55% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 61793 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5884 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.884772 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 583.981749 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5883 99.98% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5884 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5884 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 24.060333 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.369950 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 43.410965 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 5554 94.39% 94.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 88 1.50% 95.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 18 0.31% 96.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 15 0.25% 96.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 30 0.51% 96.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 27 0.46% 97.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 26 0.44% 97.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 9 0.15% 98.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 10 0.17% 98.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 1 0.02% 98.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 18 0.31% 98.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 12 0.20% 98.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 8 0.14% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 5 0.08% 98.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 2 0.03% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 3 0.05% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 2 0.03% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 6 0.10% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 6 0.10% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 3 0.05% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 3 0.05% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 16 0.27% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 3 0.05% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::400-415 2 0.03% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::432-447 2 0.03% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::464-479 1 0.02% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 2 0.03% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 1 0.02% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 3 0.05% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 2 0.03% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 2 0.03% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::560-575 3 0.05% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::576-591 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5884 # Writes before turning the bus around for reads -system.physmem.totQLat 1705654500 # Total ticks spent queuing -system.physmem.totMemAccLat 4892573250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 849845000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10035.09 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 1946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2321 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6468 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6808 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6552 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6597 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6601 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8563 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7445 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6625 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6590 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6530 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 257 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 19 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 60792 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 310.959863 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 183.660922 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.542835 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22288 36.66% 36.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14645 24.09% 60.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6538 10.75% 71.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3485 5.73% 77.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2623 4.31% 81.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1593 2.62% 84.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1118 1.84% 86.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1065 1.75% 87.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7437 12.23% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 60792 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6289 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.056766 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 539.634570 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6287 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6289 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6289 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.907934 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.344478 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.522535 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5503 87.50% 87.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 53 0.84% 88.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 178 2.83% 91.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 46 0.73% 91.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 61 0.97% 92.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 176 2.80% 95.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 19 0.30% 95.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 6 0.10% 96.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 12 0.19% 96.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 10 0.16% 96.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 8 0.13% 96.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 5 0.08% 96.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 165 2.62% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 4 0.06% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 2 0.03% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 5 0.08% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 4 0.06% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.02% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.03% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.02% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.03% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 17 0.27% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 3 0.05% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6289 # Writes before turning the bus around for reads +system.physmem.totQLat 1698489250 # Total ticks spent queuing +system.physmem.totMemAccLat 4889233000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 850865000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9980.96 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28785.09 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.81 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.18 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.80 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.61 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28730.96 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.82 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.81 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.81 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.80 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.27 # Average write queue length when enqueuing -system.physmem.readRowHits 140294 # Number of row buffer hits during reads -system.physmem.writeRowHits 109452 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.54 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.30 # Row buffer hit rate for writes -system.physmem.avgGap 8508814.60 # Average gap between requests -system.physmem.pageHitRate 80.16 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 242736480 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 132445500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 692741400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 468840960 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 186330281280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 83545935120 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1638387378750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1909800359490 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.450312 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2725465336224 # Time in different power states -system.physmem_0.memoryStateTime::REF 95260880000 # Time in different power states +system.physmem.avgWrQLen 24.43 # Average write queue length when enqueuing +system.physmem.readRowHits 140383 # Number of row buffer hits during reads +system.physmem.writeRowHits 94198 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.49 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.22 # Row buffer hit rate for writes +system.physmem.avgGap 9526450.45 # Average gap between requests +system.physmem.pageHitRate 79.41 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 240748200 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 131360625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 698201400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 419262480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 186320618640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 83613121875 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1638239679750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1909662992970 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.436876 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2725220726500 # Time in different power states +system.physmem_0.memoryStateTime::REF 95255940000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 32062608776 # Time in different power states +system.physmem_0.memoryStateTime::ACT 32164219750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 224418600 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 122450625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 633009000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 448539120 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 186330281280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 82219424850 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1639550984250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1909529107725 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.355229 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2727414398224 # Time in different power states -system.physmem_1.memoryStateTime::REF 95260880000 # Time in different power states +system.physmem_1.actEnergy 218839320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 119406375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 629140200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 392040000 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 186320618640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 82051531065 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1639609496250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1909341071850 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.324025 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2727521283250 # Time in different power states +system.physmem_1.memoryStateTime::REF 95255940000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30117847276 # Time in different power states +system.physmem_1.memoryStateTime::ACT 29871038250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.bytes_read::cpu.inst 448 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 448 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 7 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 157 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 157 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 157 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 157 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 157 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 157 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_read::cpu.inst 512 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 512 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 512 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 512 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 179 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 179 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 179 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 179 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 179 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 179 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 31001883 # Number of BP lookups -system.cpu.branchPred.condPredicted 16796453 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2502337 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 18460820 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13284720 # Number of BTB hits +system.cpu.branchPred.lookups 31035995 # Number of BP lookups +system.cpu.branchPred.condPredicted 16848460 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2529330 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18616538 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13364370 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 71.961701 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7904518 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1496209 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 71.787622 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7827743 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1524480 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -373,58 +370,56 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 66819 # Table walker walks requested -system.cpu.dtb.walker.walksShort 66819 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43911 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22908 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 66819 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 66819 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 66819 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 7827 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 11026.574677 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 8748.919938 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 7443.454079 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-16383 6102 77.96% 77.96% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::16384-32767 1719 21.96% 99.92% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::32768-49151 1 0.01% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::81920-98303 3 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walks 66851 # Table walker walks requested +system.cpu.dtb.walker.walksShort 66851 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 44044 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22807 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 66851 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 66851 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 66851 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 7848 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 11969.673802 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 9947.704899 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 7432.490287 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-16383 6134 78.16% 78.16% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::16384-32767 1708 21.76% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::81920-98303 5 0.06% 99.99% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 7827 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 262515000 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 262515000 100.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 262515000 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6438 82.25% 82.25% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1389 17.75% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7827 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 66819 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkCompletionTime::total 7848 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 260813000 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 260813000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 260813000 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6448 82.16% 82.16% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1400 17.84% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7848 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 66851 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 66819 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7827 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 66851 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7848 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7827 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 74646 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7848 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 74699 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24698795 # DTB read hits -system.cpu.dtb.read_misses 59886 # DTB read misses -system.cpu.dtb.write_hits 19408206 # DTB write hits -system.cpu.dtb.write_misses 6933 # DTB write misses +system.cpu.dtb.read_hits 24795366 # DTB read hits +system.cpu.dtb.read_misses 59924 # DTB read misses +system.cpu.dtb.write_hits 19459513 # DTB write hits +system.cpu.dtb.write_misses 6927 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4360 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1246 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1786 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4353 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 1315 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 1793 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 745 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24758681 # DTB read accesses -system.cpu.dtb.write_accesses 19415139 # DTB write accesses +system.cpu.dtb.perms_faults 738 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 24855290 # DTB read accesses +system.cpu.dtb.write_accesses 19466440 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44107001 # DTB hits -system.cpu.dtb.misses 66819 # DTB misses -system.cpu.dtb.accesses 44173820 # DTB accesses +system.cpu.dtb.hits 44254879 # DTB hits +system.cpu.dtb.misses 66851 # DTB misses +system.cpu.dtb.accesses 44321730 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -454,37 +449,37 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 5459 # Table walker walks requested -system.cpu.itb.walker.walksShort 5459 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 321 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksShortTerminationLevel::Level2 5138 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 5459 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 5459 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 5459 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 3190 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 11236.050157 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 8968.317634 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7059.322929 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-8191 1291 40.47% 40.47% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::8192-16383 1179 36.96% 77.43% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-24575 719 22.54% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walks 5476 # Table walker walks requested +system.cpu.itb.walker.walksShort 5476 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 320 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 5156 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 5476 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 5476 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 5476 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3185 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 12111.930926 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 10073.036735 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7077.069157 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-8191 1309 41.10% 41.10% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::8192-16383 1163 36.51% 77.61% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-24575 712 22.35% 99.97% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 3190 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 262109500 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 262109500 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 262109500 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 2880 90.28% 90.28% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 310 9.72% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3190 # Table walker page sizes translated +system.cpu.itb.walker.walkCompletionTime::total 3185 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 260408500 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 260408500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 260408500 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 2875 90.27% 90.27% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 310 9.73% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3185 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5459 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 5459 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5476 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 5476 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3190 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3190 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 8649 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 57544146 # ITB inst hits -system.cpu.itb.inst_misses 5459 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3185 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3185 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 8661 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 57644793 # ITB inst hits +system.cpu.itb.inst_misses 5476 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -493,274 +488,274 @@ system.cpu.itb.flush_tlb 64 # Nu system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2978 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2975 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 8374 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 8375 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 57549605 # ITB inst accesses -system.cpu.itb.hits 57544146 # DTB hits -system.cpu.itb.misses 5459 # DTB misses -system.cpu.itb.accesses 57549605 # DTB accesses -system.cpu.numCycles 315425036 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 57650269 # ITB inst accesses +system.cpu.itb.hits 57644793 # DTB hits +system.cpu.itb.misses 5476 # DTB misses +system.cpu.itb.accesses 57650269 # DTB accesses +system.cpu.numCycles 315472495 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 111742418 # Number of instructions committed -system.cpu.committedOps 135104867 # Number of ops (including micro ops) committed -system.cpu.discardedOps 7746377 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 3035 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 5390221882 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.822787 # CPI: cycles per instruction -system.cpu.ipc 0.354260 # IPC: instructions per cycle +system.cpu.committedInsts 112177181 # Number of instructions committed +system.cpu.committedOps 135636113 # Number of ops (including micro ops) committed +system.cpu.discardedOps 7815514 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 3033 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 5389884731 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.812270 # CPI: cycles per instruction +system.cpu.ipc 0.355585 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3035 # number of quiesce instructions executed -system.cpu.tickCycles 227203186 # Number of cycles that the object actually ticked -system.cpu.idleCycles 88221850 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 843958 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.947848 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42509637 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 844470 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 50.338836 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 313221250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.947848 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999898 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999898 # Average percentage of cache occupancy +system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed +system.cpu.tickCycles 227521960 # Number of cycles that the object actually ticked +system.cpu.idleCycles 87950535 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 843739 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.948229 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42652951 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 844251 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 50.521647 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 310642500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.948229 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999899 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999899 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 352 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 356 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 53 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 175807461 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 175807461 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23001062 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23001062 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18245677 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18245677 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 356392 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 356392 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 443406 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 443406 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460170 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460170 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41246739 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41246739 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41603131 # number of overall hits -system.cpu.dcache.overall_hits::total 41603131 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 493519 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 493519 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 547788 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 547788 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 170140 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 170140 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22585 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22585 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 176384491 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 176384491 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23097762 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23097762 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18292469 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18292469 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 356103 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 356103 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 443541 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 443541 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460142 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460142 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 41390231 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41390231 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 41746334 # number of overall hits +system.cpu.dcache.overall_hits::total 41746334 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 493938 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 493938 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 548534 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 548534 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 170153 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 170153 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22409 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22409 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 1041307 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1041307 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1211447 # number of overall misses -system.cpu.dcache.overall_misses::total 1211447 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7303521091 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7303521091 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 23397429282 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 23397429282 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 285183750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 285183750 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 167000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 167000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 30700950373 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 30700950373 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 30700950373 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 30700950373 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23494581 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23494581 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 18793465 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 18793465 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 526532 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 526532 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465991 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 465991 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460172 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460172 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42288046 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42288046 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42814578 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42814578 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021006 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.021006 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029148 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.029148 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.323133 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.323133 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048467 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048467 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_misses::cpu.data 1042472 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1042472 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1212625 # number of overall misses +system.cpu.dcache.overall_misses::total 1212625 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7285426000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7285426000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 23290524980 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 23290524980 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 282897500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 282897500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 165500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 165500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 30575950980 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 30575950980 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 30575950980 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 30575950980 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23591700 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23591700 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 18841003 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 18841003 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 526256 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 526256 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465950 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 465950 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460144 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460144 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 42432703 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42432703 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42958959 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42958959 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020937 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.020937 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029114 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.029114 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.323327 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.323327 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048093 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048093 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.024624 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.024624 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.028295 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.028295 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14798.865071 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14798.865071 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42712.562674 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42712.562674 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12627.130839 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12627.130839 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83500 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83500 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 29483.092280 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29483.092280 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 25342.380123 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 25342.380123 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 238 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.024568 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.024568 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.028228 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.028228 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14749.677085 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14749.677085 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42459.583143 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42459.583143 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12624.280423 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12624.280423 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82750 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82750 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 29330.237148 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29330.237148 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25214.679707 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25214.679707 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 276 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 20 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 22 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.900000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.545455 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 699616 # number of writebacks -system.cpu.dcache.writebacks::total 699616 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 75147 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 75147 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 249007 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 249007 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14321 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 14321 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 324154 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 324154 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 324154 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 324154 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 418372 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 418372 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298781 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 298781 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 121907 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 121907 # number of SoftPFReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8264 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 8264 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 699258 # number of writebacks +system.cpu.dcache.writebacks::total 699258 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 75585 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 75585 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 249712 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 249712 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14175 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 14175 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 325297 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 325297 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 325297 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 325297 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 418353 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 418353 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298822 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 298822 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 121703 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 121703 # number of SoftPFReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8234 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 8234 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 717153 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 717153 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 839060 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 839060 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 717175 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 717175 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 838878 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 838878 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31128 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 31128 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27583 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 27583 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 58711 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5719215890 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5719215890 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12311488911 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12311488911 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1563028750 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1563028750 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 105928000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 105928000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 164000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 164000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18030704801 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 18030704801 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19593733551 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 19593733551 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5833996750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5833996750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4510200000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4510200000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10344196750 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 10344196750 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017807 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017807 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015898 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015898 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.231528 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.231528 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017734 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017734 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5919321500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5919321500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12456778000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12456778000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1615525000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1615525000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 109204500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 109204500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 163500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 163500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18376099500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 18376099500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19991624500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 19991624500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5909109000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5909109000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4568792500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4568792500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10477901500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10477901500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017733 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017733 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015860 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015860 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.231262 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.231262 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017671 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017671 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016959 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016959 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019598 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.019598 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13670.168869 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13670.168869 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41205.728982 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41205.728982 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12821.484820 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12821.484820 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12818.005808 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12818.005808 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25142.061458 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25142.061458 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23352.005281 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23352.005281 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 187419.582048 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 187419.582048 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 163513.758474 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163513.758474 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 176188.393146 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 176188.393146 # average overall mshr uncacheable latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016901 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016901 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019527 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019527 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14149.107333 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14149.107333 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41686.281465 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41686.281465 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13274.323558 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13274.323558 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13262.630556 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13262.630556 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81750 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81750 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25622.894691 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25622.894691 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23831.384897 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23831.384897 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189832.594449 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 189832.594449 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 165637.983541 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 165637.983541 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 178465.730442 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 178465.730442 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 2897206 # number of replacements -system.cpu.icache.tags.tagsinuse 511.401811 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 54637656 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 2897718 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18.855408 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 15497791250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.401811 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.998832 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.998832 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 2894405 # number of replacements +system.cpu.icache.tags.tagsinuse 511.404377 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 54741020 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 2894917 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18.909357 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 15461690500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.404377 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.998837 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.998837 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 197 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 60433115 # Number of tag accesses -system.cpu.icache.tags.data_accesses 60433115 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 54637656 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 54637656 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 54637656 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 54637656 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 54637656 # number of overall hits -system.cpu.icache.overall_hits::total 54637656 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 2897730 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 2897730 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 2897730 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 2897730 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 2897730 # number of overall misses -system.cpu.icache.overall_misses::total 2897730 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 39295051229 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 39295051229 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 39295051229 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 39295051229 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 39295051229 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 39295051229 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 57535386 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 57535386 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 57535386 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 57535386 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 57535386 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 57535386 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050364 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.050364 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.050364 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.050364 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.050364 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.050364 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13560.632367 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13560.632367 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13560.632367 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13560.632367 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13560.632367 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13560.632367 # average overall miss latency +system.cpu.icache.tags.tag_accesses 60530877 # Number of tag accesses +system.cpu.icache.tags.data_accesses 60530877 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 54741020 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 54741020 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 54741020 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 54741020 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 54741020 # number of overall hits +system.cpu.icache.overall_hits::total 54741020 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 2894929 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 2894929 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 2894929 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 2894929 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 2894929 # number of overall misses +system.cpu.icache.overall_misses::total 2894929 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 39235778500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 39235778500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 39235778500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 39235778500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 39235778500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 39235778500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 57635949 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 57635949 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 57635949 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 57635949 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 57635949 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 57635949 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050228 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.050228 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.050228 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.050228 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.050228 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.050228 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13553.278336 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13553.278336 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13553.278336 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13553.278336 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13553.278336 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13553.278336 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -769,200 +764,212 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2897730 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 2897730 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 2897730 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 2897730 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 2897730 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 2897730 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3172 # number of ReadReq MSHR uncacheable -system.cpu.icache.ReadReq_mshr_uncacheable::total 3172 # number of ReadReq MSHR uncacheable -system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3172 # number of overall MSHR uncacheable misses -system.cpu.icache.overall_mshr_uncacheable_misses::total 3172 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 34939012271 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 34939012271 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 34939012271 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 34939012271 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 34939012271 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 34939012271 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 247386750 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 247386750 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 247386750 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 247386750 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050364 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050364 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050364 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.050364 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050364 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.050364 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12057.373279 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12057.373279 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12057.373279 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12057.373279 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12057.373279 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12057.373279 # average overall mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 77990.778689 # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 77990.778689 # average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 77990.778689 # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 77990.778689 # average overall mshr uncacheable latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2894929 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 2894929 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 2894929 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 2894929 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 2894929 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 2894929 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3191 # number of ReadReq MSHR uncacheable +system.cpu.icache.ReadReq_mshr_uncacheable::total 3191 # number of ReadReq MSHR uncacheable +system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3191 # number of overall MSHR uncacheable misses +system.cpu.icache.overall_mshr_uncacheable_misses::total 3191 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36340850500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 36340850500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36340850500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 36340850500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36340850500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 36340850500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 248718500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 248718500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 248718500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 248718500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050228 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050228 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050228 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.050228 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050228 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.050228 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12553.278681 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12553.278681 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12553.278681 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12553.278681 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12553.278681 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12553.278681 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 77943.748041 # average ReadReq mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 77943.748041 # average ReadReq mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 77943.748041 # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 77943.748041 # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 96812 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65065.452586 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4048611 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 162072 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 24.980324 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 97027 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65057.378732 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 7025854 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 162288 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 43.292505 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 47495.130648 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 59.738238 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.009476 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 12201.333788 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 5309.240435 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.724718 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000912 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 47465.165488 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 71.060465 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.009465 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 12271.489149 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 5249.654166 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.724261 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.001084 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.186178 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.081013 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.992820 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 46 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65214 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 46 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2294 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6948 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55853 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000702 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995087 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 36624702 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 36624702 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 71053 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4456 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 2874723 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 534200 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 3484432 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 699616 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 699616 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 54 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 54 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 164782 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 164782 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 71053 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 4456 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 2874723 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 698982 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 3649214 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 71053 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 4456 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 2874723 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 698982 # number of overall hits -system.cpu.l2cache.overall_hits::total 3649214 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 118 # number of ReadReq misses +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.187248 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.080103 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.992697 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 65 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65196 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 65 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 93 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2298 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6933 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55841 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000992 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994812 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 60441725 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 60441725 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 70902 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4431 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 75333 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 699258 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 699258 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 51 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 51 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 164486 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 164486 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2871960 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 2871960 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 534033 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 534033 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 70902 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 4431 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 2871960 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 698519 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 3645812 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 70902 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 4431 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 2871960 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 698519 # number of overall hits +system.cpu.l2cache.overall_hits::total 3645812 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 128 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 22979 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 14338 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 37437 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2773 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2773 # number of UpgradeReq misses +system.cpu.l2cache.ReadReq_misses::total 130 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2782 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2782 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 131177 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 131177 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 118 # number of demand (read+write) misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 131508 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 131508 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 22945 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 22945 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 14252 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 14252 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 128 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 22979 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 145515 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 168614 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 118 # number of overall misses +system.cpu.l2cache.demand_misses::cpu.inst 22945 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 145760 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 168835 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 128 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 22979 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 145515 # number of overall misses -system.cpu.l2cache.overall_misses::total 168614 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 10044750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 179750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1842559750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1204180000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 3056964250 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1091465 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 1091465 # number of UpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 162000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::total 162000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10184869681 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 10184869681 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 10044750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 179750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1842559750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 11389049681 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 13241833931 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 10044750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 179750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1842559750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 11389049681 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 13241833931 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 71171 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4458 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 2897702 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 548538 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 3521869 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 699616 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 699616 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2827 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2827 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.inst 22945 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 145760 # number of overall misses +system.cpu.l2cache.overall_misses::total 168835 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 11086500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 371000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 11457500 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1074500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 1074500 # number of UpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 160500 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::total 160500 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10184937000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 10184937000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1831389500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 1831389500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1184928500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 1184928500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 11086500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 371000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1831389500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11369865500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 13212712500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 11086500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 371000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1831389500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11369865500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 13212712500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 71030 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4433 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 75463 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 699258 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 699258 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2833 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2833 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 295959 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 295959 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 71171 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 4458 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 2897702 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 844497 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 3817828 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 71171 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 4458 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 2897702 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 844497 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 3817828 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001658 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000449 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.007930 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026139 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.010630 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.980898 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.980898 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 295994 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 295994 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 2894905 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 2894905 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 548285 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 548285 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 71030 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 4433 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 2894905 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 844279 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 3814647 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 71030 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 4433 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 2894905 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 844279 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 3814647 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001802 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000451 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.001723 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.981998 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.981998 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.443227 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.443227 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001658 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000449 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.007930 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.172310 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.044165 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001658 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000449 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.007930 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.172310 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.044165 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 85125 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 89875 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80184.505418 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83985.214116 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 81656.229132 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 393.604400 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 393.604400 # average UpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 81000 # average SCUpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 81000 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77642.190940 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77642.190940 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 85125 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 89875 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80184.505418 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78267.186757 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 78533.419117 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 85125 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 89875 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80184.505418 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78267.186757 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 78533.419117 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.444293 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.444293 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.007926 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.007926 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.025994 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.025994 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001802 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000451 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.007926 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.172644 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.044260 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001802 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000451 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.007926 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.172644 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.044260 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 86613.281250 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 185500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 88134.615385 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 386.232926 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 386.232926 # average UpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 80250 # average SCUpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 80250 # average SCUpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77447.280774 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77447.280774 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79816.495969 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79816.495969 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83141.208251 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83141.208251 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 86613.281250 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 185500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79816.495969 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78004.016877 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78258.136642 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 86613.281250 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 185500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79816.495969 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78004.016877 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78258.136642 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -971,176 +978,187 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 88394 # number of writebacks -system.cpu.l2cache.writebacks::total 88394 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 20 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 140 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 160 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 20 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 140 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 160 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 20 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 140 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 160 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 118 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 88547 # number of writebacks +system.cpu.l2cache.writebacks::total 88547 # number of writebacks +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 24 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 24 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 141 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 141 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 24 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 141 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 165 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 24 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 141 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 165 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 128 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 22959 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 14198 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 37277 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2773 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2773 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 130 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2782 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2782 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131177 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 131177 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 118 # number of demand (read+write) MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131508 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 131508 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 22921 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 22921 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 14111 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 14111 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 128 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 22959 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 145375 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 168454 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 118 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 22921 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 145619 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 168670 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 128 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 22959 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 145375 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 168454 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3172 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.overall_mshr_misses::cpu.inst 22921 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 145619 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 168670 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3191 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31128 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34300 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34319 # number of ReadReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27583 # number of WriteReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27583 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3172 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3191 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61883 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 8565250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 154250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1554112000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1016371500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2579203000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 49277273 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 49277273 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 137000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 137000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8543347819 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8543347819 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 8565250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 154250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1554112000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9559719319 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 11122550819 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 8565250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 154250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1554112000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9559719319 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 11122550819 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 191729750 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5397684500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5589414250 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4151492500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4151492500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 191729750 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9549177000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9740906750 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001658 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000449 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.007923 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025883 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.010584 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.980898 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.980898 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61902 # number of overall MSHR uncacheable misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 9806500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 351000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10157500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 57758000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 57758000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 140500 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 140500 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8869857000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8869857000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1601051500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1601051500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1033348500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1033348500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 9806500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 351000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1601051500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9903205500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11514414500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 9806500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 351000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1601051500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9903205500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11514414500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 199170000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5519970000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5719140000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4251529500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4251529500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 199170000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9771499500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9970669500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001802 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000451 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001723 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.981998 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.981998 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.443227 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.443227 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001658 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000449 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007923 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172144 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.044123 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001658 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000449 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007923 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172144 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.044123 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 72586.864407 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 77125 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67690.753082 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71585.540217 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69190.197709 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17770.383339 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17770.383339 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 68500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 68500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65128.397654 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65128.397654 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 72586.864407 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 77125 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67690.753082 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65759.032289 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66027.228911 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72586.864407 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 77125 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67690.753082 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65759.032289 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66027.228911 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 60444.435687 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173402.868800 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162956.683673 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 150509.099808 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150509.099808 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 60444.435687 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162647.153004 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 157408.444161 # average overall mshr uncacheable latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.444293 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.444293 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.007918 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.007918 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.025737 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.025737 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001802 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000451 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007918 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172477 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.044216 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001802 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000451 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007918 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172477 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.044216 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76613.281250 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 175500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 78134.615385 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20761.322789 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20761.322789 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70250 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70250 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67447.280774 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67447.280774 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69850.857292 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69850.857292 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73229.997874 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73229.997874 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76613.281250 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 175500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69850.857292 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68007.646667 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68265.930515 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76613.281250 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 175500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69850.857292 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68007.646667 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68265.930515 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 62416.170479 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 177331.341557 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 166646.464058 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 154135.862669 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 154135.862669 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 62416.170479 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 166433.879512 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 161071.847436 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 3581126 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3581032 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 134609 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3577964 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27583 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27583 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 699616 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36257 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2827 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 824000 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2989342 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2833 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2829 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 295959 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 295959 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5801775 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2511831 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15055 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 160898 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8489559 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185655872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 99015325 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 17832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 284684 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 284973713 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 61355 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4643370 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.029465 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.169105 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 2835 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 295994 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 295994 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 2894929 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 548519 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8639925 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2647968 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15065 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 160688 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 11463646 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185478080 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98978525 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 17732 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 284120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 284758457 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 194907 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 7812293 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.034587 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.182731 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4506555 97.05% 97.05% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 136815 2.95% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 7542089 96.54% 96.54% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 270204 3.46% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4643370 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3016847250 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 211500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 7812293 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4534239000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 213000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 4356806979 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 4347433988 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1344182949 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1312866777 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 10597250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 10632499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 89732000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 89658000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 30183 # Transaction distribution system.iobus.trans_dist::ReadResp 30183 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution -system.iobus.trans_dist::WriteResp 22790 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.iobus.trans_dist::WriteResp 59014 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) @@ -1231,23 +1249,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 198883474 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 187463964 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36810507 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.031423 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.030996 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 270485733000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.031423 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.064464 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.064464 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 270425383000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.030996 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.064437 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.064437 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1255,49 +1273,49 @@ system.iocache.tags.tag_accesses 328122 # Nu system.iocache.tags.data_accesses 328122 # Number of data accesses system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses system.iocache.ReadReq_misses::total 234 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses system.iocache.demand_misses::total 234 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 234 # number of overall misses system.iocache.overall_misses::total 234 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 29239875 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 29239875 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6650280092 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 6650280092 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 29239875 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 29239875 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 29239875 # number of overall miss cycles -system.iocache.overall_miss_latency::total 29239875 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 29161877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 29161877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4271869087 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4271869087 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 29161877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 29161877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 29161877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 29161877 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ide 234 # number of demand (read+write) accesses system.iocache.demand_accesses::total 234 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ide 234 # number of overall (read+write) accesses system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124956.730769 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124956.730769 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183587.679218 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 183587.679218 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124956.730769 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124956.730769 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124956.730769 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124956.730769 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 22674 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 124623.405983 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124623.405983 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 117929.248206 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 117929.248206 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124623.405983 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124623.405983 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124623.405983 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124623.405983 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3485 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.506169 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1305,88 +1323,90 @@ system.iocache.writebacks::writebacks 36190 # nu system.iocache.writebacks::total 36190 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 16928877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 16928877 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4766620104 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4766620104 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 16928877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 16928877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 16928877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 16928877 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 17461877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 17461877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2460669087 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2460669087 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 17461877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 17461877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 17461877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 17461877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72345.628205 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72345.628205 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131587.348277 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131587.348277 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 72345.628205 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72345.628205 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 72345.628205 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72345.628205 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74623.405983 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 74623.405983 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67929.248206 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67929.248206 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 74623.405983 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 74623.405983 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 74623.405983 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 74623.405983 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 71811 # Transaction distribution -system.membus.trans_dist::ReadResp 71811 # Transaction distribution +system.membus.trans_dist::ReadReq 34319 # Transaction distribution +system.membus.trans_dist::ReadResp 71715 # Transaction distribution system.membus.trans_dist::WriteReq 27583 # Transaction distribution system.membus.trans_dist::WriteResp 27583 # Transaction distribution -system.membus.trans_dist::Writeback 124584 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4592 # Transaction distribution +system.membus.trans_dist::Writeback 124737 # Transaction distribution +system.membus.trans_dist::CleanEvict 8493 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4594 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4594 # Transaction distribution -system.membus.trans_dist::ReadExReq 129358 # Transaction distribution -system.membus.trans_dist::ReadExResp 129358 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4596 # Transaction distribution +system.membus.trans_dist::ReadExReq 129696 # Transaction distribution +system.membus.trans_dist::ReadExResp 129696 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 37396 # Transaction distribution +system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446770 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 554330 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108887 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108887 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 663217 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 455889 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 563451 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108900 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108900 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 672351 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 512 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16525920 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16689629 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21325085 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16551136 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16714909 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19032029 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 507 # Total snoops (count) -system.membus.snoop_fanout::samples 394211 # Request fanout histogram +system.membus.snoop_fanout::samples 403270 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 394211 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 403270 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 394211 # Request fanout histogram -system.membus.reqLayer0.occupancy 87591000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 403270 # Request fanout histogram +system.membus.reqLayer0.occupancy 87538000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 8500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1723500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1706000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1025789403 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 881842801 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 997949408 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 999291900 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 37471493 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64464474 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 2dea4306e..d2ddd8522 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.827616 # Number of seconds simulated -sim_ticks 2827616186000 # Number of ticks simulated -final_tick 2827616186000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.827546 # Number of seconds simulated +sim_ticks 2827546300000 # Number of ticks simulated +final_tick 2827546300000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 70271 # Simulator instruction rate (inst/s) -host_op_rate 85238 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1756065639 # Simulator tick rate (ticks/s) -host_mem_usage 621588 # Number of bytes of host memory used -host_seconds 1610.20 # Real time elapsed on the host -sim_insts 113151083 # Number of instructions simulated -sim_ops 137250963 # Number of ops (including micro ops) simulated +host_inst_rate 69908 # Simulator instruction rate (inst/s) +host_op_rate 84797 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1747497470 # Simulator tick rate (ticks/s) +host_mem_usage 626724 # Number of bytes of host memory used +host_seconds 1618.05 # Real time elapsed on the host +sim_insts 113115023 # Number of instructions simulated +sim_ops 137206411 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1325344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9769960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1322768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9763816 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11098056 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1325344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1325344 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8387584 # Number of bytes written to this memory +system.physmem.bytes_read::total 11089336 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1322768 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1322768 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8388544 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8405108 # Number of bytes written to this memory +system.physmem.bytes_written::total 8406068 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 22954 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 153176 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 22916 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 153080 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 176173 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 131056 # Number of write requests responded to by this memory +system.physmem.num_reads::total 176039 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 131071 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 135437 # Number of write requests responded to by this memory +system.physmem.num_writes::total 135452 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 475 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 468714 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3455193 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 467815 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3453106 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3924881 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 468714 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 468714 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2966309 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 6197 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2972507 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2966309 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 3921894 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 467815 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 467815 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2966722 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 6198 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2972920 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2966722 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 475 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 468714 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3461391 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 467815 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3459303 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6897387 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 176174 # Number of read requests accepted -system.physmem.writeReqs 171661 # Number of write requests accepted -system.physmem.readBursts 176174 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 171661 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11266304 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8832 # Total number of bytes read from write queue -system.physmem.bytesWritten 9457344 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11098120 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10723444 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 138 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 23861 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4579 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11334 # Per bank write bursts -system.physmem.perBankRdBursts::1 10890 # Per bank write bursts -system.physmem.perBankRdBursts::2 10732 # Per bank write bursts -system.physmem.perBankRdBursts::3 10393 # Per bank write bursts -system.physmem.perBankRdBursts::4 14045 # Per bank write bursts -system.physmem.perBankRdBursts::5 11531 # Per bank write bursts -system.physmem.perBankRdBursts::6 11498 # Per bank write bursts -system.physmem.perBankRdBursts::7 11674 # Per bank write bursts -system.physmem.perBankRdBursts::8 10645 # Per bank write bursts -system.physmem.perBankRdBursts::9 10993 # Per bank write bursts -system.physmem.perBankRdBursts::10 10307 # Per bank write bursts -system.physmem.perBankRdBursts::11 9597 # Per bank write bursts -system.physmem.perBankRdBursts::12 9956 # Per bank write bursts -system.physmem.perBankRdBursts::13 10908 # Per bank write bursts -system.physmem.perBankRdBursts::14 10689 # Per bank write bursts -system.physmem.perBankRdBursts::15 10844 # Per bank write bursts -system.physmem.perBankWrBursts::0 9257 # Per bank write bursts -system.physmem.perBankWrBursts::1 9346 # Per bank write bursts -system.physmem.perBankWrBursts::2 9336 # Per bank write bursts -system.physmem.perBankWrBursts::3 8962 # Per bank write bursts -system.physmem.perBankWrBursts::4 9705 # Per bank write bursts -system.physmem.perBankWrBursts::5 9746 # Per bank write bursts -system.physmem.perBankWrBursts::6 9125 # Per bank write bursts -system.physmem.perBankWrBursts::7 9630 # Per bank write bursts -system.physmem.perBankWrBursts::8 9307 # Per bank write bursts -system.physmem.perBankWrBursts::9 9634 # Per bank write bursts -system.physmem.perBankWrBursts::10 8942 # Per bank write bursts -system.physmem.perBankWrBursts::11 8449 # Per bank write bursts -system.physmem.perBankWrBursts::12 8881 # Per bank write bursts -system.physmem.perBankWrBursts::13 9361 # Per bank write bursts -system.physmem.perBankWrBursts::14 9018 # Per bank write bursts -system.physmem.perBankWrBursts::15 9072 # Per bank write bursts +system.physmem.bw_total::total 6894813 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 176040 # Number of read requests accepted +system.physmem.writeReqs 135452 # Number of write requests accepted +system.physmem.readBursts 176040 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 135452 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11255936 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 10624 # Total number of bytes read from write queue +system.physmem.bytesWritten 8418624 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11089400 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8406068 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 166 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3886 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 40804 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11283 # Per bank write bursts +system.physmem.perBankRdBursts::1 10909 # Per bank write bursts +system.physmem.perBankRdBursts::2 10879 # Per bank write bursts +system.physmem.perBankRdBursts::3 10544 # Per bank write bursts +system.physmem.perBankRdBursts::4 14049 # Per bank write bursts +system.physmem.perBankRdBursts::5 11359 # Per bank write bursts +system.physmem.perBankRdBursts::6 11255 # Per bank write bursts +system.physmem.perBankRdBursts::7 11497 # Per bank write bursts +system.physmem.perBankRdBursts::8 10572 # Per bank write bursts +system.physmem.perBankRdBursts::9 11295 # Per bank write bursts +system.physmem.perBankRdBursts::10 10218 # Per bank write bursts +system.physmem.perBankRdBursts::11 9589 # Per bank write bursts +system.physmem.perBankRdBursts::12 9979 # Per bank write bursts +system.physmem.perBankRdBursts::13 10701 # Per bank write bursts +system.physmem.perBankRdBursts::14 10842 # Per bank write bursts +system.physmem.perBankRdBursts::15 10903 # Per bank write bursts +system.physmem.perBankWrBursts::0 8346 # Per bank write bursts +system.physmem.perBankWrBursts::1 8306 # Per bank write bursts +system.physmem.perBankWrBursts::2 8514 # Per bank write bursts +system.physmem.perBankWrBursts::3 8219 # Per bank write bursts +system.physmem.perBankWrBursts::4 8602 # Per bank write bursts +system.physmem.perBankWrBursts::5 8561 # Per bank write bursts +system.physmem.perBankWrBursts::6 8053 # Per bank write bursts +system.physmem.perBankWrBursts::7 8529 # Per bank write bursts +system.physmem.perBankWrBursts::8 8073 # Per bank write bursts +system.physmem.perBankWrBursts::9 8804 # Per bank write bursts +system.physmem.perBankWrBursts::10 7852 # Per bank write bursts +system.physmem.perBankWrBursts::11 7407 # Per bank write bursts +system.physmem.perBankWrBursts::12 7747 # Per bank write bursts +system.physmem.perBankWrBursts::13 8181 # Per bank write bursts +system.physmem.perBankWrBursts::14 8268 # Per bank write bursts +system.physmem.perBankWrBursts::15 8079 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 58 # Number of times write queue was full causing retry -system.physmem.totGap 2827615975000 # Total gap between requests +system.physmem.numWrRetry 1 # Number of times write queue was full causing retry +system.physmem.totGap 2827546089000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 542 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) -system.physmem.readPktSize::4 2994 # Read request sizes (log2) +system.physmem.readPktSize::4 2997 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 172624 # Read request sizes (log2) +system.physmem.readPktSize::6 172487 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 167280 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 154910 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 18105 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2183 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 821 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 131071 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 154804 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 17996 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2231 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 828 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see @@ -159,161 +159,156 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1641 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6399 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6912 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6687 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7906 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7485 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 899 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2443 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2359 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2077 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1665 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1370 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1404 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1002 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 403 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 87 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 66219 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 312.955255 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 183.034234 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 334.173316 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24625 37.19% 37.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 15873 23.97% 61.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6865 10.37% 71.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3626 5.48% 77.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2732 4.13% 81.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1677 2.53% 83.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1136 1.72% 85.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1168 1.76% 87.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8517 12.86% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 66219 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6252 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.154671 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 564.033809 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6251 99.98% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6252 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6252 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.635797 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.335011 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 41.227878 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 5914 94.59% 94.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 86 1.38% 95.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 17 0.27% 96.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 16 0.26% 96.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 17 0.27% 96.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 30 0.48% 97.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 32 0.51% 97.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 14 0.22% 97.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 17 0.27% 98.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 6 0.10% 98.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 22 0.35% 98.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 18 0.29% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 7 0.11% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 1 0.02% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 1 0.02% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 6 0.10% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 4 0.06% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 4 0.06% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 3 0.05% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 5 0.08% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 16 0.26% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 2 0.03% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 3 0.05% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::400-415 1 0.02% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::448-463 1 0.02% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 3 0.05% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 1 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::704-719 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::752-767 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::864-879 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6252 # Writes before turning the bus around for reads -system.physmem.totQLat 2104913750 # Total ticks spent queuing -system.physmem.totMemAccLat 5405588750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 880180000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11957.29 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 2191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6983 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6948 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8550 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9754 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8859 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7952 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7090 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 65199 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 301.760702 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 178.342640 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.505125 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24507 37.59% 37.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 15999 24.54% 62.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6852 10.51% 72.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3716 5.70% 78.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2634 4.04% 82.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1687 2.59% 84.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1128 1.73% 86.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1089 1.67% 88.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7587 11.64% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65199 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6653 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.433789 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 560.061521 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6652 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6653 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6653 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.771682 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.345316 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 11.497785 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5824 87.54% 87.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 71 1.07% 88.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 181 2.72% 91.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 53 0.80% 92.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 64 0.96% 93.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 178 2.68% 95.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 29 0.44% 96.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 6 0.09% 96.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 9 0.14% 96.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 9 0.14% 96.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 8 0.12% 96.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 6 0.09% 96.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 170 2.56% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 4 0.06% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 6 0.09% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 8 0.12% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 2 0.03% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.02% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.03% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 4 0.06% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.02% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 11 0.17% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6653 # Writes before turning the bus around for reads +system.physmem.totQLat 2123501000 # Total ticks spent queuing +system.physmem.totMemAccLat 5421138500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 879370000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12073.99 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30707.29 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 30823.99 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.98 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.34 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 2.98 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.92 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.79 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.97 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.06 # Data bus utilization in percentage +system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.89 # Average write queue length when enqueuing -system.physmem.readRowHits 145058 # Number of row buffer hits during reads -system.physmem.writeRowHits 112529 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.40 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 76.14 # Row buffer hit rate for writes -system.physmem.avgGap 8129187.62 # Average gap between requests -system.physmem.pageHitRate 79.54 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 260517600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 142147500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 718356600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 486693360 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 184686106800 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 81488169855 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1625088668250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1892870659965 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.422846 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2703351122494 # Time in different power states -system.physmem_0.memoryStateTime::REF 94420300000 # Time in different power states +system.physmem.avgWrQLen 24.42 # Average write queue length when enqueuing +system.physmem.readRowHits 144861 # Number of row buffer hits during reads +system.physmem.writeRowHits 97354 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.37 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.00 # Row buffer hit rate for writes +system.physmem.avgGap 9077427.64 # Average gap between requests +system.physmem.pageHitRate 78.78 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 255989160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 139676625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 715845000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 435002400 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 184681529760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 81048006450 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1625432730750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1892708780145 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.382186 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2703925000250 # Time in different power states +system.physmem_0.memoryStateTime::REF 94417960000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 29844456256 # Time in different power states +system.physmem_0.memoryStateTime::ACT 29202842250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 240098040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 131005875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 654716400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 470862720 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 184686106800 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 80123990850 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1626285316500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1892592097185 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.324331 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2705354976994 # Time in different power states -system.physmem_1.memoryStateTime::REF 94420300000 # Time in different power states +system.physmem_1.actEnergy 236915280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 129269250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 655964400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 417383280 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 184681529760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 80055144540 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1626303662250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1892479868760 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.301228 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2705388162750 # Time in different power states +system.physmem_1.memoryStateTime::REF 94417960000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 27840895506 # Time in different power states +system.physmem_1.memoryStateTime::ACT 27740163750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory @@ -333,15 +328,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 46937284 # Number of BP lookups -system.cpu.branchPred.condPredicted 24041936 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1233234 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 29553356 # Number of BTB lookups -system.cpu.branchPred.BTBHits 21362007 # Number of BTB hits +system.cpu.branchPred.lookups 46902830 # Number of BP lookups +system.cpu.branchPred.condPredicted 24030897 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1232795 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 29532360 # Number of BTB lookups +system.cpu.branchPred.BTBHits 21346058 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 72.282847 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 11754741 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 33891 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 72.280231 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 11742213 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 33846 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -372,45 +367,45 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.dtb.walker.walks 9923 # Table walker walks requested -system.cpu.checker.dtb.walker.walksShort 9923 # Table walker walks initiated with short descriptors -system.cpu.checker.dtb.walker.walkWaitTime::samples 9923 # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walkWaitTime::0 9923 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walkWaitTime::total 9923 # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walksPending::samples 230116500 # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walksPending::0 230116500 100.00% 100.00% # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walksPending::total 230116500 # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walkPageSizes::4K 6339 81.70% 81.70% # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkPageSizes::1M 1420 18.30% 100.00% # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkPageSizes::total 7759 # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 9923 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walks 9925 # Table walker walks requested +system.cpu.checker.dtb.walker.walksShort 9925 # Table walker walks initiated with short descriptors +system.cpu.checker.dtb.walker.walkWaitTime::samples 9925 # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walkWaitTime::0 9925 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walkWaitTime::total 9925 # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walksPending::samples 227240000 # Table walker pending requests distribution +system.cpu.checker.dtb.walker.walksPending::0 227240000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.checker.dtb.walker.walksPending::total 227240000 # Table walker pending requests distribution +system.cpu.checker.dtb.walker.walkPageSizes::4K 6352 81.85% 81.85% # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkPageSizes::1M 1409 18.15% 100.00% # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkPageSizes::total 7761 # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 9925 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 9923 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 7759 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 9925 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 7761 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 7759 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin::total 17682 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 7761 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin::total 17686 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 24588859 # DTB read hits -system.cpu.checker.dtb.read_misses 8478 # DTB read misses -system.cpu.checker.dtb.write_hits 19638229 # DTB write hits -system.cpu.checker.dtb.write_misses 1445 # DTB write misses +system.cpu.checker.dtb.read_hits 24580805 # DTB read hits +system.cpu.checker.dtb.read_misses 8471 # DTB read misses +system.cpu.checker.dtb.write_hits 19633932 # DTB write hits +system.cpu.checker.dtb.write_misses 1454 # DTB write misses system.cpu.checker.dtb.flush_tlb 128 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.checker.dtb.flush_entries 4321 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 1767 # Number of TLB faults due to prefetch +system.cpu.checker.dtb.prefetch_faults 1778 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 24597337 # DTB read accesses -system.cpu.checker.dtb.write_accesses 19639674 # DTB write accesses +system.cpu.checker.dtb.read_accesses 24589276 # DTB read accesses +system.cpu.checker.dtb.write_accesses 19635386 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 44227088 # DTB hits -system.cpu.checker.dtb.misses 9923 # DTB misses -system.cpu.checker.dtb.accesses 44237011 # DTB accesses +system.cpu.checker.dtb.hits 44214737 # DTB hits +system.cpu.checker.dtb.misses 9925 # DTB misses +system.cpu.checker.dtb.accesses 44224662 # DTB accesses system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -445,9 +440,9 @@ system.cpu.checker.itb.walker.walksShort 4826 # Ta system.cpu.checker.itb.walker.walkWaitTime::samples 4826 # Table walker wait (enqueue to first request) latency system.cpu.checker.itb.walker.walkWaitTime::0 4826 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.checker.itb.walker.walkWaitTime::total 4826 # Table walker wait (enqueue to first request) latency -system.cpu.checker.itb.walker.walksPending::samples 229704000 # Table walker pending requests distribution -system.cpu.checker.itb.walker.walksPending::0 229704000 100.00% 100.00% # Table walker pending requests distribution -system.cpu.checker.itb.walker.walksPending::total 229704000 # Table walker pending requests distribution +system.cpu.checker.itb.walker.walksPending::samples 226829000 # Table walker pending requests distribution +system.cpu.checker.itb.walker.walksPending::0 226829000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.checker.itb.walker.walksPending::total 226829000 # Table walker pending requests distribution system.cpu.checker.itb.walker.walkPageSizes::4K 2798 88.24% 88.24% # Table walker page sizes translated system.cpu.checker.itb.walker.walkPageSizes::1M 373 11.76% 100.00% # Table walker page sizes translated system.cpu.checker.itb.walker.walkPageSizes::total 3171 # Table walker page sizes translated @@ -458,7 +453,7 @@ system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 3171 # Table walker requests started/completed, data/inst system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 3171 # Table walker requests started/completed, data/inst system.cpu.checker.itb.walker.walkRequestOrigin::total 7997 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.inst_hits 115853330 # ITB inst hits +system.cpu.checker.itb.inst_hits 115815180 # ITB inst hits system.cpu.checker.itb.inst_misses 4826 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -475,11 +470,11 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 115858156 # ITB inst accesses -system.cpu.checker.itb.hits 115853330 # DTB hits +system.cpu.checker.itb.inst_accesses 115820006 # ITB inst accesses +system.cpu.checker.itb.hits 115815180 # DTB hits system.cpu.checker.itb.misses 4826 # DTB misses -system.cpu.checker.itb.accesses 115858156 # DTB accesses -system.cpu.checker.numCycles 139105254 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 115820006 # DTB accesses +system.cpu.checker.numCycles 139058612 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -511,84 +506,86 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 72371 # Table walker walks requested -system.cpu.dtb.walker.walksShort 72371 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29709 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22637 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 20025 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 52346 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 408.397967 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 2384.163324 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-4095 50769 96.99% 96.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::4096-8191 522 1.00% 97.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::8192-12287 392 0.75% 98.73% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::12288-16383 322 0.62% 99.35% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::16384-20479 112 0.21% 99.56% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::20480-24575 191 0.36% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::24576-28671 14 0.03% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::28672-32767 8 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::32768-36863 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::36864-40959 2 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walks 72877 # Table walker walks requested +system.cpu.dtb.walker.walksShort 72877 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29786 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22407 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 20684 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 52193 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 427.193302 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 2519.151181 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-4095 50372 96.51% 96.51% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::4096-8191 577 1.11% 97.62% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::8192-12287 541 1.04% 98.65% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::12288-16383 349 0.67% 99.32% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::16384-20479 64 0.12% 99.44% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::20480-24575 245 0.47% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::24576-28671 20 0.04% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::28672-32767 5 0.01% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::32768-36863 6 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::36864-40959 4 0.01% 99.98% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::40960-45055 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::45056-49151 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::45056-49151 3 0.01% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::49152-53247 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::61440-65535 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 52346 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 17999 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 11613.492583 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 9112.637070 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 7625.312992 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-16383 13355 74.20% 74.20% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::16384-32767 4455 24.75% 98.95% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::32768-49151 181 1.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::49152-65535 5 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::81920-98303 2 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkWaitTime::53248-57343 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 52193 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 18420 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 12316.720955 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 9894.996282 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 7919.116299 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-16383 13659 74.15% 74.15% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::16384-32767 4520 24.54% 98.69% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::32768-49151 229 1.24% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::49152-65535 5 0.03% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-81919 1 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 17999 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 117490693224 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.629020 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.491115 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 117435257724 99.95% 99.95% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 37744500 0.03% 99.98% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 7698500 0.01% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 6179000 0.01% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 1033000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 848500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 1404000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 520500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::16-17 7500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 117490693224 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6498 81.61% 81.61% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1464 18.39% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7962 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 72371 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkCompletionTime::total 18420 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 117420807224 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.629573 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.491742 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 117361135224 99.95% 99.95% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 40228000 0.03% 99.98% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 8514000 0.01% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 6836000 0.01% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 1132500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 742000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 1403500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 806000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::16-17 10000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 117420807224 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6507 81.76% 81.76% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1452 18.24% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7959 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 72877 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 72371 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7962 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 72877 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7959 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7962 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 80333 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7959 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 80836 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 25461869 # DTB read hits -system.cpu.dtb.read_misses 62291 # DTB read misses -system.cpu.dtb.write_hits 19915387 # DTB write hits -system.cpu.dtb.write_misses 10080 # DTB write misses +system.cpu.dtb.read_hits 25454298 # DTB read hits +system.cpu.dtb.read_misses 62609 # DTB read misses +system.cpu.dtb.write_hits 19910353 # DTB write hits +system.cpu.dtb.write_misses 10268 # DTB write misses system.cpu.dtb.flush_tlb 128 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_entries 4354 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 348 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 2290 # Number of TLB faults due to prefetch +system.cpu.dtb.align_faults 354 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 2301 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1335 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 25524160 # DTB read accesses -system.cpu.dtb.write_accesses 19925467 # DTB write accesses +system.cpu.dtb.perms_faults 1336 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 25516907 # DTB read accesses +system.cpu.dtb.write_accesses 19920621 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 45377256 # DTB hits -system.cpu.dtb.misses 72371 # DTB misses -system.cpu.dtb.accesses 45449627 # DTB accesses +system.cpu.dtb.hits 45364651 # DTB hits +system.cpu.dtb.misses 72877 # DTB misses +system.cpu.dtb.accesses 45437528 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -618,56 +615,56 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 11974 # Table walker walks requested -system.cpu.itb.walker.walksShort 11974 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 3948 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksShortTerminationLevel::Level2 7776 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 250 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 11724 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 570.794951 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 2803.545728 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-8191 11373 97.01% 97.01% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::8192-16383 269 2.29% 99.30% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::16384-24575 71 0.61% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::24576-32767 7 0.06% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walks 11947 # Table walker walks requested +system.cpu.itb.walker.walksShort 11947 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 3916 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 7772 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 259 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 11688 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 646.175565 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 3062.873414 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-8191 11278 96.49% 96.49% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::8192-16383 250 2.14% 98.63% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::16384-24575 145 1.24% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::24576-32767 11 0.09% 99.97% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::40960-49151 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::49152-57343 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::57344-65535 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::57344-65535 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::65536-73727 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::73728-81919 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 11724 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 3579 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 12176.865046 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 9546.126127 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7774.383636 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-8191 1294 36.16% 36.16% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::8192-16383 1330 37.16% 73.32% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-24575 901 25.17% 98.49% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::24576-32767 22 0.61% 99.11% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::32768-40959 25 0.70% 99.80% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::40960-49151 5 0.14% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkWaitTime::total 11688 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3588 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 13165.830546 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 10749.838149 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7878.482425 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-8191 1266 35.28% 35.28% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::8192-16383 1353 37.71% 72.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-24575 898 25.03% 98.02% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::24576-32767 28 0.78% 98.80% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::32768-40959 19 0.53% 99.33% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::40960-49151 22 0.61% 99.94% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::81920-90111 2 0.06% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 3579 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 23001352712 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.973391 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.161136 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 612637000 2.66% 2.66% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 22388223712 97.33% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 416000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::3 45500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::4 30500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 23001352712 # Table walker pending requests distribution +system.cpu.itb.walker.walkCompletionTime::total 3588 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 22931465712 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.972560 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.163591 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 629948000 2.75% 2.75% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 22300919212 97.25% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 517500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 46500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::4 34500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 22931465712 # Table walker pending requests distribution system.cpu.itb.walker.walkPageSizes::4K 3007 90.33% 90.33% # Table walker page sizes translated system.cpu.itb.walker.walkPageSizes::1M 322 9.67% 100.00% # Table walker page sizes translated system.cpu.itb.walker.walkPageSizes::total 3329 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 11974 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 11974 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 11947 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 11947 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3329 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 3329 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 15303 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 66270436 # ITB inst hits -system.cpu.itb.inst_misses 11974 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin::total 15276 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 66251443 # ITB inst hits +system.cpu.itb.inst_misses 11947 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -676,98 +673,98 @@ system.cpu.itb.flush_tlb 128 # Nu system.cpu.itb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 3095 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 3094 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2189 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2204 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 66282410 # ITB inst accesses -system.cpu.itb.hits 66270436 # DTB hits -system.cpu.itb.misses 11974 # DTB misses -system.cpu.itb.accesses 66282410 # DTB accesses -system.cpu.numCycles 263104506 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 66263390 # ITB inst accesses +system.cpu.itb.hits 66251443 # DTB hits +system.cpu.itb.misses 11947 # DTB misses +system.cpu.itb.accesses 66263390 # DTB accesses +system.cpu.numCycles 263015768 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 104871759 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 184678718 # Number of instructions fetch has processed -system.cpu.fetch.Branches 46937284 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33116748 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 147875517 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6159108 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 184684 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 7836 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 337023 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 520063 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 109 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 66270632 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1094853 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5249 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 256876545 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.877001 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.234757 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 104824855 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 184645834 # Number of instructions fetch has processed +system.cpu.fetch.Branches 46902830 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33088271 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 147851260 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6154028 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 194015 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 8214 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 337761 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 519343 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 115 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 66251613 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1117287 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5276 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 256812577 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.876982 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.234768 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 157598366 61.35% 61.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 29238251 11.38% 72.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 14077167 5.48% 78.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 55962761 21.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 157563978 61.35% 61.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 29227624 11.38% 72.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 14070468 5.48% 78.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 55950507 21.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 256876545 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.178398 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.701922 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 78017085 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 107782223 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 64633482 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3841952 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2601803 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3422699 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 486058 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 157446500 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3690202 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2601803 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 83861883 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 10277178 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 74822964 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 62634848 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 22677869 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 146804130 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 949467 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 441862 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 64017 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 17858 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 19908152 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 150492299 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 678751292 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 164435882 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10966 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 141814735 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8677561 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2844686 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2648369 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13872312 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26410080 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21300681 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1687720 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2166938 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 143540852 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2119167 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 143328298 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 272168 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8409052 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14689564 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 125312 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 256876545 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.557966 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.879925 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 256812577 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.178327 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.702033 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 77991094 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 107772330 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 64608850 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3840943 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2599360 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3422500 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 485951 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 157387425 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3689294 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2599360 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 83831420 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 10325294 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 74929297 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 62613486 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 22513720 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 146758942 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 947731 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 441861 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 64728 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 18116 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 19773665 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 150448126 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 678536041 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 164391886 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10952 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 141768145 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 8679978 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2842610 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2646257 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13861181 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26401367 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21296245 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1688204 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2197018 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 143495141 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2119201 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 143282260 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 272024 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8407927 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14689646 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 125355 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 256812577 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.557925 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.879880 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 168573864 65.62% 65.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 45206232 17.60% 83.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 31980064 12.45% 95.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 10303635 4.01% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 812717 0.32% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 168546355 65.63% 65.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 45160300 17.58% 83.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 32009606 12.46% 95.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 10282549 4.00% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 813734 0.32% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -775,44 +772,44 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 256876545 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 256812577 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 7356620 32.59% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 33 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5633879 24.95% 57.54% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 9585743 42.46% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7349115 32.77% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 31 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5633990 25.12% 57.89% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 9444813 42.11% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 96002656 66.98% 66.98% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 114517 0.08% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 95970305 66.98% 66.98% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 114498 0.08% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.06% # Type of FU issued @@ -836,101 +833,101 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.06% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 8586 0.01% 67.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 8584 0.01% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 26193106 18.27% 85.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21007096 14.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 26184358 18.27% 85.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21002178 14.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 143328298 # Type of FU issued -system.cpu.iq.rate 0.544758 # Inst issue rate -system.cpu.iq.fu_busy_cnt 22576275 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.157514 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 566346237 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 154074171 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 140211060 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 35347 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 13216 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 143282260 # Type of FU issued +system.cpu.iq.rate 0.544767 # Inst issue rate +system.cpu.iq.fu_busy_cnt 22427949 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.156530 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 566041717 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 154027392 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 140167901 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 35353 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 13184 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 11430 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 165879208 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 23028 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 323617 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 165684822 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 23050 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 323667 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1493976 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1493736 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 505 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18357 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 705133 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18344 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 705002 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 87833 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6849 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 87759 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6780 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2601803 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 997477 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 311742 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 145861072 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 2599360 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 993976 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 306451 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 145815403 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26410080 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21300681 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1095001 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 17866 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 276819 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18357 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 317506 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 471434 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 788940 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 142382517 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25789725 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 873528 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 26401367 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21296245 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1095018 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 17939 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 271517 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18344 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 317394 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 471153 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 788547 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 142337327 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25781702 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 872174 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 201053 # number of nop insts executed -system.cpu.iew.exec_refs 46667574 # number of memory reference insts executed -system.cpu.iew.exec_branches 26530134 # Number of branches executed -system.cpu.iew.exec_stores 20877849 # Number of stores executed -system.cpu.iew.exec_rate 0.541163 # Inst execution rate -system.cpu.iew.wb_sent 141996041 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 140222490 # cumulative count of insts written-back -system.cpu.iew.wb_producers 63271750 # num instructions producing a value -system.cpu.iew.wb_consumers 95823649 # num instructions consuming a value +system.cpu.iew.exec_nop 201061 # number of nop insts executed +system.cpu.iew.exec_refs 46654499 # number of memory reference insts executed +system.cpu.iew.exec_branches 26517785 # Number of branches executed +system.cpu.iew.exec_stores 20872797 # Number of stores executed +system.cpu.iew.exec_rate 0.541174 # Inst execution rate +system.cpu.iew.wb_sent 141950761 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 140179331 # cumulative count of insts written-back +system.cpu.iew.wb_producers 63256602 # num instructions producing a value +system.cpu.iew.wb_consumers 95788019 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.532954 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.660294 # average fanout of values written-back +system.cpu.iew.wb_rate 0.532969 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.660381 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7612502 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1993855 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 755483 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 253938585 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.541099 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.141491 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7614067 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1993846 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 755141 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 253876624 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.541055 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.141749 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 180469459 71.07% 71.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 43296577 17.05% 88.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15470824 6.09% 94.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4378580 1.72% 95.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6397908 2.52% 98.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1648304 0.65% 99.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 799189 0.31% 99.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 418335 0.16% 99.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1059409 0.42% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 180454723 71.08% 71.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 43255238 17.04% 88.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15471181 6.09% 94.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4380130 1.73% 95.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6364867 2.51% 98.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1673276 0.66% 99.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 800938 0.32% 99.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 418318 0.16% 99.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1057953 0.42% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 253938585 # Number of insts commited each cycle -system.cpu.commit.committedInsts 113305988 # Number of instructions committed -system.cpu.commit.committedOps 137405868 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 253876624 # Number of insts commited each cycle +system.cpu.commit.committedInsts 113269928 # Number of instructions committed +system.cpu.commit.committedOps 137361316 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 45511652 # Number of memory references committed -system.cpu.commit.loads 24916104 # Number of loads committed -system.cpu.commit.membars 814017 # Number of memory barriers committed -system.cpu.commit.branches 26045610 # Number of branches committed +system.cpu.commit.refs 45498874 # Number of memory references committed +system.cpu.commit.loads 24907631 # Number of loads committed +system.cpu.commit.membars 814016 # Number of memory barriers committed +system.cpu.commit.branches 26032948 # Number of branches committed system.cpu.commit.fp_insts 11428 # Number of committed floating point instructions. -system.cpu.commit.int_insts 120229462 # Number of committed integer instructions. -system.cpu.commit.function_calls 4892502 # Number of function calls committed. +system.cpu.commit.int_insts 120189151 # Number of committed integer instructions. +system.cpu.commit.function_calls 4888294 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 91772138 66.79% 66.79% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 113493 0.08% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 91740391 66.79% 66.79% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 113468 0.08% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction @@ -954,489 +951,501 @@ system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 8585 0.01% 66.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 8583 0.01% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 24916104 18.13% 85.01% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 20595548 14.99% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 24907631 18.13% 85.01% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 20591243 14.99% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 137405868 # Class of committed instruction -system.cpu.commit.bw_lim_events 1059409 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 375672050 # The number of ROB reads -system.cpu.rob.rob_writes 292972268 # The number of ROB writes -system.cpu.timesIdled 891577 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 6227961 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 5392127867 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 113151083 # Number of Instructions Simulated -system.cpu.committedOps 137250963 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.325250 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.325250 # CPI: Total CPI of All Threads -system.cpu.ipc 0.430061 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.430061 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 155826636 # number of integer regfile reads -system.cpu.int_regfile_writes 88633022 # number of integer regfile writes -system.cpu.fp_regfile_reads 9606 # number of floating regfile reads +system.cpu.commit.op_class_0::total 137361316 # Class of committed instruction +system.cpu.commit.bw_lim_events 1057953 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 375595727 # The number of ROB reads +system.cpu.rob.rob_writes 292884314 # The number of ROB writes +system.cpu.timesIdled 891951 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6203191 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 5392076833 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 113115023 # Number of Instructions Simulated +system.cpu.committedOps 137206411 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.325206 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.325206 # CPI: Total CPI of All Threads +system.cpu.ipc 0.430069 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.430069 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 155781292 # number of integer regfile reads +system.cpu.int_regfile_writes 88602574 # number of integer regfile writes +system.cpu.fp_regfile_reads 9590 # number of floating regfile reads system.cpu.fp_regfile_writes 2716 # number of floating regfile writes -system.cpu.cc_regfile_reads 502981881 # number of cc regfile reads -system.cpu.cc_regfile_writes 53178096 # number of cc regfile writes -system.cpu.misc_regfile_reads 334359649 # number of misc regfile reads -system.cpu.misc_regfile_writes 1519760 # number of misc regfile writes -system.cpu.dcache.tags.replacements 839617 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.954240 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40126369 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 840129 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 47.762152 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 270754250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.954240 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999911 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999911 # Average percentage of cache occupancy +system.cpu.cc_regfile_reads 502823667 # number of cc regfile reads +system.cpu.cc_regfile_writes 53168068 # number of cc regfile writes +system.cpu.misc_regfile_reads 334407132 # number of misc regfile reads +system.cpu.misc_regfile_writes 1519751 # number of misc regfile writes +system.cpu.dcache.tags.replacements 839265 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.954798 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40095385 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 839777 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 47.745276 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 267431500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.954798 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999912 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999912 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 359 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 360 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 179354797 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 179354797 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23316087 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23316087 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 15561026 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 15561026 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 345829 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 345829 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 441066 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 441066 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 459481 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 459481 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 38877113 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 38877113 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 39222942 # number of overall hits -system.cpu.dcache.overall_hits::total 39222942 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 705718 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 705718 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3595150 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3595150 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 177438 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 177438 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 26862 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 26862 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 179307579 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 179307579 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23304230 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23304230 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 15542006 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 15542006 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 345703 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 345703 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 441081 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 441081 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 459484 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 459484 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 38846236 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 38846236 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 39191939 # number of overall hits +system.cpu.dcache.overall_hits::total 39191939 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 710133 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 710133 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3609878 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3609878 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 177558 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 177558 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 26867 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 26867 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 4300868 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4300868 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4478306 # number of overall misses -system.cpu.dcache.overall_misses::total 4478306 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10273111663 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10273111663 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 149502808344 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 149502808344 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 365521996 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 365521996 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 4320011 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4320011 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4497569 # number of overall misses +system.cpu.dcache.overall_misses::total 4497569 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10292232000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10292232000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 148465108677 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 148465108677 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 365302500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 365302500 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 209000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 209000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 159775920007 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 159775920007 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 159775920007 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 159775920007 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24021805 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24021805 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19156176 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19156176 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 523267 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 523267 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 467928 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 467928 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 459486 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 459486 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 43177981 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 43177981 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 43701248 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 43701248 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029378 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.029378 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.187676 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.187676 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.339096 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.339096 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057406 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057406 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_latency::cpu.data 158757340677 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 158757340677 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 158757340677 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 158757340677 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24014363 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24014363 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19151884 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19151884 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 523261 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 523261 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 467948 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 467948 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 459489 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 459489 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 43166247 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 43166247 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43689508 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43689508 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029571 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.029571 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188487 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.188487 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.339330 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.339330 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057414 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057414 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000011 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000011 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.099608 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.099608 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.102475 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.102475 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14556.964202 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14556.964202 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41584.581546 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41584.581546 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13607.400640 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13607.400640 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.100078 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.100078 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.102944 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.102944 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14493.386450 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14493.386450 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41127.458789 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41127.458789 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13596.698552 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13596.698552 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 41800 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 41800 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37149.691645 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37149.691645 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35677.758511 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 35677.758511 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 582483 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 36749.290841 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 36749.290841 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35298.478062 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35298.478062 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 590707 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 7397 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 7439 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 78.745843 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 79.406775 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 696320 # number of writebacks -system.cpu.dcache.writebacks::total 696320 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 291077 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 291077 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3294875 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3294875 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18482 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 18482 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3585952 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3585952 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3585952 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3585952 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414641 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 414641 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300275 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 300275 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119609 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 119609 # number of SoftPFReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8380 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 8380 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 696043 # number of writebacks +system.cpu.dcache.writebacks::total 696043 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 295841 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 295841 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3309634 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3309634 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18475 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 18475 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3605475 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3605475 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3605475 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3605475 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414292 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 414292 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300244 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 300244 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119628 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 119628 # number of SoftPFReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8392 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 8392 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 714916 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 714916 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 834525 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 834525 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 714536 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 714536 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 834164 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 834164 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31127 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 31127 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 58711 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5660697158 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5660697158 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13235281165 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 13235281165 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1562991253 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1562991253 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 123125251 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 123125251 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 201500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 201500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18895978323 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 18895978323 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20458969576 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 20458969576 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5831942750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5831942750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4511868951 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4511868951 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10343811701 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 10343811701 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017261 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017261 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015675 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015675 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228581 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228581 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017909 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017909 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5857375000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5857375000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13373750471 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 13373750471 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1627994000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1627994000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 128038500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 128038500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 204000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 204000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19231125471 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 19231125471 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20859119471 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 20859119471 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5908113500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5908113500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4570874950 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4570874950 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10478988450 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10478988450 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017252 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017252 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015677 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015677 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228620 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228620 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017934 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017934 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016557 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016557 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019096 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.019096 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13652.043956 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13652.043956 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44077.199784 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44077.199784 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13067.505397 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13067.505397 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14692.750716 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14692.750716 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 40300 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 40300 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26431.046896 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26431.046896 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24515.706032 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24515.706032 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 187359.615446 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 187359.615446 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 163568.334941 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163568.334941 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 176181.834767 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 176181.834767 # average overall mshr uncacheable latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016553 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016553 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019093 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019093 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14138.276868 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14138.276868 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44542.939979 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44542.939979 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13608.803959 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13608.803959 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15257.209247 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15257.209247 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 40800 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 40800 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26914.144943 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26914.144943 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25006.017367 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25006.017367 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189806.711215 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 189806.711215 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 165707.473535 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 165707.473535 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 178484.244009 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 178484.244009 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1892540 # number of replacements -system.cpu.icache.tags.tagsinuse 511.345997 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 64285030 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1893052 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 33.958407 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 13579028250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.345997 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.998723 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.998723 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1891955 # number of replacements +system.cpu.icache.tags.tagsinuse 511.348314 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 64263909 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1892467 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 33.957744 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 13555622500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.348314 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.998727 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.998727 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 228 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 68160699 # Number of tag accesses -system.cpu.icache.tags.data_accesses 68160699 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 64285030 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 64285030 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 64285030 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 64285030 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 64285030 # number of overall hits -system.cpu.icache.overall_hits::total 64285030 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1982600 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1982600 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1982600 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1982600 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1982600 # number of overall misses -system.cpu.icache.overall_misses::total 1982600 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 26922947970 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 26922947970 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 26922947970 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 26922947970 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 26922947970 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 26922947970 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 66267630 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 66267630 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 66267630 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 66267630 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 66267630 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 66267630 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029918 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.029918 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.029918 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.029918 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.029918 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.029918 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13579.616650 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13579.616650 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13579.616650 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13579.616650 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13579.616650 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13579.616650 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2392 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 68141093 # Number of tag accesses +system.cpu.icache.tags.data_accesses 68141093 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 64263909 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 64263909 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 64263909 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 64263909 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 64263909 # number of overall hits +system.cpu.icache.overall_hits::total 64263909 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1984699 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1984699 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1984699 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1984699 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1984699 # number of overall misses +system.cpu.icache.overall_misses::total 1984699 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 26888996997 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 26888996997 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 26888996997 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 26888996997 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 26888996997 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 26888996997 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 66248608 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 66248608 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 66248608 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 66248608 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 66248608 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 66248608 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029958 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.029958 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.029958 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.029958 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.029958 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.029958 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13548.148609 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13548.148609 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13548.148609 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13548.148609 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13548.148609 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13548.148609 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2508 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 125 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 127 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 19.136000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 19.748031 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 89529 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 89529 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 89529 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 89529 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 89529 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 89529 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1893071 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1893071 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1893071 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1893071 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1893071 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1893071 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3002 # number of ReadReq MSHR uncacheable -system.cpu.icache.ReadReq_mshr_uncacheable::total 3002 # number of ReadReq MSHR uncacheable -system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3002 # number of overall MSHR uncacheable misses -system.cpu.icache.overall_mshr_uncacheable_misses::total 3002 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23219754000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23219754000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23219754000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23219754000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23219754000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23219754000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 225366000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 225366000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 225366000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 225366000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028567 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028567 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028567 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.028567 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028567 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.028567 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12265.654062 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12265.654062 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12265.654062 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12265.654062 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12265.654062 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12265.654062 # average overall mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 75071.952032 # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 75071.952032 # average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 75071.952032 # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 75071.952032 # average overall mshr uncacheable latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 92212 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 92212 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 92212 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 92212 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 92212 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 92212 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1892487 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1892487 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1892487 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1892487 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1892487 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1892487 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3005 # number of ReadReq MSHR uncacheable +system.cpu.icache.ReadReq_mshr_uncacheable::total 3005 # number of ReadReq MSHR uncacheable +system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3005 # number of overall MSHR uncacheable misses +system.cpu.icache.overall_mshr_uncacheable_misses::total 3005 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24145787497 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 24145787497 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24145787497 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 24145787497 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24145787497 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 24145787497 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 225776500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 225776500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 225776500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 225776500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028566 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028566 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028566 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.028566 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028566 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.028566 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12758.760032 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12758.760032 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12758.760032 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12758.760032 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12758.760032 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12758.760032 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 75133.610649 # average ReadReq mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 75133.610649 # average ReadReq mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 75133.610649 # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 75133.610649 # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 103160 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65071.102218 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3020124 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 168359 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 17.938596 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 103023 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65070.034194 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5007824 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 168222 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 29.769138 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 49253.315053 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 11.936082 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 2.797931 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 10086.820532 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 5716.232619 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.751546 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000182 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 49133.665655 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 12.985449 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 2.797952 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 10208.479538 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 5712.105601 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.749720 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000198 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000043 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.153913 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.087223 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.992906 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65183 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.155769 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.087160 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.992890 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 17 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65182 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 17 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 152 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2920 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6837 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55246 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000244 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994614 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 28477722 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 28477722 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 56030 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12587 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 1873051 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 528182 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2469850 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 696320 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 696320 # number of Writeback hits +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 153 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2916 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6860 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55225 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000259 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994598 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 44376961 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 44376961 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 56023 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12549 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 68572 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 696043 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 696043 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 36 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 36 # number of UpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 157101 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 157101 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 56030 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 12587 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1873051 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 685283 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2626951 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 56030 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 12587 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1873051 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 685283 # number of overall hits -system.cpu.l2cache.overall_hits::total 2626951 # number of overall hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 157187 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 157187 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1872509 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1872509 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 527843 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 527843 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 56023 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 12549 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 1872509 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 685030 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2626111 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 56023 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 12549 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1872509 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 685030 # number of overall hits +system.cpu.l2cache.overall_hits::total 2626111 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 21 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 19985 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 14326 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 34339 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2720 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2720 # number of UpgradeReq misses +system.cpu.l2cache.ReadReq_misses::total 28 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2721 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2721 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 140540 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 140540 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 140423 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 140423 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 19944 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 19944 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 14346 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 14346 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 21 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 19985 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 154866 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 174879 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 19944 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 154769 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 174741 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 21 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 19985 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 154866 # number of overall misses -system.cpu.l2cache.overall_misses::total 174879 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1759750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 789750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1637862750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1227493750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2867906000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 966469 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 966469 # number of UpgradeReq miss cycles +system.cpu.l2cache.overall_misses::cpu.inst 19944 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 154769 # number of overall misses +system.cpu.l2cache.overall_misses::total 174741 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1844500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 579500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2424000 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 955000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 955000 # number of UpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 165000 # number of SCUpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::total 165000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11197753141 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 11197753141 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1759750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 789750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1637862750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 12425246891 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 14065659141 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1759750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 789750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1637862750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12425246891 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 14065659141 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 56051 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12594 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1893036 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 542508 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2504189 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 696320 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 696320 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11187095500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 11187095500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1623118000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 1623118000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1226117500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 1226117500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1844500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 579500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1623118000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12413213000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 14038755000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1844500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 579500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1623118000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12413213000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 14038755000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 56044 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12556 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 68600 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 696043 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 696043 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2757 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2757 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 5 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 297641 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 297641 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 56051 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 12594 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1893036 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 840149 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2801830 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 56051 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 12594 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1893036 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 840149 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2801830 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 297610 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 297610 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1892453 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1892453 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 542189 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 542189 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 56044 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 12556 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1892453 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 839799 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2800852 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 56044 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 12556 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1892453 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 839799 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2800852 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000375 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000556 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010557 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026407 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.013713 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986938 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986938 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000558 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.000408 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986942 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986942 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.400000 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.400000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.472180 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.472180 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.471836 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.471836 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010539 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010539 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.026459 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.026459 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000375 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000556 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010557 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.184332 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.062416 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000558 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010539 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.184293 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.062389 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000375 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000556 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010557 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.184332 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.062416 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 83797.619048 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 112821.428571 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81954.603453 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85682.936619 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 83517.458284 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 355.319485 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 355.319485 # average UpgradeReq miss latency +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000558 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010539 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.184293 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.062389 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 87833.333333 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 82785.714286 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 86571.428571 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 350.973907 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 350.973907 # average UpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 82500 # average SCUpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 82500 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79676.626875 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79676.626875 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 83797.619048 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 112821.428571 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81954.603453 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80232.245238 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 80430.807250 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 83797.619048 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 112821.428571 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81954.603453 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80232.245238 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 80430.807250 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79667.116498 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79667.116498 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81383.774569 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81383.774569 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85467.551931 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85467.551931 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 87833.333333 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 82785.714286 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81383.774569 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80204.776150 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 80340.360877 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 87833.333333 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 82785.714286 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81383.774569 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80204.776150 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 80340.360877 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1445,176 +1454,187 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 94866 # number of writebacks -system.cpu.l2cache.writebacks::total 94866 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 22 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 112 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 134 # number of ReadReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 94881 # number of writebacks +system.cpu.l2cache.writebacks::total 94881 # number of writebacks +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 22 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 22 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 111 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 111 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 22 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 112 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 134 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 111 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 133 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 22 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 112 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 134 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 111 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 133 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 21 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 19963 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 14214 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 34205 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2720 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2720 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 28 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2721 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2721 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 140540 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 140540 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 140423 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 140423 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 19922 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 19922 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 14235 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 14235 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 21 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 19963 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 154754 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 174745 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 19922 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 154658 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 174608 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 21 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 19963 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 154754 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 174745 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3002 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.overall_mshr_misses::cpu.inst 19922 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 154658 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 174608 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3005 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31127 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34129 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34132 # number of ReadReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3002 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3005 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61713 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1495250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 701750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1386544250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1041614500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2430355750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 48397220 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 48397220 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 140500 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 140500 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9440469859 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9440469859 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1495250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 701750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1386544250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10482084359 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 11870825609 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1495250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 701750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1386544250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10482084359 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 11870825609 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 181832000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5395669750 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5577501750 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4151610000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4151610000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 181832000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9547279750 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9729111750 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61716 # number of overall MSHR uncacheable misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1634500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 509500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2144000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 56503000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 56503000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 145000 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 145000 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9782865500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9782865500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1422648500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1422648500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1076334500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1076334500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1634500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 509500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1422648500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10859200000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12283992500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1634500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 509500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1422648500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10859200000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 12283992500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 188213500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5519024000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5707237500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4252080000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4252080000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 188213500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9771104000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9959317500 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000375 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010545 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026201 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013659 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986938 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986938 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000558 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000408 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986942 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986942 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.400000 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.472180 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.472180 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.471836 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.471836 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010527 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010527 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026255 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.026255 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000375 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010545 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.184198 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.062368 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000558 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010527 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.184161 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.062341 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000375 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010545 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.184198 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.062368 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 100250 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69455.705555 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73280.885043 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71052.645812 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17793.095588 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17793.095588 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70250 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70250 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67172.832354 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67172.832354 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 100250 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69455.705555 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67733.850879 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67932.276225 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 100250 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69455.705555 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67733.850879 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67932.276225 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 60570.286476 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173343.712854 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163424.118785 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 150507.903132 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150507.903132 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 60570.286476 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162614.837935 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 157650.928492 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000558 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010527 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.184161 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.062341 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 77833.333333 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 72785.714286 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 76571.428571 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20765.527380 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20765.527380 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 72500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 72500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69667.116498 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69667.116498 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71410.927618 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71410.927618 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75611.837021 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75611.837021 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 77833.333333 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 72785.714286 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71410.927618 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70214.279248 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70351.830958 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 77833.333333 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 72785.714286 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71410.927618 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70214.279248 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70351.830958 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 62633.444260 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 177306.646962 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 167210.755303 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 154150.232019 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 154150.232019 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 62633.444260 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 166427.143125 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 161373.347268 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2564424 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2564404 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 128192 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2563081 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 696320 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36268 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 827115 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1997055 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2757 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2761 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 297641 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 297641 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3792109 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2499777 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 32094 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 131034 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6455014 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121202208 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98530845 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 50376 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 224204 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 220007633 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 62589 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3624998 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.036134 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.186622 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 2762 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 297610 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 297610 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1892487 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 542422 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5643819 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2634611 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 32016 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 130644 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8441090 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121164944 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98490717 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 50224 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 224176 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 219930061 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 201613 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5797948 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.046562 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.210699 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3494014 96.39% 96.39% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 130984 3.61% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5527984 95.34% 95.34% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 269964 4.66% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3624998 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2504368734 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 5797948 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3520857499 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 322500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2847443747 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2842352755 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1338896897 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1306164667 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 19507738 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 19466986 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 75011458 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74632435 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 30182 # Transaction distribution system.iobus.trans_dist::ReadResp 30182 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution -system.iobus.trans_dist::WriteResp 22790 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.iobus.trans_dist::WriteResp 59014 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) @@ -1705,23 +1725,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 198816983 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 187477456 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36845510 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36738000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36423 # number of replacements -system.iocache.tags.tagsinuse 1.000480 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.000222 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36439 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 252520633000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.000480 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062530 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062530 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 252500924000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.000222 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062514 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062514 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1729,49 +1749,49 @@ system.iocache.tags.tag_accesses 328113 # Nu system.iocache.tags.data_accesses 328113 # Number of data accesses system.iocache.ReadReq_misses::realview.ide 233 # number of ReadReq misses system.iocache.ReadReq_misses::total 233 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses system.iocache.demand_misses::realview.ide 233 # number of demand (read+write) misses system.iocache.demand_misses::total 233 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 233 # number of overall misses system.iocache.overall_misses::total 233 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 28780877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 28780877 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6657450596 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 6657450596 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 28780877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 28780877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 28780877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 28780877 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 28674877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28674877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4272498579 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4272498579 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 28674877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 28674877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 28674877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 28674877 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 233 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 233 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ide 233 # number of demand (read+write) accesses system.iocache.demand_accesses::total 233 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ide 233 # number of overall (read+write) accesses system.iocache.overall_accesses::total 233 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 123523.077253 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 123523.077253 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183785.628202 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 183785.628202 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 123523.077253 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 123523.077253 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 123523.077253 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 123523.077253 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 22928 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 123068.141631 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 123068.141631 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 117946.625966 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 117946.625966 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 123068.141631 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 123068.141631 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 123068.141631 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 123068.141631 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3494 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.562106 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1779,88 +1799,90 @@ system.iocache.writebacks::writebacks 36190 # nu system.iocache.writebacks::total 36190 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ide 233 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 233 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ide 233 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 233 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 233 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 233 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 16449877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 16449877 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4773782616 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4773782616 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 16449877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 16449877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 16449877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 16449877 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 17024877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 17024877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2461298579 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2461298579 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 17024877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 17024877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 17024877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 17024877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 70600.330472 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70600.330472 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131785.076634 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131785.076634 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 70600.330472 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70600.330472 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 70600.330472 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70600.330472 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73068.141631 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 73068.141631 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67946.625966 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67946.625966 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 73068.141631 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 73068.141631 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 73068.141631 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 73068.141631 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 68567 # Transaction distribution -system.membus.trans_dist::ReadResp 68566 # Transaction distribution +system.membus.trans_dist::ReadReq 34132 # Transaction distribution +system.membus.trans_dist::ReadResp 68549 # Transaction distribution system.membus.trans_dist::WriteReq 27584 # Transaction distribution system.membus.trans_dist::WriteResp 27584 # Transaction distribution -system.membus.trans_dist::Writeback 131056 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4579 # Transaction distribution +system.membus.trans_dist::Writeback 131071 # Transaction distribution +system.membus.trans_dist::CleanEvict 8154 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4580 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4581 # Transaction distribution -system.membus.trans_dist::ReadExReq 138681 # Transaction distribution -system.membus.trans_dist::ReadExResp 138681 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4582 # Transaction distribution +system.membus.trans_dist::ReadExReq 138564 # Transaction distribution +system.membus.trans_dist::ReadExResp 138564 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 34418 # Transaction distribution +system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 465382 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 572946 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108886 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108886 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 681832 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 473273 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 580837 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108898 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108898 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 689735 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17186044 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 17349437 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21984893 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17178284 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 17341677 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19658797 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 497 # Total snoops (count) -system.membus.snoop_fanout::samples 406751 # Request fanout histogram +system.membus.snoop_fanout::samples 414951 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 406751 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 414951 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 406751 # Request fanout histogram -system.membus.reqLayer0.occupancy 83856500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 414951 # Request fanout histogram +system.membus.reqLayer0.occupancy 83605000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1725500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1746000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1057992643 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 911806448 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1020413671 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1019741659 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 37506490 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64533936 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 22d20f171..51ea3fd8c 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,166 +1,166 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.625378 # Number of seconds simulated -sim_ticks 2625378187500 # Number of ticks simulated -final_tick 2625378187500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.625395 # Number of seconds simulated +sim_ticks 2625394935000 # Number of ticks simulated +final_tick 2625394935000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 105357 # Simulator instruction rate (inst/s) -host_op_rate 127837 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2300779000 # Simulator tick rate (ticks/s) -host_mem_usage 602544 # Number of bytes of host memory used -host_seconds 1141.08 # Real time elapsed on the host -sim_insts 120220550 # Number of instructions simulated -sim_ops 145872273 # Number of ops (including micro ops) simulated +host_inst_rate 95356 # Simulator instruction rate (inst/s) +host_op_rate 115687 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2080724894 # Simulator tick rate (ticks/s) +host_mem_usage 655064 # Number of bytes of host memory used +host_seconds 1261.77 # Real time elapsed on the host +sim_insts 120317196 # Number of instructions simulated +sim_ops 145970023 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 1728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1156128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1193576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8234944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 336832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 657616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 605504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 1600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1152320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1224232 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8325184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 318816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 736276 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 690624 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12188376 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1156128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 336832 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1492960 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8634432 # Number of bytes written to this memory +system.physmem.bytes_read::total 12451228 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1152320 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 318816 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1471136 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9003520 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8651996 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 27 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 20310 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 19170 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 128671 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5329 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10295 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 9461 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 9021084 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 25 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 20252 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 19649 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 130081 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5049 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 11525 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 10791 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 193295 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 134913 # Number of write requests responded to by this memory +system.physmem.num_reads::total 197406 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 140680 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 139304 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 658 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 122 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 440366 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 454630 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 3136670 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 268 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 24 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 128298 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 250484 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 230635 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 145071 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 609 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 171 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 438913 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 466304 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 3171022 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 244 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 49 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 121435 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 280444 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 263055 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 366 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4642522 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 440366 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 128298 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 568665 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3288834 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4742611 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 438913 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 121435 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 560348 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3429396 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6675 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 15 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3295524 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3288834 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 658 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 122 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 440366 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 461305 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 3136670 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 268 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 24 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 128298 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 250500 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 230635 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3436086 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3429396 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 609 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 171 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 438913 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 472979 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 3171022 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 244 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 121435 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 280459 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 263055 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 366 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7938046 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 193296 # Number of read requests accepted -system.physmem.writeReqs 175528 # Number of write requests accepted -system.physmem.readBursts 193296 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 175528 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12362624 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8320 # Total number of bytes read from write queue -system.physmem.bytesWritten 9724800 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12188440 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10970332 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 130 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 23562 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 14506 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12287 # Per bank write bursts -system.physmem.perBankRdBursts::1 11514 # Per bank write bursts -system.physmem.perBankRdBursts::2 12472 # Per bank write bursts -system.physmem.perBankRdBursts::3 12180 # Per bank write bursts -system.physmem.perBankRdBursts::4 14590 # Per bank write bursts -system.physmem.perBankRdBursts::5 12444 # Per bank write bursts -system.physmem.perBankRdBursts::6 12518 # Per bank write bursts -system.physmem.perBankRdBursts::7 12466 # Per bank write bursts -system.physmem.perBankRdBursts::8 11679 # Per bank write bursts -system.physmem.perBankRdBursts::9 12089 # Per bank write bursts -system.physmem.perBankRdBursts::10 11915 # Per bank write bursts -system.physmem.perBankRdBursts::11 11053 # Per bank write bursts -system.physmem.perBankRdBursts::12 11299 # Per bank write bursts -system.physmem.perBankRdBursts::13 11450 # Per bank write bursts -system.physmem.perBankRdBursts::14 11880 # Per bank write bursts -system.physmem.perBankRdBursts::15 11330 # Per bank write bursts -system.physmem.perBankWrBursts::0 9713 # Per bank write bursts -system.physmem.perBankWrBursts::1 9189 # Per bank write bursts -system.physmem.perBankWrBursts::2 10054 # Per bank write bursts -system.physmem.perBankWrBursts::3 9647 # Per bank write bursts -system.physmem.perBankWrBursts::4 9435 # Per bank write bursts -system.physmem.perBankWrBursts::5 9608 # Per bank write bursts -system.physmem.perBankWrBursts::6 10036 # Per bank write bursts -system.physmem.perBankWrBursts::7 9866 # Per bank write bursts -system.physmem.perBankWrBursts::8 9192 # Per bank write bursts -system.physmem.perBankWrBursts::9 9471 # Per bank write bursts -system.physmem.perBankWrBursts::10 9539 # Per bank write bursts -system.physmem.perBankWrBursts::11 9209 # Per bank write bursts -system.physmem.perBankWrBursts::12 9294 # Per bank write bursts -system.physmem.perBankWrBursts::13 9108 # Per bank write bursts -system.physmem.perBankWrBursts::14 9699 # Per bank write bursts -system.physmem.perBankWrBursts::15 8890 # Per bank write bursts +system.physmem.bw_total::total 8178698 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 197407 # Number of read requests accepted +system.physmem.writeReqs 145071 # Number of write requests accepted +system.physmem.readBursts 197407 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 145071 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12624448 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9600 # Total number of bytes read from write queue +system.physmem.bytesWritten 9033728 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12451292 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9021084 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 150 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 50333 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 12702 # Per bank write bursts +system.physmem.perBankRdBursts::1 12398 # Per bank write bursts +system.physmem.perBankRdBursts::2 12869 # Per bank write bursts +system.physmem.perBankRdBursts::3 12803 # Per bank write bursts +system.physmem.perBankRdBursts::4 14881 # Per bank write bursts +system.physmem.perBankRdBursts::5 12147 # Per bank write bursts +system.physmem.perBankRdBursts::6 12755 # Per bank write bursts +system.physmem.perBankRdBursts::7 12276 # Per bank write bursts +system.physmem.perBankRdBursts::8 11968 # Per bank write bursts +system.physmem.perBankRdBursts::9 12044 # Per bank write bursts +system.physmem.perBankRdBursts::10 11861 # Per bank write bursts +system.physmem.perBankRdBursts::11 11195 # Per bank write bursts +system.physmem.perBankRdBursts::12 11579 # Per bank write bursts +system.physmem.perBankRdBursts::13 12354 # Per bank write bursts +system.physmem.perBankRdBursts::14 11791 # Per bank write bursts +system.physmem.perBankRdBursts::15 11634 # Per bank write bursts +system.physmem.perBankWrBursts::0 9169 # Per bank write bursts +system.physmem.perBankWrBursts::1 9145 # Per bank write bursts +system.physmem.perBankWrBursts::2 9512 # Per bank write bursts +system.physmem.perBankWrBursts::3 9193 # Per bank write bursts +system.physmem.perBankWrBursts::4 8772 # Per bank write bursts +system.physmem.perBankWrBursts::5 8759 # Per bank write bursts +system.physmem.perBankWrBursts::6 9221 # Per bank write bursts +system.physmem.perBankWrBursts::7 8821 # Per bank write bursts +system.physmem.perBankWrBursts::8 8638 # Per bank write bursts +system.physmem.perBankWrBursts::9 8679 # Per bank write bursts +system.physmem.perBankWrBursts::10 8601 # Per bank write bursts +system.physmem.perBankWrBursts::11 8338 # Per bank write bursts +system.physmem.perBankWrBursts::12 8547 # Per bank write bursts +system.physmem.perBankWrBursts::13 8875 # Per bank write bursts +system.physmem.perBankWrBursts::14 8631 # Per bank write bursts +system.physmem.perBankWrBursts::15 8251 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 46 # Number of times write queue was full causing retry -system.physmem.totGap 2625377925000 # Total gap between requests +system.physmem.numWrRetry 15 # Number of times write queue was full causing retry +system.physmem.totGap 2625394672500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 550 # Read request sizes (log2) +system.physmem.readPktSize::2 551 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) -system.physmem.readPktSize::4 3082 # Read request sizes (log2) +system.physmem.readPktSize::4 3086 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 189636 # Read request sizes (log2) +system.physmem.readPktSize::6 193742 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 171137 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 58646 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 70721 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 16311 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 12182 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8246 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7467 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 6266 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 5177 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 4683 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1253 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 923 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 715 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 309 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 259 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 140680 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 60453 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 70781 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 16881 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12152 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8838 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7520 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 6581 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 5428 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 4952 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1308 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 972 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 775 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 324 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 266 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -188,158 +188,159 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2340 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3256 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4036 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4706 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5941 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6575 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7082 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7445 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8621 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 11356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8943 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8063 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1588 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2519 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2445 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1915 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2563 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1717 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1608 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1694 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1075 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 483 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 429 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 82 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 87477 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 252.493341 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 140.519371 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 314.341475 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 45925 52.50% 52.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16983 19.41% 71.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5819 6.65% 78.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3357 3.84% 82.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2775 3.17% 85.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1460 1.67% 87.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 948 1.08% 88.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 995 1.14% 89.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9215 10.53% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 87477 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6395 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 30.205629 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 580.308341 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6393 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6395 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6395 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.760751 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.753987 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 37.694415 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 6028 94.26% 94.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 95 1.49% 95.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 28 0.44% 96.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 10 0.16% 96.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 24 0.38% 96.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 40 0.63% 97.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 30 0.47% 97.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 13 0.20% 98.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 18 0.28% 98.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 5 0.08% 98.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 23 0.36% 98.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 21 0.33% 99.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 7 0.11% 99.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 3 0.05% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 2 0.03% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 5 0.08% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 3 0.05% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 2 0.03% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 3 0.05% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 7 0.11% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 6 0.09% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 11 0.17% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 1 0.02% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 2 0.03% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 2 0.03% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 2 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 3 0.05% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::688-703 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6395 # Writes before turning the bus around for reads -system.physmem.totQLat 6824061250 # Total ticks spent queuing -system.physmem.totMemAccLat 10445923750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 965830000 # Total ticks spent in databus transfers -system.physmem.avgQLat 35327.45 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 2665 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6711 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 10182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9787 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 11207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 9191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8461 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7930 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 40 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 90794 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 238.541225 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 134.856216 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 301.373578 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 48956 53.92% 53.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17750 19.55% 73.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6013 6.62% 80.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3452 3.80% 83.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2808 3.09% 86.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1564 1.72% 88.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 893 0.98% 89.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 995 1.10% 90.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8363 9.21% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 90794 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7077 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.872686 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 551.008017 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7075 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 7077 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7077 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.945175 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.553311 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 11.579174 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5904 83.43% 83.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 368 5.20% 88.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 217 3.07% 91.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 59 0.83% 92.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 82 1.16% 93.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 159 2.25% 95.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 25 0.35% 96.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 12 0.17% 96.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 13 0.18% 96.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 11 0.16% 96.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 10 0.14% 96.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 6 0.08% 97.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 165 2.33% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 6 0.08% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 3 0.04% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 6 0.08% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 1 0.01% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 3 0.04% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 3 0.04% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 2 0.03% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.01% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.01% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.01% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 10 0.14% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 5 0.07% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7077 # Writes before turning the bus around for reads +system.physmem.totQLat 6986626052 # Total ticks spent queuing +system.physmem.totMemAccLat 10685194802 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 986285000 # Total ticks spent in databus transfers +system.physmem.avgQLat 35418.90 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 54077.45 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.71 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.70 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.64 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.18 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 54168.90 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.81 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.44 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.74 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.44 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.07 # Data bus utilization in percentage +system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.24 # Average write queue length when enqueuing -system.physmem.readRowHits 161531 # Number of row buffer hits during reads -system.physmem.writeRowHits 96107 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.62 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 63.24 # Row buffer hit rate for writes -system.physmem.avgGap 7118240.48 # Average gap between requests -system.physmem.pageHitRate 74.65 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 340124400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 185583750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 783673800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 502511040 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 171476769360 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 74898468540 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1509525073500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1757712204390 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.508799 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2511124862587 # Time in different power states -system.physmem_0.memoryStateTime::REF 87667060000 # Time in different power states +system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.34 # Average write queue length when enqueuing +system.physmem.readRowHits 164764 # Number of row buffer hits during reads +system.physmem.writeRowHits 82850 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.53 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 58.69 # Row buffer hit rate for writes +system.physmem.avgGap 7665878.31 # Average gap between requests +system.physmem.pageHitRate 73.17 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 357081480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 194836125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 802081800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 470396160 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 171477786480 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 75099546585 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1509358032750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1757759761380 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.522942 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2510844795677 # Time in different power states +system.physmem_0.memoryStateTime::REF 87667580000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 26583898663 # Time in different power states +system.physmem_0.memoryStateTime::ACT 26879018073 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 321201720 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 175258875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 723013200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 482124960 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 171476769360 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 74441693340 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1509925753500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1757545814955 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.445422 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2511799542258 # Time in different power states -system.physmem_1.memoryStateTime::REF 87667060000 # Time in different power states +system.physmem_1.actEnergy 329321160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 179689125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 736515000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 444268800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 171477786480 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 74435410800 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1509940608000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1757543599365 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.440607 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2511823665901 # Time in different power states +system.physmem_1.memoryStateTime::REF 87667580000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 25911565742 # Time in different power states +system.physmem_1.memoryStateTime::ACT 25903669599 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 128 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 192 # Number of bytes read from this memory @@ -365,15 +366,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 22612465 # Number of BP lookups -system.cpu0.branchPred.condPredicted 14651481 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 907853 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 13732961 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 10133003 # Number of BTB hits +system.cpu0.branchPred.lookups 51763361 # Number of BP lookups +system.cpu0.branchPred.condPredicted 23412597 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 921572 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 31250401 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 23297364 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 73.786003 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 3723828 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 29274 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 74.550608 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 15315613 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 29376 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -404,80 +405,80 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 61748 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 61748 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 23984 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18764 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 19000 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 42748 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 436.289417 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 2694.039371 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-8191 41732 97.62% 97.62% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::8192-16383 726 1.70% 99.32% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::16384-24575 177 0.41% 99.74% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::24576-32767 77 0.18% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::32768-40959 11 0.03% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::40960-49151 19 0.04% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::49152-57343 4 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::57344-65535 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::98304-106495 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 42748 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 15024 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 8664.869276 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 7136.607726 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 7119.581025 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 14229 94.71% 94.71% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 745 4.96% 99.67% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 26 0.17% 99.84% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-98303 4 0.03% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-114687 3 0.02% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-147455 16 0.11% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 15024 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 87051634064 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.443285 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.503059 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 87007241564 99.95% 99.95% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 33256500 0.04% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 5843000 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 2996500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 874000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 581000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 581000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 249500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 11000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 87051634064 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5088 77.48% 77.48% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1479 22.52% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6567 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 61748 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 63347 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 63347 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 24259 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18763 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 20325 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 43022 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 472.792990 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 2838.942862 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-8191 41882 97.35% 97.35% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::8192-16383 877 2.04% 99.39% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::16384-24575 115 0.27% 99.66% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::24576-32767 113 0.26% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::32768-40959 6 0.01% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::40960-49151 23 0.05% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::49152-57343 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::57344-65535 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-73727 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 43022 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 16160 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 9833.168317 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 8304.443400 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 6846.428458 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 15169 93.87% 93.87% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 911 5.64% 99.50% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 54 0.33% 99.84% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::49152-65535 3 0.02% 99.86% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 2 0.01% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-114687 20 0.12% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 16160 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 95658285656 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.461466 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.505385 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 95607533656 99.95% 99.95% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 37952000 0.04% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 6012000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 3722000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 1321500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 760000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 604000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 360500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 20000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 95658285656 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 5176 77.00% 77.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1546 23.00% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6722 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 63347 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 61748 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6567 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 63347 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6722 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6567 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 68315 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6722 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 70069 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 16748968 # DTB read hits -system.cpu0.dtb.read_misses 52995 # DTB read misses -system.cpu0.dtb.write_hits 13907664 # DTB write hits -system.cpu0.dtb.write_misses 8753 # DTB write misses +system.cpu0.dtb.read_hits 22737235 # DTB read hits +system.cpu0.dtb.read_misses 54172 # DTB read misses +system.cpu0.dtb.write_hits 16921500 # DTB write hits +system.cpu0.dtb.write_misses 9175 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3489 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 88 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 2047 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3524 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 141 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1882 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 843 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 16801963 # DTB read accesses -system.cpu0.dtb.write_accesses 13916417 # DTB write accesses +system.cpu0.dtb.perms_faults 854 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 22791407 # DTB read accesses +system.cpu0.dtb.write_accesses 16930675 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 30656632 # DTB hits -system.cpu0.dtb.misses 61748 # DTB misses -system.cpu0.dtb.accesses 30718380 # DTB accesses +system.cpu0.dtb.hits 39658735 # DTB hits +system.cpu0.dtb.misses 63347 # DTB misses +system.cpu0.dtb.accesses 39722082 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -507,56 +508,62 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 9874 # Table walker walks requested -system.cpu0.itb.walker.walksShort 9874 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3715 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6056 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 103 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 9771 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 366.390339 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 1951.164851 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-4095 9421 96.42% 96.42% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::4096-8191 224 2.29% 98.71% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::8192-12287 80 0.82% 99.53% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::12288-16383 17 0.17% 99.70% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::16384-20479 13 0.13% 99.84% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::20480-24575 5 0.05% 99.89% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::24576-28671 4 0.04% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::28672-32767 6 0.06% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-36863 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 9771 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2691 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 9965.812709 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 8554.132900 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 5681.325139 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 1024 38.05% 38.05% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1554 57.75% 95.80% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 43 1.60% 97.40% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 63 2.34% 99.74% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 4 0.15% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::40960-49151 2 0.07% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2691 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 18106130328 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.976227 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.152552 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 430953000 2.38% 2.38% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 17674714828 97.62% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 401500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 61000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 18106130328 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2271 87.75% 87.75% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 317 12.25% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walks 10275 # Table walker walks requested +system.cpu0.itb.walker.walksShort 10275 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 4076 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6085 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 114 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 10161 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 480.267690 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 2390.213266 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-4095 9738 95.84% 95.84% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::4096-8191 133 1.31% 97.15% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::8192-12287 215 2.12% 99.26% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::12288-16383 37 0.36% 99.63% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::16384-20479 9 0.09% 99.71% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::20480-24575 15 0.15% 99.86% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::24576-28671 3 0.03% 99.89% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::28672-32767 3 0.03% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-36863 2 0.02% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::36864-40959 4 0.04% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::40960-45055 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::45056-49151 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 10161 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2702 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 11438.934123 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 10140.740913 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 6204.580963 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 871 32.24% 32.24% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1681 62.21% 94.45% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 53 1.96% 96.41% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 85 3.15% 99.56% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 7 0.26% 99.81% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.04% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-106495 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2702 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 22643799124 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.979659 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.141451 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 461404000 2.04% 2.04% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 22181693124 97.96% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 593000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 109000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 22643799124 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 2268 87.64% 87.64% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 320 12.36% 100.00% # Table walker page sizes translated system.cpu0.itb.walker.walkPageSizes::total 2588 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 9874 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 9874 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10275 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10275 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2588 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2588 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 12462 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 35678798 # ITB inst hits -system.cpu0.itb.inst_misses 9874 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin::total 12863 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 70928349 # ITB inst hits +system.cpu0.itb.inst_misses 10275 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -565,1020 +572,1041 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2368 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2365 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1932 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1936 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 35688672 # ITB inst accesses -system.cpu0.itb.hits 35678798 # DTB hits -system.cpu0.itb.misses 9874 # DTB misses -system.cpu0.itb.accesses 35688672 # DTB accesses -system.cpu0.numCycles 121733824 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 70938624 # ITB inst accesses +system.cpu0.itb.hits 70928349 # DTB hits +system.cpu0.itb.misses 10275 # DTB misses +system.cpu0.itb.accesses 70938624 # DTB accesses +system.cpu0.numCycles 192976868 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 17621783 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 106366119 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 22612465 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 13856831 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 98711813 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2650530 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 130938 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 54154 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 345087 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 416739 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 73296 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 35679429 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 256075 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 4180 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 118679075 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.081251 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.263308 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 19363908 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 190332929 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 51763361 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 38612977 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 166709106 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 5608958 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 145099 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 54692 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 348676 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 420281 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 85262 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 70928958 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 257958 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 4691 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 189931503 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.225932 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.310916 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 59721044 50.32% 50.32% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 20146281 16.98% 67.30% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 8259650 6.96% 74.26% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 30552100 25.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 88125904 46.40% 46.40% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 29232702 15.39% 61.79% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 14108338 7.43% 69.22% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 58464559 30.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 118679075 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.185753 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.873760 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 18470879 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 55646585 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 38814384 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 4744194 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1003033 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 2910392 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 326287 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 104430369 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 3709386 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1003033 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 23916141 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 11897059 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 33727750 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 37986661 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 10148431 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 99624170 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 979348 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 1380369 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 148421 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 51935 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 6127142 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 103189966 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 455330287 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 114159594 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 9381 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 92428419 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 10761544 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1188796 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 1051388 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 11830283 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 17680232 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 15386939 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1636462 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 2175060 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 96814528 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1636038 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 95024919 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 451413 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 8911325 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 20849804 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 116309 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 118679075 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.800688 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.033122 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 189931503 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.268236 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.986299 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 24608865 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 101406874 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 56677604 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 4757932 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 2480228 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 2944179 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 328448 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 148845488 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 3759445 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 2480228 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 33020653 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 11928133 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 79389996 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 52895431 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 10217062 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 132354164 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 1007004 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 1382043 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 149840 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 52195 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 6188026 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 135879963 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 611395498 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 146969281 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 9373 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 124973310 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 10906650 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 2656416 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 2518561 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 22027855 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 23660512 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 18424443 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1639164 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 2432445 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 129487187 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1661777 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 127665829 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 454854 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10484678 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 21309646 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 116701 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 189931503 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.672168 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 0.963951 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 65546472 55.23% 55.23% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 22156727 18.67% 73.90% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 21116341 17.79% 91.69% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 8802658 7.42% 99.11% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1056849 0.89% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 28 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 116041258 61.10% 61.10% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 32572628 17.15% 78.25% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 29941917 15.76% 94.01% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 10293469 5.42% 99.43% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1082195 0.57% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 36 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 118679075 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 189931503 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 8808229 40.49% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 130 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 5336848 24.53% 65.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 7610455 34.98% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 10298963 43.90% 43.90% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 129 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 5415712 23.09% 66.99% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 7742693 33.01% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 2272 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 62565826 65.84% 65.84% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 87588 0.09% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 7159 0.01% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 17417081 18.33% 84.27% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 14944992 15.73% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 86175456 67.50% 67.50% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 106512 0.08% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 7179 0.01% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 23410232 18.34% 85.93% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 17964178 14.07% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 95024919 # Type of FU issued -system.cpu0.iq.rate 0.780596 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 21755662 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.228947 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 330903688 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 107369307 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 93061278 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 32300 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 11278 # Number of floating instruction queue writes +system.cpu0.iq.FU_type_0::total 127665829 # Type of FU issued +system.cpu0.iq.rate 0.661560 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 23457497 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.183741 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 469142790 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 141641253 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 124187141 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 32722 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 11272 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 9724 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 116757282 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 21027 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 347087 # Number of loads that had data forwarded from stores +system.cpu0.iq.int_alu_accesses 151099696 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 21358 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 349091 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1857425 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2513 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 18755 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 953252 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1883461 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2555 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 18950 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 972383 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 101364 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 327888 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 113459 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 340118 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1003033 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 1539075 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 172884 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 98621711 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 2480228 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 1536268 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 176000 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 131320075 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 17680232 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 15386939 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 849096 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 24467 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 126834 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 18755 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 265533 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 373430 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 638963 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 94008948 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 16992930 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 954343 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 23660512 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 18424443 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 851631 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 24928 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 129599 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 18950 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 275041 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 375413 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 650454 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 126634007 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 22982824 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 968597 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 171145 # number of nop insts executed -system.cpu0.iew.exec_refs 31760151 # number of memory reference insts executed -system.cpu0.iew.exec_branches 15805524 # Number of branches executed -system.cpu0.iew.exec_stores 14767221 # Number of stores executed -system.cpu0.iew.exec_rate 0.772250 # Inst execution rate -system.cpu0.iew.wb_sent 93501427 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 93071002 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 48393961 # num instructions producing a value -system.cpu0.iew.wb_consumers 79995949 # num instructions consuming a value +system.cpu0.iew.exec_nop 171111 # number of nop insts executed +system.cpu0.iew.exec_refs 40767921 # number of memory reference insts executed +system.cpu0.iew.exec_branches 24572908 # Number of branches executed +system.cpu0.iew.exec_stores 17785097 # Number of stores executed +system.cpu0.iew.exec_rate 0.656213 # Inst execution rate +system.cpu0.iew.wb_sent 126104266 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 124196865 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 63208416 # num instructions producing a value +system.cpu0.iew.wb_consumers 102222094 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.764545 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.604955 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.643584 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.618344 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 7948634 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 1519729 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 585621 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 117035605 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.766100 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.480781 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 9488534 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 1545076 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 597321 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 186809549 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.646573 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.344397 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 75174289 64.23% 64.23% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 23319780 19.93% 84.16% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 7849886 6.71% 90.86% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 3044520 2.60% 93.47% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 3180912 2.72% 96.18% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 1406827 1.20% 97.39% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 1102407 0.94% 98.33% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 520278 0.44% 98.77% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1436706 1.23% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 128903317 69.00% 69.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 31993486 17.13% 86.13% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 12242174 6.55% 92.68% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 3077822 1.65% 94.33% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 4650551 2.49% 96.82% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 2601023 1.39% 98.21% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 1367878 0.73% 98.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 526295 0.28% 99.23% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1447003 0.77% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 117035605 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 74499569 # Number of instructions committed -system.cpu0.commit.committedOps 89660931 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 186809549 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 99693903 # Number of instructions committed +system.cpu0.commit.committedOps 120785976 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 30256494 # Number of memory references committed -system.cpu0.commit.loads 15822807 # Number of loads committed -system.cpu0.commit.membars 627513 # Number of memory barriers committed -system.cpu0.commit.branches 15208996 # Number of branches committed +system.cpu0.commit.refs 39229111 # Number of memory references committed +system.cpu0.commit.loads 21777051 # Number of loads committed +system.cpu0.commit.membars 629182 # Number of memory barriers committed +system.cpu0.commit.branches 23976855 # Number of branches committed system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 77458658 # Number of committed integer instructions. -system.cpu0.commit.function_calls 1847857 # Number of function calls committed. +system.cpu0.commit.int_insts 105625598 # Number of committed integer instructions. +system.cpu0.commit.function_calls 4749745 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 59311896 66.15% 66.15% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 85382 0.10% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 7159 0.01% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 15822807 17.65% 83.90% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 14433687 16.10% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 81445291 67.43% 67.43% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 104395 0.09% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 7179 0.01% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 21777051 18.03% 85.55% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 17452060 14.45% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 89660931 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1436706 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 209187674 # The number of ROB reads -system.cpu0.rob.rob_writes 196861250 # The number of ROB writes -system.cpu0.timesIdled 121559 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 3054749 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5129022957 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 74377875 # Number of Instructions Simulated -system.cpu0.committedOps 89539237 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.636694 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.636694 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.610988 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.610988 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 104549028 # number of integer regfile reads -system.cpu0.int_regfile_writes 56469550 # number of integer regfile writes -system.cpu0.fp_regfile_reads 8161 # number of floating regfile reads +system.cpu0.commit.op_class_0::total 120785976 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1447003 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 292572702 # The number of ROB reads +system.cpu0.rob.rob_writes 263669539 # The number of ROB writes +system.cpu0.timesIdled 123127 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 3045365 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5057813082 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 99572209 # Number of Instructions Simulated +system.cpu0.committedOps 120664282 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.938060 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.938060 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.515980 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.515980 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 137228019 # number of integer regfile reads +system.cpu0.int_regfile_writes 78727155 # number of integer regfile writes +system.cpu0.fp_regfile_reads 8192 # number of floating regfile reads system.cpu0.fp_regfile_writes 2264 # number of floating regfile writes -system.cpu0.cc_regfile_reads 331224109 # number of cc regfile reads -system.cpu0.cc_regfile_writes 38421528 # number of cc regfile writes -system.cpu0.misc_regfile_reads 166953922 # number of misc regfile reads -system.cpu0.misc_regfile_writes 1191250 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 674914 # number of replacements -system.cpu0.dcache.tags.tagsinuse 486.328727 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 27281228 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 675426 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 40.391143 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 277646000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 486.328727 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.949861 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.949861 # Average percentage of cache occupancy +system.cpu0.cc_regfile_reads 446969794 # number of cc regfile reads +system.cpu0.cc_regfile_writes 47254034 # number of cc regfile writes +system.cpu0.misc_regfile_reads 263157526 # number of misc regfile reads +system.cpu0.misc_regfile_writes 1194331 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 673421 # number of replacements +system.cpu0.dcache.tags.tagsinuse 483.801587 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 36230548 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 673933 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 53.759866 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 274448500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 483.801587 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.944925 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.944925 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 300 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 180 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 310 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 60112887 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 60112887 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 14700771 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 14700771 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 11392924 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 11392924 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 295732 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 295732 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 354072 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 354072 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 350987 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 350987 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 26093695 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 26093695 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 26389427 # number of overall hits -system.cpu0.dcache.overall_hits::total 26389427 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 607182 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 607182 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1803068 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1803068 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 141599 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 141599 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 24346 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 24346 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21181 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 21181 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2410250 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2410250 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2551849 # number of overall misses -system.cpu0.dcache.overall_misses::total 2551849 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8154354688 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 8154354688 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 26135736531 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 26135736531 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 384171142 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 384171142 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 484170513 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 484170513 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 824000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 824000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 34290091219 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 34290091219 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 34290091219 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 34290091219 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 15307953 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 15307953 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 13195992 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 13195992 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 437331 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 437331 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 378418 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 378418 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 372168 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 372168 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 28503945 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 28503945 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 28941276 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 28941276 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039664 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.039664 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.136638 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.136638 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.323780 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.323780 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064336 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064336 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056912 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056912 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.084558 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.084558 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.088173 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.088173 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13429.836010 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13429.836010 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14495.147455 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 14495.147455 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15779.641091 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15779.641091 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22858.718332 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22858.718332 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 78023145 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 78023145 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 20647656 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 20647656 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 14394101 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 14394101 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 296444 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 296444 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 354739 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 354739 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 351671 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 351671 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 35041757 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 35041757 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 35338201 # number of overall hits +system.cpu0.dcache.overall_hits::total 35338201 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 609728 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 609728 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1806132 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1806132 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 141710 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 141710 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 24359 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 24359 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21165 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 21165 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 2415860 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2415860 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 2557570 # number of overall misses +system.cpu0.dcache.overall_misses::total 2557570 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8120126000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 8120126000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 26313440366 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 26313440366 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 385463000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 385463000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 480627500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 480627500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 430000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 430000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 34433566366 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 34433566366 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 34433566366 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 34433566366 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 21257384 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 21257384 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 16200233 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 16200233 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 438154 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 438154 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 379098 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 379098 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 372836 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 372836 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 37457617 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 37457617 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 37895771 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 37895771 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028683 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.028683 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.111488 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.111488 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.323425 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.323425 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064255 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064255 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056768 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056768 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.064496 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.064496 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.067490 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.067490 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13317.620316 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13317.620316 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14568.946437 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 14568.946437 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15824.253869 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15824.253869 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22708.599102 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22708.599102 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14226.777811 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 14226.777811 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13437.351199 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 13437.351199 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 781 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 3670700 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 43 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 191761 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 18.162791 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 19.142057 # average number of cycles each access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14253.129886 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 14253.129886 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13463.391565 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 13463.391565 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 747 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 3913122 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 47 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 192454 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.893617 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 20.332765 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 492000 # number of writebacks -system.cpu0.dcache.writebacks::total 492000 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 239081 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 239081 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1490741 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1490741 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18153 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18153 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1729822 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1729822 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1729822 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1729822 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 368101 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 368101 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 312327 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 312327 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 98325 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 98325 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6193 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6193 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21181 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 21181 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 680428 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 680428 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 778753 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 778753 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 17965 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 17965 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16714 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 16714 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 34679 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 34679 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4128121038 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4128121038 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5207818329 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5207818329 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1570971031 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1570971031 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 91940502 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 91940502 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 451443987 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 451443987 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 794000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 794000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9335939367 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9335939367 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10906910398 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10906910398 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3693380750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3693380750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2688166013 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2688166013 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6381546763 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6381546763 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024046 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024046 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023668 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023668 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224830 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224830 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016366 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016366 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056912 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056912 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023871 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.023871 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026908 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.026908 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11214.642280 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11214.642280 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16674.249517 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16674.249517 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15977.330598 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15977.330598 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14845.874697 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14845.874697 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21313.629526 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21313.629526 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 491417 # number of writebacks +system.cpu0.dcache.writebacks::total 491417 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 243049 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 243049 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1494093 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1494093 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18165 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18165 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1737142 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1737142 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1737142 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1737142 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 366679 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 366679 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 312039 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 312039 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 98387 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 98387 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6194 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6194 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21165 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 21165 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 678718 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 678718 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 777105 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 777105 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 29394 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 29394 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 26127 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 26127 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 55521 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 55521 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4291687500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4291687500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5394914387 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5394914387 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1614083000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1614083000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 96183500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 96183500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 459474500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 459474500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 418000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 418000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9686601887 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9686601887 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11300684887 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11300684887 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5681056500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5681056500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4312326500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4312326500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 9993383000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 9993383000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017249 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017249 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019261 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019261 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224549 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224549 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016339 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016339 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056768 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056768 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018120 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.018120 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020506 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.020506 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11704.208586 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11704.208586 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17289.231112 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17289.231112 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16405.449907 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16405.449907 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15528.495318 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15528.495318 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21709.166076 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21709.166076 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13720.686637 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13720.686637 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14005.609478 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14005.609478 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 205587.573059 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 205587.573059 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 160833.194508 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 160833.194508 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 184017.611898 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184017.611898 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14271.909522 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14271.909522 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14542.030854 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14542.030854 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 193272.657685 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 193272.657685 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165052.493589 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 165052.493589 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 179992.849552 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 179992.849552 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1200530 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.748320 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 34431245 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1201042 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 28.667811 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6414143250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.748320 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999508 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999508 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 1208444 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.748718 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 69666115 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1208956 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 57.625021 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6421480000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.748718 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999509 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999509 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 148 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 147 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 72552920 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 72552920 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 34431245 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 34431245 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 34431245 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 34431245 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 34431245 # number of overall hits -system.cpu0.icache.overall_hits::total 34431245 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1244682 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1244682 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1244682 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1244682 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1244682 # number of overall misses -system.cpu0.icache.overall_misses::total 1244682 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12221339030 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 12221339030 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 12221339030 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 12221339030 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 12221339030 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 12221339030 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 35675927 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 35675927 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 35675927 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 35675927 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 35675927 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 35675927 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.034889 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.034889 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.034889 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.034889 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.034889 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.034889 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9818.844516 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9818.844516 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9818.844516 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9818.844516 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9818.844516 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9818.844516 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1349229 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 432 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 105227 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 12.822080 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 39.272727 # average number of cycles each access was blocked +system.cpu0.icache.tags.tag_accesses 143059850 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 143059850 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 69666115 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 69666115 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 69666115 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 69666115 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 69666115 # number of overall hits +system.cpu0.icache.overall_hits::total 69666115 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1259322 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1259322 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1259322 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1259322 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1259322 # number of overall misses +system.cpu0.icache.overall_misses::total 1259322 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12306647041 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 12306647041 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 12306647041 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 12306647041 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 12306647041 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 12306647041 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 70925437 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 70925437 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 70925437 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 70925437 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 70925437 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 70925437 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.017756 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.017756 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.017756 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.017756 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.017756 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.017756 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9772.438694 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9772.438694 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9772.438694 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9772.438694 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9772.438694 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9772.438694 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1459740 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 453 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 110714 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 10 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.184782 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 45.300000 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43614 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 43614 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 43614 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 43614 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 43614 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 43614 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1201068 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1201068 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1201068 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1201068 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1201068 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1201068 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3002 # number of ReadReq MSHR uncacheable -system.cpu0.icache.ReadReq_mshr_uncacheable::total 3002 # number of ReadReq MSHR uncacheable -system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3002 # number of overall MSHR uncacheable misses -system.cpu0.icache.overall_mshr_uncacheable_misses::total 3002 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10504795288 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10504795288 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10504795288 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10504795288 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10504795288 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10504795288 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 265434748 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 265434748 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 265434748 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 265434748 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033666 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033666 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033666 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.033666 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033666 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.033666 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8746.211945 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8746.211945 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8746.211945 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 8746.211945 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8746.211945 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 8746.211945 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88419.303131 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88419.303131 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88419.303131 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88419.303131 # average overall mshr uncacheable latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 50344 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 50344 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 50344 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 50344 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 50344 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 50344 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1208978 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1208978 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1208978 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1208978 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1208978 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1208978 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3004 # number of ReadReq MSHR uncacheable +system.cpu0.icache.ReadReq_mshr_uncacheable::total 3004 # number of ReadReq MSHR uncacheable +system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3004 # number of overall MSHR uncacheable misses +system.cpu0.icache.overall_mshr_uncacheable_misses::total 3004 # number of overall MSHR uncacheable misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11179466333 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11179466333 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11179466333 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11179466333 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11179466333 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11179466333 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 265874998 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 265874998 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 265874998 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 265874998 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.017046 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017046 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.017046 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.017046 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.017046 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.017046 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9247.038683 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9247.038683 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9247.038683 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 9247.038683 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9247.038683 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9247.038683 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88506.990013 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88506.990013 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88506.990013 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88506.990013 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1764126 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1768652 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 4013 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1763942 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1769107 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 4567 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 220332 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 264213 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16022.712569 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 2093032 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 280442 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 7.463333 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 220637 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 266650 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16052.098762 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 3449668 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 282876 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 12.194983 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 9357.549400 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 12.830885 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.990255 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 3887.194071 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1642.708300 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1121.439658 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.571139 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000783 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000060 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.237255 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.100263 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.068447 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.977949 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1027 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15194 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 39 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 304 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 426 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 258 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 450 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4677 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7327 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2684 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.062683 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.927368 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 41624222 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 41624222 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 49855 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 11685 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1152127 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 374018 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 1587685 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 491993 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 491993 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28477 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 28477 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1602 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 1602 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 210193 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 210193 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 49855 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 11685 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1152127 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 584211 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1797878 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 49855 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 11685 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1152127 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 584211 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1797878 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 397 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 143 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 48926 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 98504 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 147970 # number of ReadReq misses -system.cpu0.l2cache.Writeback_misses::writebacks 2 # number of Writeback misses -system.cpu0.l2cache.Writeback_misses::total 2 # number of Writeback misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 27483 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 27483 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19577 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 19577 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 46426 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 46426 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 397 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 143 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 48926 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 144930 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 194396 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 397 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 143 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 48926 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 144930 # number of overall misses -system.cpu0.l2cache.overall_misses::total 194396 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 10907493 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3478500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 2401346947 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2853426397 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 5269159337 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 505786782 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 505786782 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 394596383 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 394596383 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 773499 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 773499 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2617489063 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 2617489063 # number of ReadExReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 10907493 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3478500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2401346947 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 5470915460 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 7886648400 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 10907493 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3478500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2401346947 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 5470915460 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 7886648400 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 50252 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 11828 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1201053 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 472522 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 1735655 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 491995 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 491995 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55960 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 55960 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 21179 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 21179 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 256619 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 256619 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 50252 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 11828 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 1201053 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 729141 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 1992274 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 50252 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 11828 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 1201053 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 729141 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 1992274 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.007900 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.012090 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.040736 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.208464 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.085253 # miss rate for ReadReq accesses -system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000004 # miss rate for Writeback accesses -system.cpu0.l2cache.Writeback_miss_rate::total 0.000004 # miss rate for Writeback accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.491119 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.491119 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.924359 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.924359 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.tags.occ_blocks::writebacks 9287.877050 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 13.757624 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.215297 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4106.053527 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1602.376504 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1041.818760 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.566887 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000840 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000013 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.250614 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.097801 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.063588 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.979742 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1056 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 12 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15158 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 44 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 321 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 415 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 276 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 6 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 414 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4651 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7186 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2852 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.064453 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000732 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.925171 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 63497786 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 63497786 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 50315 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 12479 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 62794 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 491416 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 491416 # number of Writeback hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28453 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 28453 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1608 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 1608 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 210730 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 210730 # number of ReadExReq hits +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1158323 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadCleanReq_hits::total 1158323 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 372689 # number of ReadSharedReq hits +system.cpu0.l2cache.ReadSharedReq_hits::total 372689 # number of ReadSharedReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 50315 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 12479 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1158323 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 583419 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 1804536 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 50315 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 12479 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1158323 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 583419 # number of overall hits +system.cpu0.l2cache.overall_hits::total 1804536 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 419 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 174 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 593 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 27292 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 27292 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19556 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 19556 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 45826 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 45826 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 50641 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 50641 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 98477 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 98477 # number of ReadSharedReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 419 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 174 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 50641 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 144303 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 195537 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 419 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 174 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 50641 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 144303 # number of overall misses +system.cpu0.l2cache.overall_misses::total 195537 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 11008500 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4405500 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 15414000 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 502449500 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 502449500 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 396768500 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 396768500 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 399000 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 399000 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2648910998 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 2648910998 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2424883999 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2424883999 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2835688998 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2835688998 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 11008500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4405500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2424883999 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 5484599996 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 7924897995 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 11008500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4405500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2424883999 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 5484599996 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 7924897995 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 50734 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 12653 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 63387 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 491416 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 491416 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55745 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 55745 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 21164 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 21164 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 256556 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 256556 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1208964 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::total 1208964 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 471166 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::total 471166 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 50734 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 12653 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 1208964 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 727722 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 2000073 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 50734 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 12653 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 1208964 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 727722 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 2000073 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.008259 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.013752 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.009355 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.489587 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.489587 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.924022 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.924022 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.180914 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.180914 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.007900 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.012090 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040736 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.198768 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.097575 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.007900 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.012090 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040736 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.198768 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.097575 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 27474.793451 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24325.174825 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 49081.203184 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 28967.619559 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 35609.646124 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18403.623404 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18403.623404 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20156.121112 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20156.121112 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 386749.500000 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 386749.500000 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 56379.810085 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 56379.810085 # average ReadExReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 27474.793451 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24325.174825 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 49081.203184 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 37748.674947 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 40570.013786 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 27474.793451 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24325.174825 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 49081.203184 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 37748.674947 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 40570.013786 # average overall miss latency -system.cpu0.l2cache.blocked_cycles::no_mshrs 227 # number of cycles access was blocked +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.178620 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.178620 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.041888 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.041888 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.209007 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.209007 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.008259 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.013752 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.041888 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.198294 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.097765 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.008259 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.013752 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.041888 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.198294 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.097765 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26273.269690 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 25318.965517 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 25993.254637 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18410.138502 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18410.138502 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20288.837186 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20288.837186 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 399000 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 399000 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 57803.670362 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 57803.670362 # average ReadExReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 47883.809542 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 47883.809542 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 28795.444601 # average ReadSharedReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 28795.444601 # average ReadSharedReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26273.269690 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 25318.965517 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 47883.809542 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 38007.525803 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 40528.892205 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 26273.269690 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 25318.965517 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 47883.809542 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 38007.525803 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 40528.892205 # average overall miss latency +system.cpu0.l2cache.blocked_cycles::no_mshrs 236 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.blocked::no_mshrs 7 # number of cycles access was blocked +system.cpu0.l2cache.blocked::no_mshrs 8 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 32.428571 # average number of cycles each access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 29.500000 # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 192333 # number of writebacks -system.cpu0.l2cache.writebacks::total 192333 # number of writebacks +system.cpu0.l2cache.writebacks::writebacks 193260 # number of writebacks +system.cpu0.l2cache.writebacks::total 193260 # number of writebacks system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 30 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 734 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::total 766 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5918 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 5918 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 6054 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 6054 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 30 # number of ReadCleanReq MSHR hits +system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 30 # number of ReadCleanReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 713 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 713 # number of ReadSharedReq MSHR hits system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 # number of demand (read+write) MSHR hits system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 30 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6652 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 6684 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6767 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 6799 # number of demand (read+write) MSHR hits system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 # number of overall MSHR hits system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 30 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6652 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 6684 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 396 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 142 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 48896 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 97770 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 147204 # number of ReadReq MSHR misses -system.cpu0.l2cache.Writeback_mshr_misses::writebacks 2 # number of Writeback MSHR misses -system.cpu0.l2cache.Writeback_mshr_misses::total 2 # number of Writeback MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 231819 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 231819 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 27483 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 27483 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19577 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19577 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 2 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 40508 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 40508 # number of ReadExReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 396 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 142 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 48896 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 138278 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 187712 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 396 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 142 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 48896 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 138278 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 231819 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 419531 # number of overall MSHR misses -system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3002 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 17965 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 20967 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 16714 # number of WriteReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 16714 # number of WriteReq MSHR uncacheable -system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3002 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 34679 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 37681 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 8304499 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2542000 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2076482303 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 2175990950 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 4263319752 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 15030655008 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 15030655008 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 535907154 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 535907154 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 292472580 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 292472580 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 643499 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 643499 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1596975176 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1596975176 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 8304499 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2542000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2076482303 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3772966126 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 5860294928 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 8304499 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2542000 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2076482303 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3772966126 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 15030655008 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 20890949936 # number of overall MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 241524750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 3549350250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 3790875000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2559965955 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2559965955 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 241524750 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6109316205 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6350840955 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.007880 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.012005 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.040711 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.206911 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.084812 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000004 # mshr miss rate for Writeback accesses -system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000004 # mshr miss rate for Writeback accesses +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6767 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 6799 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 418 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 173 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 591 # number of ReadReq MSHR misses +system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 8374 # number of CleanEvict MSHR misses +system.cpu0.l2cache.CleanEvict_mshr_misses::total 8374 # number of CleanEvict MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 232540 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 232540 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 27292 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 27292 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19556 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19556 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 1 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 39772 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 39772 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 50611 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 50611 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 97764 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 97764 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 418 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 173 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 50611 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 137536 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 188738 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 418 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 173 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 50611 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 137536 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 232540 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 421278 # number of overall MSHR misses +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3004 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 29394 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 32398 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 26127 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 26127 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3004 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 55521 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 58525 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 8479500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3355000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 11834500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 15228773142 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 15228773142 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 539452500 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 539452500 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 299483497 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 299483497 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 327000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 327000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1648200500 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1648200500 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 2120543999 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2120543999 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2210587998 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2210587998 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 8479500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3355000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2120543999 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3858788498 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 5991166997 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 8479500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3355000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2120543999 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3858788498 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 15228773142 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 21219940139 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 243342000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5445807000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5689149000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 4113464958 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4113464958 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 243342000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 9559271958 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 9802613958 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.008239 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.013673 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.009324 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.491119 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.491119 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.924359 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.924359 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.489587 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.489587 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.924022 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.924022 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.157853 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.157853 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.007880 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.012005 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.040711 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.189645 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.094220 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.007880 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.012005 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.040711 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.189645 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.155023 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.155023 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.041863 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.041863 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.207494 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.207494 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.008239 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.013673 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.041863 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.188995 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.094366 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.008239 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.013673 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.041863 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.188995 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.210579 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20970.957071 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17901.408451 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42467.324587 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22256.223279 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28961.983044 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 64837.890803 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 64837.890803 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19499.587163 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19499.587163 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14939.601573 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14939.601573 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 321749.500000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 321749.500000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39423.698430 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39423.698430 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20970.957071 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17901.408451 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 42467.324587 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27285.368070 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31219.607313 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20970.957071 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17901.408451 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 42467.324587 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27285.368070 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 64837.890803 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 49795.962482 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80454.613591 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197570.289452 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 180801.974531 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 153162.974453 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 153162.974453 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80454.613591 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 176167.600133 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 168542.261485 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.210631 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20285.885167 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 19393.063584 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20024.534687 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65488.832640 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 65488.832640 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19765.957057 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19765.957057 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15314.148957 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15314.148957 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 327000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 327000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41441.227497 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41441.227497 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 41898.875719 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 41898.875719 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 22611.472505 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 22611.472505 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20285.885167 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 19393.063584 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 41898.875719 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28056.570629 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31743.300220 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20285.885167 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 19393.063584 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 41898.875719 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28056.570629 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65488.832640 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 50370.397075 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81005.992011 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185269.340682 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 175601.858139 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 157441.151223 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157441.151223 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81005.992011 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 172173.987464 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 167494.471730 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 1907833 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1820754 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 31055 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 16714 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 491995 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 299768 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36263 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 92116 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43624 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 114864 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 16 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 34 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 284068 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 270286 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2408123 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2274201 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 27655 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 111764 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 4821743 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 76915296 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 82255660 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 47312 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 201008 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 159419276 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 687931 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 3186793 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 1.203876 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.402878 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 116134 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1839025 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 31035 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 26127 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 864426 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 1492254 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 304971 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 91775 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43512 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 114568 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 284553 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 270414 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1208978 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 592867 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3608808 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2486821 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 28899 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 112519 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 6237047 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 77421632 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 82196692 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 50612 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 202936 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 159871872 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 1179844 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 5097277 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 1.224281 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.417108 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 2537081 79.61% 79.61% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 649712 20.39% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 3954053 77.57% 77.57% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 1143224 22.43% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 3186793 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 1807599924 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 5097277 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 2520550941 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 112679999 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 112317000 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1808718407 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1816757420 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1166698241 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1173564387 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 15837483 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 16253983 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 61547958 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 61816936 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 35319894 # Number of BP lookups -system.cpu1.branchPred.condPredicted 12619407 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 374072 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 19615876 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 15617711 # Number of BTB hits +system.cpu1.branchPred.lookups 6152669 # Number of BP lookups +system.cpu1.branchPred.condPredicted 3868120 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 360109 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 3337115 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 2452438 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 79.617709 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 12648833 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 10709 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 73.489766 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 1042883 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 10537 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1608,89 +1636,91 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 24259 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 24259 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 11332 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 6025 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 6902 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 17357 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 400.040330 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 2564.899375 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-4095 16829 96.96% 96.96% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::4096-8191 181 1.04% 98.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::8192-12287 173 1.00% 99.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::12288-16383 71 0.41% 99.41% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::16384-20479 28 0.16% 99.57% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::20480-24575 5 0.03% 99.60% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::24576-28671 45 0.26% 99.86% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::28672-32767 6 0.03% 99.89% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-36863 14 0.08% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::36864-40959 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::40960-45055 2 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walks 24322 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 24322 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 11233 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5990 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 7099 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 17223 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 438.425361 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 2740.461547 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-4095 16689 96.90% 96.90% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::4096-8191 124 0.72% 97.62% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::8192-12287 219 1.27% 98.89% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::12288-16383 86 0.50% 99.39% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::16384-20479 20 0.12% 99.51% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::20480-24575 13 0.08% 99.58% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::24576-28671 39 0.23% 99.81% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::28672-32767 13 0.08% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::32768-36863 16 0.09% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::45056-49151 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::49152-53247 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::53248-57343 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 17357 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 5295 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 9383.568650 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 7860.112601 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 8293.617199 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 5259 99.32% 99.32% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 29 0.55% 99.87% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-98303 3 0.06% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::163840-196607 3 0.06% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::294912-327679 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 5295 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 69596834880 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.389063 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.490087 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 42554298056 61.14% 61.14% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 27024786824 38.83% 99.97% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2 11219000 0.02% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::3 3252000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4 913000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::5 701500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6 719000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::7 299000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8 99500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::9 182000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10 50000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::11 63500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12 106500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::13 34000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14 15000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::15 96000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 69596834880 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1939 74.63% 74.63% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 659 25.37% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2598 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 24259 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkWaitTime::53248-57343 2 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 17223 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 5609 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 10144.232484 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 8674.966878 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6379.427582 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 2437 43.45% 43.45% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 2571 45.84% 89.29% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 453 8.08% 97.36% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 115 2.05% 99.41% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 3 0.05% 99.47% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 25 0.45% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::90112-98303 4 0.07% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 5609 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 69613371380 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.373428 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.487046 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 43658416792 62.72% 62.72% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 25935559588 37.26% 99.97% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2 12091000 0.02% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::3 3523500 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4 1046500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::5 593000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6 908500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::7 323500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8 151000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::9 143500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10 80500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::11 88500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12 153000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::13 38000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14 28000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::15 226500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 69613371380 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1968 73.85% 73.85% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 697 26.15% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2665 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 24322 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 24259 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2598 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 24322 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2665 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2598 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 26857 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2665 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 26987 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 11166498 # DTB read hits -system.cpu1.dtb.read_misses 21069 # DTB read misses -system.cpu1.dtb.write_hits 7306223 # DTB write hits -system.cpu1.dtb.write_misses 3190 # DTB write misses +system.cpu1.dtb.read_hits 5224196 # DTB read hits +system.cpu1.dtb.read_misses 21002 # DTB read misses +system.cpu1.dtb.write_hits 4300766 # DTB write hits +system.cpu1.dtb.write_misses 3320 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2022 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 70 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 623 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2043 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 67 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 616 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 374 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 11187567 # DTB read accesses -system.cpu1.dtb.write_accesses 7309413 # DTB write accesses +system.cpu1.dtb.perms_faults 364 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 5245198 # DTB read accesses +system.cpu1.dtb.write_accesses 4304086 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 18472721 # DTB hits -system.cpu1.dtb.misses 24259 # DTB misses -system.cpu1.dtb.accesses 18496980 # DTB accesses +system.cpu1.dtb.hits 9524962 # DTB hits +system.cpu1.dtb.misses 24322 # DTB misses +system.cpu1.dtb.accesses 9549284 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1720,63 +1750,58 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 6817 # Table walker walks requested -system.cpu1.itb.walker.walksShort 6817 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 4075 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2679 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 63 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 6754 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 138.510512 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 1194.021921 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-2047 6631 98.18% 98.18% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::2048-4095 35 0.52% 98.70% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::4096-6143 28 0.41% 99.11% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::6144-8191 28 0.41% 99.53% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::8192-10239 11 0.16% 99.69% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::10240-12287 8 0.12% 99.81% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::12288-14335 4 0.06% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::14336-16383 2 0.03% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::20480-22527 2 0.03% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::22528-24575 2 0.03% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::24576-26623 2 0.03% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::26624-28671 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 6754 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1229 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 9949.958503 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 8666.714001 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 5833.930601 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-4095 208 16.92% 16.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 175 14.24% 31.16% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 520 42.31% 73.47% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 258 20.99% 94.47% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 10 0.81% 95.28% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 3 0.24% 95.52% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 30 2.44% 97.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 16 1.30% 99.27% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-36863 2 0.16% 99.43% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.41% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.08% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::61440-65535 1 0.08% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1229 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 18026373328 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.989122 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.103762 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 196149764 1.09% 1.09% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 17830158064 98.91% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 65500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 18026373328 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 995 85.33% 85.33% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 171 14.67% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1166 # Table walker page sizes translated +system.cpu1.itb.walker.walks 6842 # Table walker walks requested +system.cpu1.itb.walker.walksShort 6842 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 4094 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2680 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 68 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 6774 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 241.142604 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 1918.263476 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-4095 6651 98.18% 98.18% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::4096-8191 49 0.72% 98.91% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::8192-12287 35 0.52% 99.42% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::12288-16383 15 0.22% 99.65% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::16384-20479 5 0.07% 99.72% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::20480-24575 10 0.15% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::24576-28671 5 0.07% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::28672-32767 2 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::36864-40959 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::49152-53247 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 6774 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1233 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 11141.524736 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 9875.363796 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 6280.061079 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-8191 357 28.95% 28.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-16383 797 64.64% 93.59% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-24575 18 1.46% 95.05% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-32767 48 3.89% 98.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-40959 5 0.41% 99.35% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-49151 7 0.57% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-73727 1 0.08% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 1233 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 18042065828 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.988332 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.107619 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 210878764 1.17% 1.17% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 17830879064 98.83% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 267500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 19000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 21500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 18042065828 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 995 85.41% 85.41% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 170 14.59% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1165 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6817 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6817 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6842 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6842 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1166 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1166 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 7983 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 45723303 # ITB inst hits -system.cpu1.itb.inst_misses 6817 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1165 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1165 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 8007 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 10488200 # ITB inst hits +system.cpu1.itb.inst_misses 6842 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1785,1005 +1810,1037 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1199 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1196 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 537 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 530 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 45730120 # ITB inst accesses -system.cpu1.itb.hits 45723303 # DTB hits -system.cpu1.itb.misses 6817 # DTB misses -system.cpu1.itb.accesses 45730120 # DTB accesses -system.cpu1.numCycles 113567718 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 10495042 # ITB inst accesses +system.cpu1.itb.hits 10488200 # DTB hits +system.cpu1.itb.misses 6842 # DTB misses +system.cpu1.itb.accesses 10495042 # DTB accesses +system.cpu1.numCycles 43023242 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 11092326 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 115445294 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 35319894 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 28266544 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 98824380 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3951464 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 84431 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 39920 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 219438 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 325443 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 27387 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 45722696 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 133886 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2307 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 112589057 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.268755 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.334526 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 9545006 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 31536140 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 6152669 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 3495321 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 31308638 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 988880 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 91081 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 40105 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 214294 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 338691 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 30719 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 10487595 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 131638 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2429 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 42062974 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.911933 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.224898 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 52059388 46.24% 46.24% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 15346880 13.63% 59.87% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 8047278 7.15% 67.02% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 37135511 32.98% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 24350235 57.89% 57.89% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 6287044 14.95% 72.84% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 2205515 5.24% 78.08% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 9220180 21.92% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 112589057 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.311003 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.016533 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 14201102 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 65884249 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 29361473 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 1323272 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1818961 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 906595 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 159892 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 74422628 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 1448245 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1818961 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 18946447 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 2582249 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 60294532 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 25904145 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3042723 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 61245605 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 312742 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 326990 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 51393 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 18938 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 1837973 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 61569183 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 287884146 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 65513638 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 1660 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 58022651 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 3546532 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1914472 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1838523 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 13613893 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 11512865 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 7756589 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 697877 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 945772 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 60208856 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 646860 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 59677362 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 148586 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 4522679 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 7282133 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 53722 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 112589057 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.530046 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 0.866401 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 42062974 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.143008 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.733002 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 8267663 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 20626897 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 11490517 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 1337775 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 340122 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 874675 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 157334 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 30100708 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 1379443 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 340122 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 10041900 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 2603998 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 14921640 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11019721 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 3135593 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 28621166 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 281517 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 330506 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 50454 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 20125 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 1923436 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 29030542 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 132294985 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 32813170 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 1657 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 25609862 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 3420680 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 453393 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 375590 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 3438293 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 5562789 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 4719499 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 701110 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 705314 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 27634808 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 626900 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 27144127 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 143701 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 2955966 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 6891737 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 53840 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 42062974 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.645321 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 0.965357 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 76211299 67.69% 67.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 17665370 15.69% 83.38% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 14473056 12.85% 96.23% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3891466 3.46% 99.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 347848 0.31% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 18 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 26343154 62.63% 62.63% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 7337268 17.44% 80.07% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 5660550 13.46% 93.53% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 2402263 5.71% 99.24% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 319725 0.76% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 14 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 112589057 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 42062974 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 3478019 44.85% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 614 0.01% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 1940620 25.03% 69.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 2334930 30.11% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 1996325 32.40% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 609 0.01% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 1885144 30.59% 63.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 2280359 37.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 67 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 40635841 68.09% 68.09% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 52797 0.09% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 4119 0.01% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 11419177 19.13% 87.32% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7565361 12.68% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 17084879 62.94% 62.94% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 34880 0.13% 63.07% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 4083 0.02% 63.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 63.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 63.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 63.09% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 5473288 20.16% 83.25% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 4546930 16.75% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 59677362 # Type of FU issued -system.cpu1.iq.rate 0.525478 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7754183 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.129935 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 239840869 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 65386915 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 57545759 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 5681 # Number of floating instruction queue reads +system.cpu1.iq.FU_type_0::total 27144127 # Type of FU issued +system.cpu1.iq.rate 0.630918 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 6162437 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.227027 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 102651570 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 31226183 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 26510239 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 5796 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 2046 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 1784 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 67427880 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 3598 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 109848 # Number of loads that had data forwarded from stores +system.cpu1.iq.int_alu_accesses 33302783 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 3714 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 106694 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 624171 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 851 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 10604 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 419293 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 599497 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 782 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 10594 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 400513 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 57328 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 95447 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 46755 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 99859 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1818961 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 659321 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 119824 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 60910908 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 340122 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 663664 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 112730 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 28316728 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 11512865 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 7756589 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 325462 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 12815 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 97459 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 10604 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 81282 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 152799 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 234081 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 59327650 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 11286961 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 325473 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 5562789 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 4719499 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 329074 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 12650 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 90576 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 10594 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 71921 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 150578 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 222499 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 26808358 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 5342958 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 311471 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 55192 # number of nop insts executed -system.cpu1.iew.exec_refs 18774109 # number of memory reference insts executed -system.cpu1.iew.exec_branches 12866831 # Number of branches executed -system.cpu1.iew.exec_stores 7487148 # Number of stores executed -system.cpu1.iew.exec_rate 0.522399 # Inst execution rate -system.cpu1.iew.wb_sent 59146208 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 57547543 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 28211344 # num instructions producing a value -system.cpu1.iew.wb_consumers 43350974 # num instructions consuming a value +system.cpu1.iew.exec_nop 55020 # number of nop insts executed +system.cpu1.iew.exec_refs 9813397 # number of memory reference insts executed +system.cpu1.iew.exec_branches 4108906 # Number of branches executed +system.cpu1.iew.exec_stores 4470439 # Number of stores executed +system.cpu1.iew.exec_rate 0.623113 # Inst execution rate +system.cpu1.iew.wb_sent 26632744 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 26512023 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 13415515 # num instructions producing a value +system.cpu1.iew.wb_consumers 21195279 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.506724 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.650766 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.616226 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.632948 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 4198450 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 593138 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 217301 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 110549070 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.509875 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.177384 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 2659330 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 573060 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 205791 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 41503303 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.610529 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.356545 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 82464476 74.60% 74.60% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 15679600 14.18% 88.78% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6499039 5.88% 94.66% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 896756 0.81% 95.47% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 2234307 2.02% 97.49% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 1661965 1.50% 98.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 498497 0.45% 99.44% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 155172 0.14% 99.58% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 459258 0.42% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 29410485 70.86% 70.86% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 7042051 16.97% 87.83% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2116509 5.10% 92.93% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 864843 2.08% 95.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 769424 1.85% 96.87% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 435639 1.05% 97.92% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 276731 0.67% 98.58% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 147889 0.36% 98.94% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 439732 1.06% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 110549070 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 45875888 # Number of instructions committed -system.cpu1.commit.committedOps 56366249 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 41503303 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 20778200 # Number of instructions committed +system.cpu1.commit.committedOps 25338954 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 18225990 # Number of memory references committed -system.cpu1.commit.loads 10888694 # Number of loads committed -system.cpu1.commit.membars 231720 # Number of memory barriers committed -system.cpu1.commit.branches 12659864 # Number of branches committed +system.cpu1.commit.refs 9282278 # Number of memory references committed +system.cpu1.commit.loads 4963292 # Number of loads committed +system.cpu1.commit.membars 229830 # Number of memory barriers committed +system.cpu1.commit.branches 3902679 # Number of branches committed system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 50354679 # Number of committed integer instructions. -system.cpu1.commit.function_calls 3453612 # Number of function calls committed. +system.cpu1.commit.int_insts 22267919 # Number of committed integer instructions. +system.cpu1.commit.function_calls 549742 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 38084418 67.57% 67.57% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 51722 0.09% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 4119 0.01% 67.67% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.67% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.67% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.67% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 10888694 19.32% 86.98% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 7337296 13.02% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 16018762 63.22% 63.22% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 33831 0.13% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 4083 0.02% 63.37% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 63.37% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.37% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.37% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 4963292 19.59% 82.96% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 4318986 17.04% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 56366249 # Class of committed instruction -system.cpu1.commit.bw_lim_events 459258 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 150434096 # The number of ROB reads -system.cpu1.rob.rob_writes 123166009 # The number of ROB writes -system.cpu1.timesIdled 67345 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 978661 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 5136638072 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 45842675 # Number of Instructions Simulated -system.cpu1.committedOps 56333036 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 2.477336 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 2.477336 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.403659 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.403659 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 62490093 # number of integer regfile reads -system.cpu1.int_regfile_writes 39068646 # number of integer regfile writes -system.cpu1.fp_regfile_reads 1381 # number of floating regfile reads +system.cpu1.commit.op_class_0::total 25338954 # Class of committed instruction +system.cpu1.commit.bw_lim_events 439732 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 67911551 # The number of ROB reads +system.cpu1.rob.rob_writes 56552827 # The number of ROB writes +system.cpu1.timesIdled 67532 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 960268 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 5207215501 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 20744987 # Number of Instructions Simulated +system.cpu1.committedOps 25305741 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 2.073910 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 2.073910 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.482181 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.482181 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 29917814 # number of integer regfile reads +system.cpu1.int_regfile_writes 16874088 # number of integer regfile writes +system.cpu1.fp_regfile_reads 1382 # number of floating regfile reads system.cpu1.fp_regfile_writes 516 # number of floating regfile writes -system.cpu1.cc_regfile_reads 211116899 # number of cc regfile reads -system.cpu1.cc_regfile_writes 18233735 # number of cc regfile writes -system.cpu1.misc_regfile_reads 156287903 # number of misc regfile reads -system.cpu1.misc_regfile_writes 421035 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 227457 # number of replacements -system.cpu1.dcache.tags.tagsinuse 483.345523 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 17322126 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 227768 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 76.051623 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 89024511500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 483.345523 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.944034 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.944034 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id +system.cpu1.cc_regfile_reads 95785070 # number of cc regfile reads +system.cpu1.cc_regfile_writes 9455596 # number of cc regfile writes +system.cpu1.misc_regfile_reads 60806398 # number of misc regfile reads +system.cpu1.misc_regfile_writes 422782 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 228231 # number of replacements +system.cpu1.dcache.tags.tagsinuse 478.409113 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 8403253 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 228545 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 36.768483 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 103444079500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 478.409113 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.934393 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.934393 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 314 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 282 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 29 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 36423981 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 36423981 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 10467087 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 10467087 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 6561195 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 6561195 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 65021 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 65021 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 88659 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 88659 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 80691 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 80691 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 17028282 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 17028282 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 17093303 # number of overall hits -system.cpu1.dcache.overall_hits::total 17093303 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 254533 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 254533 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 479063 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 479063 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 35844 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 35844 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 19098 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 19098 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23509 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23509 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 733596 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 733596 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 769440 # number of overall misses -system.cpu1.dcache.overall_misses::total 769440 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3958996431 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3958996431 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 10579018157 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 10579018157 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 370185734 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 370185734 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 549251321 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 549251321 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 798500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 798500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 14538014588 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 14538014588 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 14538014588 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 14538014588 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 10721620 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 10721620 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 7040258 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 7040258 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 100865 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 100865 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 107757 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 107757 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 104200 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 104200 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 17761878 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 17761878 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 17862743 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 17862743 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023740 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.023740 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.068046 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.068046 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.355366 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.355366 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.177232 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.177232 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.225614 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.225614 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.041302 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.041302 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043075 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.043075 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15553.961298 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15553.961298 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22082.728487 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 22082.728487 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19383.481726 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19383.481726 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23363.448934 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23363.448934 # average StoreCondReq miss latency +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 32 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.613281 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 18586968 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 18586968 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 4548259 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 4548259 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 3563356 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3563356 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 63759 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 63759 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 87271 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 87271 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79516 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 79516 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 8111615 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 8111615 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 8175374 # number of overall hits +system.cpu1.dcache.overall_hits::total 8175374 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 254647 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 254647 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 480567 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 480567 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 35928 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 35928 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 19211 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 19211 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23462 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23462 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 735214 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 735214 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 771142 # number of overall misses +system.cpu1.dcache.overall_misses::total 771142 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4017153000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 4017153000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 11025282924 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 11025282924 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 376163500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 376163500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 545526500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 545526500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 528500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 528500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 15042435924 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 15042435924 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 15042435924 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 15042435924 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 4802906 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 4802906 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 4043923 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4043923 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 99687 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 99687 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 106482 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 106482 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 102978 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 102978 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 8846829 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 8846829 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 8946516 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 8946516 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.053019 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.053019 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.118837 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.118837 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.360408 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.360408 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.180415 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.180415 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.227835 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.227835 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.083105 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.083105 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.086195 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.086195 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15775.379250 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15775.379250 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22942.238905 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 22942.238905 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19580.630889 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19580.630889 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23251.491774 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23251.491774 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19817.467091 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 19817.467091 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18894.279720 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 18894.279720 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 393 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 1480475 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 42 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 48784 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.357143 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 30.347552 # average number of cycles each access was blocked +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20459.942172 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20459.942172 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19506.700354 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 19506.700354 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 359 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 1638919 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 40 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 49248 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.975000 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 33.278895 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 138868 # number of writebacks -system.cpu1.dcache.writebacks::total 138868 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 91268 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 91268 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 375164 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 375164 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13545 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13545 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 466432 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 466432 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 466432 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 466432 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 163265 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 163265 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 103899 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 103899 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 32275 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 32275 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5553 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5553 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23509 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23509 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 267164 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 267164 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 299439 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 299439 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 17059 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 17059 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 14341 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 14341 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 31400 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 31400 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2133861458 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2133861458 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2484196176 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2484196176 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 503074190 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 503074190 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 95947255 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 95947255 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 512832179 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 512832179 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 777500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 777500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4618057634 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4618057634 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5121131824 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 5121131824 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2900210250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2900210250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2419067503 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2419067503 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 5319277753 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 5319277753 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.015228 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.015228 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014758 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014758 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.319982 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.319982 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051533 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051533 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.225614 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.225614 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.015041 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.015041 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.016763 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.016763 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13069.925936 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13069.925936 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23909.721711 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23909.721711 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15587.116654 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15587.116654 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17278.453989 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17278.453989 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21814.291505 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21814.291505 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 137260 # number of writebacks +system.cpu1.dcache.writebacks::total 137260 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 91413 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 91413 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 375801 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 375801 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13808 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13808 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 467214 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 467214 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 467214 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 467214 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 163234 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 163234 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 104766 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 104766 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 32551 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 32551 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5403 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5403 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23462 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23462 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 268000 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 268000 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 300551 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 300551 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5603 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 5603 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 4908 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 4908 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10511 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 10511 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2247760000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2247760000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2639771935 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2639771935 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 542309000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 542309000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 101732500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 101732500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 522075500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 522075500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 517500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 517500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4887531935 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4887531935 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5429840935 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5429840935 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 989470000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 989470000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 857954500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 857954500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1847424500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1847424500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033987 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033987 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025907 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.025907 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.326532 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.326532 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050741 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050741 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.227835 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.227835 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030293 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.030293 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033594 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.033594 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13770.170430 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13770.170430 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 25196.838049 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 25196.838049 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16660.286934 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16660.286934 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18828.891357 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18828.891357 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22251.960617 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22251.960617 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17285.478710 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17285.478710 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17102.420940 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17102.420940 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 170010.566270 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 170010.566270 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 168681.926156 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 168681.926156 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 169403.750096 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 169403.750096 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18237.059459 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18237.059459 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18066.288034 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18066.288034 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176596.466179 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 176596.466179 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 174807.355338 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 174807.355338 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 175761.059842 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 175761.059842 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 671809 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.529348 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 45027049 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 672321 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 66.972546 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 78856865000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.529348 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973690 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.973690 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 661426 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.525577 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 9800007 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 661938 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 14.805023 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 78861824000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.525577 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973683 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.973683 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 92117192 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 92117192 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 45027049 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 45027049 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 45027049 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 45027049 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 45027049 # number of overall hits -system.cpu1.icache.overall_hits::total 45027049 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 695384 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 695384 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 695384 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 695384 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 695384 # number of overall misses -system.cpu1.icache.overall_misses::total 695384 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6371214084 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6371214084 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6371214084 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6371214084 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6371214084 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6371214084 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 45722433 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 45722433 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 45722433 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 45722433 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 45722433 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 45722433 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.015209 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.015209 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.015209 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.015209 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.015209 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.015209 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9162.152255 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 9162.152255 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9162.152255 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 9162.152255 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9162.152255 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 9162.152255 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 596666 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 27 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 49414 # number of cycles access was blocked +system.cpu1.icache.tags.tag_accesses 21636569 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 21636569 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 9800007 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 9800007 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 9800007 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 9800007 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 9800007 # number of overall hits +system.cpu1.icache.overall_hits::total 9800007 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 687303 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 687303 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 687303 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 687303 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 687303 # number of overall misses +system.cpu1.icache.overall_misses::total 687303 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6263235013 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 6263235013 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 6263235013 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 6263235013 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 6263235013 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 6263235013 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 10487310 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 10487310 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 10487310 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 10487310 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 10487310 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 10487310 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.065537 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.065537 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.065537 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.065537 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.065537 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.065537 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9112.771242 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 9112.771242 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9112.771242 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9112.771242 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9112.771242 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9112.771242 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 638996 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 564 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 53890 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.074837 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 27 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.857413 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 564 # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 23058 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 23058 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 23058 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 23058 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 23058 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 23058 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 672326 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 672326 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 672326 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 672326 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 672326 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 672326 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 100 # number of ReadReq MSHR uncacheable -system.cpu1.icache.ReadReq_mshr_uncacheable::total 100 # number of ReadReq MSHR uncacheable -system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 100 # number of overall MSHR uncacheable misses -system.cpu1.icache.overall_mshr_uncacheable_misses::total 100 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5482686465 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5482686465 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5482686465 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5482686465 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5482686465 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5482686465 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8677000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8677000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8677000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 8677000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014705 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014705 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014705 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.014705 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014705 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.014705 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8154.803570 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8154.803570 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8154.803570 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8154.803570 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8154.803570 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8154.803570 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86770 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 86770 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86770 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 86770 # average overall mshr uncacheable latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 25354 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 25354 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 25354 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 25354 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 25354 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 25354 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 661949 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 661949 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 661949 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 661949 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 661949 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 661949 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable +system.cpu1.icache.ReadReq_mshr_uncacheable::total 102 # number of ReadReq MSHR uncacheable +system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses +system.cpu1.icache.overall_mshr_uncacheable_misses::total 102 # number of overall MSHR uncacheable misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5721508360 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5721508360 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5721508360 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5721508360 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5721508360 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5721508360 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8594000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8594000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8594000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 8594000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.063119 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.063119 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.063119 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.063119 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.063119 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.063119 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8643.427757 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8643.427757 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8643.427757 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8643.427757 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8643.427757 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8643.427757 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 84254.901961 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 84254.901961 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 84254.901961 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 84254.901961 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 264317 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 265106 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 699 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 269622 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 270613 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 884 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 68110 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 61852 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15537.791452 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 937119 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 76426 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 12.261783 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 67787 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 66660 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15577.889137 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1655246 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 81265 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 20.368498 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 6612.049075 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 15.719968 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.202712 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4939.798550 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2550.027939 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1417.993208 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.403567 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000959 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000134 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.301501 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.155641 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.086547 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.948352 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1249 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 36 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13289 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 16 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 878 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 355 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 11 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 462 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8497 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4330 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.076233 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002197 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.811096 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 18910778 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 18910778 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 19107 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7219 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 650283 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 128648 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 805257 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 138868 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 138868 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1925 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 1925 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1050 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 1050 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 38271 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 38271 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 19107 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7219 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 650283 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 166919 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 843528 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 19107 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7219 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 650283 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 166919 # number of overall hits -system.cpu1.l2cache.overall_hits::total 843528 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 427 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 276 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 22038 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 72420 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 95161 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29112 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 29112 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22458 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22458 # number of SCUpgradeReq misses +system.cpu1.l2cache.tags.occ_blocks::writebacks 6747.638156 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 12.637913 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.167789 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4673.355619 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2625.058292 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1517.031368 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.411843 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000771 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000132 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.285239 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.160221 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.092592 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.950799 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1291 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 24 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13290 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 17 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 868 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 406 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 8 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 470 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8605 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4215 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.078796 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001465 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.811157 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 30536660 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 30536660 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 19077 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7323 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 26400 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 137259 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 137259 # number of Writeback hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2433 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 2433 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1103 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 1103 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 38090 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 38090 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 639615 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 639615 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 127678 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 127678 # number of ReadSharedReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 19077 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7323 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 639615 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 165768 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 831783 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 19077 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7323 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 639615 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 165768 # number of overall hits +system.cpu1.l2cache.overall_hits::total 831783 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 431 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 286 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 717 # number of ReadReq misses +system.cpu1.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses +system.cpu1.l2cache.Writeback_misses::total 1 # number of Writeback misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29127 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 29127 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22358 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 22358 # number of SCUpgradeReq misses system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 35228 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 35228 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 427 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 276 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 22038 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 107648 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 130389 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 427 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 276 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 22038 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 107648 # number of overall misses -system.cpu1.l2cache.overall_misses::total 130389 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 9785994 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5538750 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 913296236 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1683125409 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 2611746389 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 548231087 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 548231087 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 449027944 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 449027944 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 763500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 763500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1429440182 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1429440182 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 9785994 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5538750 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 913296236 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 3112565591 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 4041186571 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 9785994 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5538750 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 913296236 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 3112565591 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 4041186571 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 19534 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7495 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 672321 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 201068 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 900418 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 138868 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 138868 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 31037 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 31037 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23508 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 23508 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 35752 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 35752 # number of ReadExReq misses +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 22316 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadCleanReq_misses::total 22316 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 73485 # number of ReadSharedReq misses +system.cpu1.l2cache.ReadSharedReq_misses::total 73485 # number of ReadSharedReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 431 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 286 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 22316 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 109237 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 132270 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 431 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 286 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 22316 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 109237 # number of overall misses +system.cpu1.l2cache.overall_misses::total 132270 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 9445500 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5864000 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 15309500 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 555921000 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 555921000 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 449033000 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 449033000 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 501000 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 501000 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1528833498 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 1528833498 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 894673000 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::total 894673000 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1746677998 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1746677998 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 9445500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5864000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 894673000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 3275511496 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 4185493996 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 9445500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5864000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 894673000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 3275511496 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 4185493996 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 19508 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7609 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 27117 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 137260 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 137260 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 31560 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 31560 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23461 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 23461 # number of SCUpgradeReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 73499 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 73499 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 19534 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7495 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 672321 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 274567 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 973917 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 19534 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7495 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 672321 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 274567 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 973917 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.021859 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.036825 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.032779 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.360177 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.105685 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.937977 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.937977 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.955334 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.955334 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 73842 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 73842 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 661931 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::total 661931 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 201163 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::total 201163 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 19508 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7609 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 661931 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 275005 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 964053 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 19508 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7609 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 661931 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 275005 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 964053 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.022094 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.037587 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.026441 # miss rate for ReadReq accesses +system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000007 # miss rate for Writeback accesses +system.cpu1.l2cache.Writeback_miss_rate::total 0.000007 # miss rate for Writeback accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.922909 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.922909 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.952986 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.952986 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.479299 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.479299 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.021859 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.036825 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.032779 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.392065 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.133881 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.021859 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.036825 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.032779 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.392065 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.133881 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22918.018735 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20067.934783 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 41441.883837 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 23241.168310 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 27445.554261 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18831.790567 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18831.790567 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19994.119868 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19994.119868 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 763500 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 763500 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 40576.819064 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 40576.819064 # average ReadExReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22918.018735 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20067.934783 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 41441.883837 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 28914.290939 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 30993.309029 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22918.018735 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20067.934783 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 41441.883837 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 28914.290939 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 30993.309029 # average overall miss latency -system.cpu1.l2cache.blocked_cycles::no_mshrs 61 # number of cycles access was blocked +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.484169 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.484169 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.033713 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.033713 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.365301 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.365301 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.022094 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.037587 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.033713 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.397218 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.137202 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.022094 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.037587 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.033713 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.397218 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.137202 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21915.313225 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20503.496503 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21352.161785 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 19086.105675 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 19086.105675 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20083.773146 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20083.773146 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 501000 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 501000 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 42762.181081 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 42762.181081 # average ReadExReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 40091.100556 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 40091.100556 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23769.177356 # average ReadSharedReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23769.177356 # average ReadSharedReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21915.313225 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20503.496503 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 40091.100556 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29985.366643 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 31643.562380 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21915.313225 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20503.496503 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 40091.100556 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29985.366643 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 31643.562380 # average overall miss latency +system.cpu1.l2cache.blocked_cycles::no_mshrs 124 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 12.200000 # average number of cycles each access was blocked +system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 24.800000 # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 35144 # number of writebacks -system.cpu1.l2cache.writebacks::total 35144 # number of writebacks -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits +system.cpu1.l2cache.writebacks::writebacks 39050 # number of writebacks +system.cpu1.l2cache.writebacks::total 39050 # number of writebacks system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 13 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 16 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 141 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::total 171 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 736 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 736 # number of ReadExReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::total 13 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 854 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 854 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 14 # number of ReadCleanReq MSHR hits +system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 14 # number of ReadCleanReq MSHR hits +system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 144 # number of ReadSharedReq MSHR hits +system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 144 # number of ReadSharedReq MSHR hits system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 13 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 16 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 877 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 907 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 14 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 998 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 1025 # number of demand (read+write) MSHR hits system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 13 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 16 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 877 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 907 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 426 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 263 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 22022 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 72279 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 94990 # number of ReadReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 36425 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 36425 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29112 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29112 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22458 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22458 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 14 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 998 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 1025 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 431 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 273 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 704 # number of ReadReq MSHR misses +system.cpu1.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses +system.cpu1.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses +system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 3034 # number of CleanEvict MSHR misses +system.cpu1.l2cache.CleanEvict_mshr_misses::total 3034 # number of CleanEvict MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 37433 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 37433 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29127 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29127 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22358 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22358 # number of SCUpgradeReq MSHR misses system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 1 # number of SCUpgradeFailReq MSHR misses system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34492 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 34492 # number of ReadExReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 426 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 263 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 22022 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 106771 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 129482 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 426 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 263 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 22022 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 106771 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 36425 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 165907 # number of overall MSHR misses -system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 100 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 17059 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 17159 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 14341 # number of WriteReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 14341 # number of WriteReq MSHR uncacheable -system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 100 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 31400 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 31500 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 6994000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3664750 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 767719764 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1208019590 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1986398104 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1404338548 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1404338548 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 484116716 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 484116716 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 336604833 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 336604833 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 672500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 672500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1121552915 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1121552915 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 6994000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3664750 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 767719764 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2329572505 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 3107951019 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 6994000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3664750 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 767719764 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2329572505 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1404338548 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 4512289567 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7885000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2763450750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2771335750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 2311397498 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 2311397498 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7885000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 5074848248 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 5082733248 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.021808 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.035090 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.032755 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.359475 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.105495 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34898 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 34898 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 22302 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 22302 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 73341 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 73341 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 431 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 273 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 22302 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 108239 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 131245 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 431 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 273 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 22302 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 108239 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 37433 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 168678 # number of overall MSHR misses +system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 5603 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 5705 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 4908 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 4908 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 10511 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 10613 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 6859500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4063500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 10923000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1619868588 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1619868588 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 495927500 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 495927500 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 345361500 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 345361500 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 435000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 435000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1215520500 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1215520500 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 760109500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 760109500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1300287998 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1300287998 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 6859500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4063500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 760109500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2515808498 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 3286840998 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 6859500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4063500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 760109500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2515808498 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1619868588 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 4906709586 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7829000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 944359000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 952188000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 821025498 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 821025498 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7829000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1765384498 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1773213498 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.022094 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.035879 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.025962 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000007 # mshr miss rate for Writeback accesses +system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000007 # mshr miss rate for Writeback accesses +system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.937977 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.937977 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.955334 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.955334 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.922909 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.922909 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.952986 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.952986 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.469285 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.469285 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021808 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.035090 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.032755 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.388870 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.132950 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021808 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.035090 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.032755 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.388870 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.472604 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.472604 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.033692 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.033692 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.364585 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.364585 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022094 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.035879 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.033692 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.393589 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.136139 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022094 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.035879 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.033692 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.393589 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.170350 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16417.840376 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13934.410646 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 34861.491418 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 16713.285878 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 20911.654953 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 38554.249774 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 38554.249774 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16629.455757 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16629.455757 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14988.192760 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14988.192760 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 672500 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 672500 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32516.320161 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32516.320161 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16417.840376 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13934.410646 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 34861.491418 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21818.401111 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24002.958087 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16417.840376 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13934.410646 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 34861.491418 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21818.401111 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 38554.249774 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 27197.704539 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 78850 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 161993.712996 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 161509.164287 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 161174.081166 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161174.081166 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 78850 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 161619.370955 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 161356.611048 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.174968 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15915.313225 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14884.615385 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15515.625000 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43273.811557 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43273.811557 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17026.384454 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17026.384454 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15446.887020 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15446.887020 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 435000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 435000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34830.663648 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34830.663648 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 34082.571070 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34082.571070 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17729.346450 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17729.346450 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15915.313225 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14884.615385 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 34082.571070 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23243.087039 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25043.552120 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15915.313225 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14884.615385 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 34082.571070 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23243.087039 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43273.811557 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29089.208942 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 76754.901961 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 168545.243619 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 166904.119194 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 167283.108802 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 167283.108802 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 76754.901961 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 167955.903149 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 167079.383586 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 1277963 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 964810 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 31055 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 14341 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 138868 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 45574 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36263 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 76215 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 43067 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 89621 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 21 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 34 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 96319 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 79290 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1344847 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 942237 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 16928 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 42916 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2346928 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 43030144 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29597157 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 29980 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 78136 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 72735417 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 628857 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1745350 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 1.328609 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.469708 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 70770 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 942311 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 31035 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 4908 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 510267 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 868505 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 48336 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 75730 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 43006 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 89941 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 96740 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 79738 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 661949 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 536905 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1973224 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 988189 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17063 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 42721 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 3021197 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 42365216 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29405313 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 30436 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 78032 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 71878997 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 1156869 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 2994555 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 1.368102 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.482289 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 1171812 67.14% 67.14% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 573538 32.86% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 1892252 63.19% 63.19% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 1102303 36.81% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1745350 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 748369465 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 2994555 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 1102178989 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 88425999 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 87567999 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1009581341 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 993110829 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 468876167 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 449674318 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 9538553 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 9464978 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 23419937 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 23224976 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 31011 # Transaction distribution system.iobus.trans_dist::ReadResp 31011 # Transaction distribution system.iobus.trans_dist::WriteReq 59421 # Transaction distribution -system.iobus.trans_dist::WriteResp 23197 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.iobus.trans_dist::WriteResp 59421 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56600 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) @@ -2874,23 +2931,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 198987475 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 187554438 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 84715000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36777012 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36458 # number of replacements -system.iocache.tags.tagsinuse 14.446991 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.446879 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 254817991000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.446991 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.902937 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.902937 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 254837974000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.446879 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.902930 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.902930 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -2898,49 +2955,49 @@ system.iocache.tags.tag_accesses 328284 # Nu system.iocache.tags.data_accesses 328284 # Number of data accesses system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses system.iocache.ReadReq_misses::total 252 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses system.iocache.demand_misses::total 252 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 252 # number of overall misses system.iocache.overall_misses::total 252 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 32304877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 32304877 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6652654586 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 6652654586 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 32304877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 32304877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 32304877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 32304877 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 32277877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 32277877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4275018561 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4275018561 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 32277877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 32277877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 32277877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 32277877 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 128193.956349 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 128193.956349 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183653.229516 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 183653.229516 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 128193.956349 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 128193.956349 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 128193.956349 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 128193.956349 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 22817 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 128086.813492 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 128086.813492 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118016.192607 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118016.192607 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 128086.813492 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 128086.813492 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 128086.813492 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 128086.813492 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3477 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.562266 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -2948,619 +3005,625 @@ system.iocache.writebacks::writebacks 36206 # nu system.iocache.writebacks::total 36206 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ide 252 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 252 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ide 252 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 252 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 252 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 252 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 19198877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 19198877 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4768982610 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4768982610 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 19198877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 19198877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 19198877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 19198877 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 19677877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 19677877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2463818561 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2463818561 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 19677877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 19677877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 19677877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 19677877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76186.019841 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76186.019841 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131652.567635 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131652.567635 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 76186.019841 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76186.019841 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 76186.019841 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76186.019841 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78086.813492 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 78086.813492 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68016.192607 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68016.192607 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 78086.813492 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 78086.813492 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 78086.813492 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 78086.813492 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 130801 # number of replacements -system.l2c.tags.tagsinuse 64048.619051 # Cycle average of tags in use -system.l2c.tags.total_refs 351623 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 195125 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 1.802040 # Average number of references to valid blocks. +system.l2c.tags.replacements 136014 # number of replacements +system.l2c.tags.tagsinuse 64041.678257 # Cycle average of tags in use +system.l2c.tags.total_refs 410908 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 200324 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.051217 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 12682.907006 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 14.525676 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 2.048604 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5727.667382 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 1961.871644 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34750.097208 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 8.787095 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.903255 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3571.469043 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1470.884658 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3857.457480 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.193526 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000222 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000031 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.087397 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.029936 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.530244 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000134 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.054496 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.022444 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.058860 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.977304 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 31466 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 31 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 32827 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 119 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 6139 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 25208 # Occupied blocks per task id +system.l2c.tags.occ_blocks::writebacks 12985.002975 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 12.737581 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 3.016987 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 6471.116722 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 1893.814522 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 32628.788989 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 7.896219 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 1.746917 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3305.203826 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1817.254812 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4915.098707 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.198135 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000194 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000046 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.098741 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.028897 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.497876 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000120 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000027 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.050433 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.027729 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.074998 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.977198 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 30547 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 27 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 33736 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 132 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 6158 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 24257 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 30 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 462 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4937 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 27395 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.480133 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000473 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.500900 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5006121 # Number of tag accesses -system.l2c.tags.data_accesses 5006121 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 169 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 68 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 31569 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 45303 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 43197 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 68 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 33 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 16772 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 11005 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 7251 # number of ReadReq hits -system.l2c.ReadReq_hits::total 155435 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 227479 # number of Writeback hits -system.l2c.Writeback_hits::total 227479 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 2575 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 820 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 3395 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 255 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 98 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 353 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 3872 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 2196 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 6068 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 169 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 68 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 31569 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 49175 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 43197 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 68 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 33 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 16772 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 13201 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 7251 # number of demand (read+write) hits -system.l2c.demand_hits::total 161503 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 169 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 68 # number of overall hits -system.l2c.overall_hits::cpu0.inst 31569 # number of overall hits -system.l2c.overall_hits::cpu0.data 49175 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 43197 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 68 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 33 # number of overall hits -system.l2c.overall_hits::cpu1.inst 16772 # number of overall hits -system.l2c.overall_hits::cpu1.data 13201 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 7251 # number of overall hits -system.l2c.overall_hits::total 161503 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 27 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 5 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 17327 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 8118 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 128828 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 11 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 5250 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 2138 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 9461 # number of ReadReq misses -system.l2c.ReadReq_misses::total 171166 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 8455 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3870 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 12325 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 920 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1168 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2088 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 10724 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 8176 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 18900 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 27 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 5 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 17327 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 18842 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 128828 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 11 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 5250 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 10314 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 9461 # number of demand (read+write) misses -system.l2c.demand_misses::total 190066 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 27 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 5 # number of overall misses -system.l2c.overall_misses::cpu0.inst 17327 # number of overall misses -system.l2c.overall_misses::cpu0.data 18842 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 128828 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 11 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 5250 # number of overall misses -system.l2c.overall_misses::cpu1.data 10314 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 9461 # number of overall misses -system.l2c.overall_misses::total 190066 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2599500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 443500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 1426835542 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 735252946 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 14338160773 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1206000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 97250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 448103000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 186224591 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 1256067564 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 18394990666 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 7116778 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 2985907 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 10102685 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1350463 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1030967 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 2381430 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 1037256751 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 678589231 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1715845982 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 2599500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 443500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1426835542 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 1772509697 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 14338160773 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 1206000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 97250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 448103000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 864813822 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1256067564 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 20110836648 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 2599500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 443500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1426835542 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 1772509697 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 14338160773 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 1206000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 97250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 448103000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 864813822 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1256067564 # number of overall miss cycles -system.l2c.overall_miss_latency::total 20110836648 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 196 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 73 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 48896 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 53421 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 172025 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 79 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 34 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 22022 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 13143 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 16712 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 326601 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 227479 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 227479 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 11030 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 4690 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 15720 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 1175 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 1266 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2441 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 14596 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 10372 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 24968 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 196 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 73 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 48896 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 68017 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 172025 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 79 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 34 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 22022 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 23515 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 16712 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 351569 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 196 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 73 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 48896 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 68017 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 172025 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 79 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 34 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 22022 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 23515 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 16712 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 351569 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.137755 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.068493 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.354364 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.151963 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.748891 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.139241 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.029412 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.238398 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.162672 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.566120 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.524083 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.766546 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.825160 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.784033 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.782979 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.922591 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.855387 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.734722 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.788276 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.756969 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.137755 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.068493 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.354364 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.277019 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.748891 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.139241 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.029412 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.238398 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.438614 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.566120 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.540622 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.137755 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.068493 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.354364 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.277019 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.748891 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.139241 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.029412 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.238398 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.438614 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.566120 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.540622 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 96277.777778 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 88700 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 82347.523634 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 90570.700419 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 111296.929029 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 109636.363636 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 97250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 85352.952381 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 87102.240879 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 132762.663989 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 107468.718472 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 841.724187 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 771.552196 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 819.690467 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1467.894565 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 882.677226 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 1140.531609 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 96722.934633 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82997.704379 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 90785.501693 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 96277.777778 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 88700 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 82347.523634 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 94072.269239 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 111296.929029 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 109636.363636 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 97250 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 85352.952381 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 83848.538104 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 132762.663989 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 105809.753707 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 96277.777778 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 88700 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 82347.523634 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 94072.269239 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 111296.929029 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 109636.363636 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 97250 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 85352.952381 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 83848.538104 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 132762.663989 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 105809.753707 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 234 # number of cycles access was blocked +system.l2c.tags.age_task_id_blocks_1023::4 26 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 442 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5063 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 28206 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.466110 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000412 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.514771 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 5562101 # Number of tag accesses +system.l2c.tags.data_accesses 5562101 # Number of data accesses +system.l2c.Writeback_hits::writebacks 232311 # number of Writeback hits +system.l2c.Writeback_hits::total 232311 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 2454 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 792 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 3246 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 247 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 65 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 312 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 3756 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 1862 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 5618 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 184 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 89 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 33340 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 45362 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 43171 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 54 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 50 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 17322 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 11995 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 7539 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 159106 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 184 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 89 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 33340 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 49118 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 43171 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 54 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 50 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 17322 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 13857 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 7539 # number of demand (read+write) hits +system.l2c.demand_hits::total 164724 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 184 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 89 # number of overall hits +system.l2c.overall_hits::cpu0.inst 33340 # number of overall hits +system.l2c.overall_hits::cpu0.data 49118 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 43171 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 54 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 50 # number of overall hits +system.l2c.overall_hits::cpu1.inst 17322 # number of overall hits +system.l2c.overall_hits::cpu1.data 13857 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 7539 # number of overall hits +system.l2c.overall_hits::total 164724 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 8230 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3781 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 12011 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 840 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1148 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1988 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 11269 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 9058 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 20327 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 25 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.itb.walker 7 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.inst 17264 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 8071 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 130238 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 10 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 4969 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 2483 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 10791 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 173860 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.dtb.walker 25 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 7 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 17264 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 19340 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 130238 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 10 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 2 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 4969 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 11541 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 10791 # number of demand (read+write) misses +system.l2c.demand_misses::total 194187 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 25 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 7 # number of overall misses +system.l2c.overall_misses::cpu0.inst 17264 # number of overall misses +system.l2c.overall_misses::cpu0.data 19340 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 130238 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 10 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 2 # number of overall misses +system.l2c.overall_misses::cpu1.inst 4969 # number of overall misses +system.l2c.overall_misses::cpu1.data 11541 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 10791 # number of overall misses +system.l2c.overall_misses::total 194187 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0.data 7636500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 4088000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 11724500 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1275500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 739500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 2015000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 1086401000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 758222000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1844623000 # number of ReadExReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 2203000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 699000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1415731001 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 721065000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 14450210544 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 855000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 165500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.inst 421639500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 224776000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 1455323289 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 18692667834 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 2203000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 699000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1415731001 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 1807466000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 14450210544 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 855000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 165500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 421639500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 982998000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1455323289 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 20537290834 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 2203000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 699000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 1415731001 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 1807466000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 14450210544 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 855000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 165500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 421639500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 982998000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1455323289 # number of overall miss cycles +system.l2c.overall_miss_latency::total 20537290834 # number of overall miss cycles +system.l2c.Writeback_accesses::writebacks 232311 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 232311 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 10684 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 4573 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 15257 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 1087 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 1213 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2300 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 15025 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 10920 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 25945 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 209 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 96 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.inst 50604 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 53433 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 173409 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 64 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 52 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.inst 22291 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 14478 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 18330 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 332966 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 209 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 96 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 50604 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 68458 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 173409 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 64 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 52 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 22291 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 25398 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 18330 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 358911 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 209 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 96 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 50604 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 68458 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 173409 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 64 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 52 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 22291 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 25398 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 18330 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 358911 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.770311 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.826810 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.787245 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.772769 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.946414 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.864348 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.750017 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.829487 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.783465 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.119617 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.072917 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.341159 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.151049 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.751045 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.156250 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.038462 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.222915 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.171502 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.588707 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.522155 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.119617 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.072917 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.341159 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.282509 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.751045 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.156250 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.038462 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.222915 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.454406 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.588707 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.541045 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.119617 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.072917 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.341159 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.282509 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.751045 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.156250 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.038462 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.222915 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.454406 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.588707 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.541045 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 927.885784 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1081.195451 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 976.146865 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1518.452381 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 644.163763 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 1013.581489 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 96406.158488 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83707.440936 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 90747.429527 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 88120 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 99857.142857 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 82004.807750 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 89340.230455 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 110952.337597 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 85500 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 82750 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 84853.994768 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 90525.976641 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 134864.543508 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 107515.632313 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 88120 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 99857.142857 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 82004.807750 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 93457.394002 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 110952.337597 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 85500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 82750 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 84853.994768 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 85174.421627 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 134864.543508 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 105760.379603 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 88120 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 99857.142857 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 82004.807750 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 93457.394002 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 110952.337597 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 85500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 82750 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 84853.994768 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 85174.421627 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 134864.543508 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 105760.379603 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 1319 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 2 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 21 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 117 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 62.809524 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 98707 # number of writebacks -system.l2c.writebacks::total 98707 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 8 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 9 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 8 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 9 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 8 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 9 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 17 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 27 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 5 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 17319 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 8118 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 128828 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 11 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 5241 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 2138 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 9461 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 171149 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 8455 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 3870 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 12325 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 920 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1168 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 2088 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 10724 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 8176 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 18900 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 27 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 5 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 17319 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 18842 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 128828 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 11 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 5241 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 10314 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 9461 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 190049 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 27 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 5 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 17319 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 18842 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 128828 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 11 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 5241 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 10314 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 9461 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 190049 # number of overall MSHR misses -system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3002 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 17965 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 100 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 17055 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 38122 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 16714 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 14341 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 31055 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3002 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 34679 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 100 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 31396 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 69177 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 2258000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 380000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 1209530708 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 633945550 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 12753851063 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1069000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 84250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 381902000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 159442409 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1140236224 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 16282699204 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 150732427 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 68800353 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 219532780 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 16443920 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 20736167 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 37180087 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 905183749 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 576557769 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1481741518 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2258000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 380000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 1209530708 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 1539129299 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 12753851063 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1069000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 84250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 381902000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 736000178 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1140236224 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 17764440722 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2258000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 380000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 1209530708 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 1539129299 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 12753851063 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1069000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 84250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 381902000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 736000178 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1140236224 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 17764440722 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 181479250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3198370250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5885000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2430251250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 5815985750 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2250411545 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2045879002 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 4296290547 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 181479250 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5448781795 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5885000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 4476130252 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 10112276297 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.137755 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.068493 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.354201 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.151963 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.748891 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.139241 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.029412 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.237989 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.162672 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.566120 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.524031 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.766546 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.825160 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.784033 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.782979 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.922591 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.855387 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.734722 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.788276 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.756969 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.137755 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.068493 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.354201 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.277019 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.748891 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.139241 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.029412 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.237989 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.438614 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.566120 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.540574 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.137755 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.068493 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.354201 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.277019 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.748891 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.139241 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.029412 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.237989 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.438614 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.566120 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.540574 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 83629.629630 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 76000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 69838.368728 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 78091.346391 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98999.061252 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 97181.818182 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 84250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 72868.154932 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 74575.495323 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 120519.630483 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 95137.565536 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17827.608161 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17777.868992 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17811.990264 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17873.826087 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17753.567637 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17806.555077 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 84407.287300 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 70518.318126 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 78399.022116 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 83629.629630 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 76000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69838.368728 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 81686.089534 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98999.061252 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 97181.818182 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 84250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72868.154932 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71359.334691 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 120519.630483 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 93472.950250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 83629.629630 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 76000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69838.368728 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 81686.089534 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98999.061252 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 97181.818182 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 84250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72868.154932 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71359.334691 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 120519.630483 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 93472.950250 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60452.781479 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 178033.412190 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 58850 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142494.942832 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 152562.450816 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 134642.308544 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 142659.438114 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 138344.567606 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60452.781479 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 157120.499294 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 58850 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 142570.080647 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 146179.746115 # average overall mshr uncacheable latency +system.l2c.writebacks::writebacks 104474 # number of writebacks +system.l2c.writebacks::total 104474 # number of writebacks +system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 5 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 10 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 15 # number of ReadSharedReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 5 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 10 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 15 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 5 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 10 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 15 # number of overall MSHR hits +system.l2c.CleanEvict_mshr_misses::writebacks 3557 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 3557 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 8230 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 3781 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 12011 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 840 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1148 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1988 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 11269 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 9058 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 20327 # number of ReadExReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 25 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 7 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 17259 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 8071 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 130238 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 10 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 2 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 4959 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 2483 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 10791 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 173845 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 25 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 7 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 17259 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 19340 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 130238 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 10 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 2 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 4959 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 11541 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 10791 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 194172 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 25 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 7 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 17259 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 19340 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 130238 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 10 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 2 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 4959 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 11541 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 10791 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 194172 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3004 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 29394 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 5600 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 38100 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 26127 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 4908 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 31035 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3004 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 55521 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 10508 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 69135 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 170692500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 78410000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 249102500 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 17547003 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 23836000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 41383003 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 973711000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 667642000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1641353000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 1953000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 629000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1242953501 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 640355000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13147830544 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 755000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 145500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 371358500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 199946000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1347413289 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 16953339334 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1953000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 629000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 1242953501 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 1614066000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 13147830544 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 755000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 145500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 371358500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 867588000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1347413289 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 18594692334 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1953000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 629000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 1242953501 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 1614066000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13147830544 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 755000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 145500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 371358500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 867588000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1347413289 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 18594692334 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 189269500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4916712000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5992000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 843515500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 5955489000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3669260542 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 737586502 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 4406847044 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 189269500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 8585972542 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5992000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1581102002 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 10362336044 # number of overall MSHR uncacheable cycles +system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.770311 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.826810 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.787245 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.772769 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.946414 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.864348 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.750017 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.829487 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.783465 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.119617 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.072917 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.341060 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.151049 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.751045 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.156250 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.038462 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.222466 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.171502 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.588707 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.522110 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.119617 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.072917 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.341060 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.282509 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.751045 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.156250 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.038462 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.222466 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.454406 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.588707 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.541003 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.119617 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.072917 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.341060 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.282509 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.751045 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.156250 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.038462 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.222466 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.454406 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.588707 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.541003 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20740.279465 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20737.900026 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20739.530430 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20889.289286 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20763.066202 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20816.399899 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 86406.158488 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73707.440936 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 80747.429527 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 78120 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 89857.142857 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 72017.700968 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 79340.230455 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 100952.337597 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 75500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 72750 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 74885.763259 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80525.976641 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124864.543508 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 97519.855814 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 78120 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 89857.142857 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72017.700968 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 83457.394002 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 100952.337597 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 75500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 72750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 74885.763259 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75174.421627 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124864.543508 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 95764.025369 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 78120 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 89857.142857 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72017.700968 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 83457.394002 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 100952.337597 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 75500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 72750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 74885.763259 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75174.421627 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124864.543508 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 95764.025369 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63005.825566 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167269.238620 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 58745.098039 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 150627.767857 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 156312.047244 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 140439.412944 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 150282.498370 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141996.038150 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63005.825566 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 154643.694134 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 58745.098039 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 150466.501903 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 149885.528951 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 209523 # Transaction distribution -system.membus.trans_dist::ReadResp 209522 # Transaction distribution -system.membus.trans_dist::WriteReq 31055 # Transaction distribution -system.membus.trans_dist::WriteResp 31055 # Transaction distribution -system.membus.trans_dist::Writeback 134913 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 78034 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 41651 # Transaction distribution -system.membus.trans_dist::UpgradeResp 14508 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution -system.membus.trans_dist::ReadExReq 38508 # Transaction distribution -system.membus.trans_dist::ReadExResp 18805 # Transaction distribution +system.membus.trans_dist::ReadReq 38100 # Transaction distribution +system.membus.trans_dist::ReadResp 212196 # Transaction distribution +system.membus.trans_dist::WriteReq 31035 # Transaction distribution +system.membus.trans_dist::WriteResp 31035 # Transaction distribution +system.membus.trans_dist::Writeback 140680 # Transaction distribution +system.membus.trans_dist::CleanEvict 16716 # Transaction distribution +system.membus.trans_dist::UpgradeReq 77066 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 41581 # Transaction distribution +system.membus.trans_dist::UpgradeResp 14111 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution +system.membus.trans_dist::ReadExReq 40212 # Transaction distribution +system.membus.trans_dist::ReadExResp 20215 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 174097 # Transaction distribution +system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107912 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 40 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14300 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 648289 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 770541 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108921 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108921 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 879462 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14206 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 677829 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 799987 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108934 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108934 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 908921 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162793 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28600 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18522228 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18713941 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4636480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 4636480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 23350421 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 125464 # Total snoops (count) -system.membus.snoop_fanout::samples 569969 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28412 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19154168 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 19345693 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 21663837 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 125106 # Total snoops (count) +system.membus.snoop_fanout::samples 595969 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 569969 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 595969 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 569969 # Request fanout histogram -system.membus.reqLayer0.occupancy 81685500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 595969 # Request fanout histogram +system.membus.reqLayer0.occupancy 81639500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 28500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 27500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 12047488 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11797490 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1135057072 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1030129184 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1127535962 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1147298884 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 37496988 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64422049 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -3593,48 +3656,50 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 490298 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 490282 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 31055 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 31055 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 227479 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36263 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 81334 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 42004 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 123338 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 34 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 34 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 50269 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 50269 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 990291 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 371073 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1361364 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 30980096 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6355093 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 37335189 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 292587 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 958737 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.038087 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.191405 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 38103 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 495292 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 31035 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 31035 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 373006 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 88968 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 80200 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 41893 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 122093 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 23 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 50895 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 50895 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 457205 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1082088 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 352339 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1434427 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31351112 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6763093 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 38114205 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 462700 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 1239270 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.168619 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.374415 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 922222 96.19% 96.19% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 36515 3.81% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 1030306 83.14% 83.14% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 208964 16.86% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 958737 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 763418418 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 1239270 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 822017005 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 355500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 618495385 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 615196241 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 276060555 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 261600624 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 2070 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 2069 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2756 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 9df34f531..a1c5aab40 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.827616 # Number of seconds simulated -sim_ticks 2827616186000 # Number of ticks simulated -final_tick 2827616186000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.827546 # Number of seconds simulated +sim_ticks 2827546300000 # Number of ticks simulated +final_tick 2827546300000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 97479 # Simulator instruction rate (inst/s) -host_op_rate 118241 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2435971946 # Simulator tick rate (ticks/s) -host_mem_usage 621864 # Number of bytes of host memory used -host_seconds 1160.78 # Real time elapsed on the host -sim_insts 113151083 # Number of instructions simulated -sim_ops 137250963 # Number of ops (including micro ops) simulated +host_inst_rate 98439 # Simulator instruction rate (inst/s) +host_op_rate 119404 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2460684463 # Simulator tick rate (ticks/s) +host_mem_usage 625192 # Number of bytes of host memory used +host_seconds 1149.09 # Real time elapsed on the host +sim_insts 113115023 # Number of instructions simulated +sim_ops 137206411 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1325344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9769960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1322768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9763816 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11098056 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1325344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1325344 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8387584 # Number of bytes written to this memory +system.physmem.bytes_read::total 11089336 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1322768 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1322768 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8388544 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8405108 # Number of bytes written to this memory +system.physmem.bytes_written::total 8406068 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 22954 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 153176 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 22916 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 153080 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 176173 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 131056 # Number of write requests responded to by this memory +system.physmem.num_reads::total 176039 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 131071 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 135437 # Number of write requests responded to by this memory +system.physmem.num_writes::total 135452 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 475 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 468714 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3455193 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 467815 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3453106 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3924881 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 468714 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 468714 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2966309 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 6197 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2972507 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2966309 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 3921894 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 467815 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 467815 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2966722 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 6198 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2972920 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2966722 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 475 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 468714 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3461391 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 467815 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3459303 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6897387 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 176174 # Number of read requests accepted -system.physmem.writeReqs 171661 # Number of write requests accepted -system.physmem.readBursts 176174 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 171661 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11266304 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8832 # Total number of bytes read from write queue -system.physmem.bytesWritten 9457344 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11098120 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10723444 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 138 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 23861 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4579 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11334 # Per bank write bursts -system.physmem.perBankRdBursts::1 10890 # Per bank write bursts -system.physmem.perBankRdBursts::2 10732 # Per bank write bursts -system.physmem.perBankRdBursts::3 10393 # Per bank write bursts -system.physmem.perBankRdBursts::4 14045 # Per bank write bursts -system.physmem.perBankRdBursts::5 11531 # Per bank write bursts -system.physmem.perBankRdBursts::6 11498 # Per bank write bursts -system.physmem.perBankRdBursts::7 11674 # Per bank write bursts -system.physmem.perBankRdBursts::8 10645 # Per bank write bursts -system.physmem.perBankRdBursts::9 10993 # Per bank write bursts -system.physmem.perBankRdBursts::10 10307 # Per bank write bursts -system.physmem.perBankRdBursts::11 9597 # Per bank write bursts -system.physmem.perBankRdBursts::12 9956 # Per bank write bursts -system.physmem.perBankRdBursts::13 10908 # Per bank write bursts -system.physmem.perBankRdBursts::14 10689 # Per bank write bursts -system.physmem.perBankRdBursts::15 10844 # Per bank write bursts -system.physmem.perBankWrBursts::0 9257 # Per bank write bursts -system.physmem.perBankWrBursts::1 9346 # Per bank write bursts -system.physmem.perBankWrBursts::2 9336 # Per bank write bursts -system.physmem.perBankWrBursts::3 8962 # Per bank write bursts -system.physmem.perBankWrBursts::4 9705 # Per bank write bursts -system.physmem.perBankWrBursts::5 9746 # Per bank write bursts -system.physmem.perBankWrBursts::6 9125 # Per bank write bursts -system.physmem.perBankWrBursts::7 9630 # Per bank write bursts -system.physmem.perBankWrBursts::8 9307 # Per bank write bursts -system.physmem.perBankWrBursts::9 9634 # Per bank write bursts -system.physmem.perBankWrBursts::10 8942 # Per bank write bursts -system.physmem.perBankWrBursts::11 8449 # Per bank write bursts -system.physmem.perBankWrBursts::12 8881 # Per bank write bursts -system.physmem.perBankWrBursts::13 9361 # Per bank write bursts -system.physmem.perBankWrBursts::14 9018 # Per bank write bursts -system.physmem.perBankWrBursts::15 9072 # Per bank write bursts +system.physmem.bw_total::total 6894813 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 176040 # Number of read requests accepted +system.physmem.writeReqs 135452 # Number of write requests accepted +system.physmem.readBursts 176040 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 135452 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11255936 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 10624 # Total number of bytes read from write queue +system.physmem.bytesWritten 8418624 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11089400 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8406068 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 166 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3886 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 40804 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11283 # Per bank write bursts +system.physmem.perBankRdBursts::1 10909 # Per bank write bursts +system.physmem.perBankRdBursts::2 10879 # Per bank write bursts +system.physmem.perBankRdBursts::3 10544 # Per bank write bursts +system.physmem.perBankRdBursts::4 14049 # Per bank write bursts +system.physmem.perBankRdBursts::5 11359 # Per bank write bursts +system.physmem.perBankRdBursts::6 11255 # Per bank write bursts +system.physmem.perBankRdBursts::7 11497 # Per bank write bursts +system.physmem.perBankRdBursts::8 10572 # Per bank write bursts +system.physmem.perBankRdBursts::9 11295 # Per bank write bursts +system.physmem.perBankRdBursts::10 10218 # Per bank write bursts +system.physmem.perBankRdBursts::11 9589 # Per bank write bursts +system.physmem.perBankRdBursts::12 9979 # Per bank write bursts +system.physmem.perBankRdBursts::13 10701 # Per bank write bursts +system.physmem.perBankRdBursts::14 10842 # Per bank write bursts +system.physmem.perBankRdBursts::15 10903 # Per bank write bursts +system.physmem.perBankWrBursts::0 8346 # Per bank write bursts +system.physmem.perBankWrBursts::1 8306 # Per bank write bursts +system.physmem.perBankWrBursts::2 8514 # Per bank write bursts +system.physmem.perBankWrBursts::3 8219 # Per bank write bursts +system.physmem.perBankWrBursts::4 8602 # Per bank write bursts +system.physmem.perBankWrBursts::5 8561 # Per bank write bursts +system.physmem.perBankWrBursts::6 8053 # Per bank write bursts +system.physmem.perBankWrBursts::7 8529 # Per bank write bursts +system.physmem.perBankWrBursts::8 8073 # Per bank write bursts +system.physmem.perBankWrBursts::9 8804 # Per bank write bursts +system.physmem.perBankWrBursts::10 7852 # Per bank write bursts +system.physmem.perBankWrBursts::11 7407 # Per bank write bursts +system.physmem.perBankWrBursts::12 7747 # Per bank write bursts +system.physmem.perBankWrBursts::13 8181 # Per bank write bursts +system.physmem.perBankWrBursts::14 8268 # Per bank write bursts +system.physmem.perBankWrBursts::15 8079 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 58 # Number of times write queue was full causing retry -system.physmem.totGap 2827615975000 # Total gap between requests +system.physmem.numWrRetry 1 # Number of times write queue was full causing retry +system.physmem.totGap 2827546089000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 542 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) -system.physmem.readPktSize::4 2994 # Read request sizes (log2) +system.physmem.readPktSize::4 2997 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 172624 # Read request sizes (log2) +system.physmem.readPktSize::6 172487 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 167280 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 154910 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 18105 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2183 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 821 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 131071 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 154804 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 17996 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2231 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 828 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see @@ -159,161 +159,156 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1641 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6399 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6912 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6687 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7906 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7485 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 899 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2443 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2359 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2077 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1665 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1370 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1404 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1002 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 403 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 87 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 66219 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 312.955255 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 183.034234 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 334.173316 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24625 37.19% 37.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 15873 23.97% 61.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6865 10.37% 71.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3626 5.48% 77.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2732 4.13% 81.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1677 2.53% 83.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1136 1.72% 85.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1168 1.76% 87.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8517 12.86% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 66219 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6252 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.154671 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 564.033809 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6251 99.98% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6252 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6252 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.635797 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.335011 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 41.227878 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 5914 94.59% 94.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 86 1.38% 95.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 17 0.27% 96.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 16 0.26% 96.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 17 0.27% 96.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 30 0.48% 97.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 32 0.51% 97.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 14 0.22% 97.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 17 0.27% 98.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 6 0.10% 98.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 22 0.35% 98.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 18 0.29% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 7 0.11% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 1 0.02% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 1 0.02% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 6 0.10% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 4 0.06% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 4 0.06% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 3 0.05% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 5 0.08% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 16 0.26% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 2 0.03% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 3 0.05% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::400-415 1 0.02% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::448-463 1 0.02% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 3 0.05% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 1 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::704-719 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::752-767 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::864-879 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6252 # Writes before turning the bus around for reads -system.physmem.totQLat 2104913750 # Total ticks spent queuing -system.physmem.totMemAccLat 5405588750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 880180000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11957.29 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 2191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6983 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6948 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8550 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9754 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8859 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7952 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7090 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 65199 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 301.760702 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 178.342640 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.505125 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24507 37.59% 37.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 15999 24.54% 62.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6852 10.51% 72.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3716 5.70% 78.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2634 4.04% 82.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1687 2.59% 84.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1128 1.73% 86.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1089 1.67% 88.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7587 11.64% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65199 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6653 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.433789 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 560.061521 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6652 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6653 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6653 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.771682 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.345316 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 11.497785 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5824 87.54% 87.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 71 1.07% 88.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 181 2.72% 91.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 53 0.80% 92.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 64 0.96% 93.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 178 2.68% 95.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 29 0.44% 96.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 6 0.09% 96.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 9 0.14% 96.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 9 0.14% 96.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 8 0.12% 96.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 6 0.09% 96.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 170 2.56% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 4 0.06% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 6 0.09% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 8 0.12% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 2 0.03% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.02% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.03% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 4 0.06% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.02% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 11 0.17% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6653 # Writes before turning the bus around for reads +system.physmem.totQLat 2123501000 # Total ticks spent queuing +system.physmem.totMemAccLat 5421138500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 879370000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12073.99 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30707.29 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 30823.99 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.98 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.34 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 2.98 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.92 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.79 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.97 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.06 # Data bus utilization in percentage +system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.89 # Average write queue length when enqueuing -system.physmem.readRowHits 145058 # Number of row buffer hits during reads -system.physmem.writeRowHits 112529 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.40 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 76.14 # Row buffer hit rate for writes -system.physmem.avgGap 8129187.62 # Average gap between requests -system.physmem.pageHitRate 79.54 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 260517600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 142147500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 718356600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 486693360 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 184686106800 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 81488169855 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1625088668250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1892870659965 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.422846 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2703351122494 # Time in different power states -system.physmem_0.memoryStateTime::REF 94420300000 # Time in different power states +system.physmem.avgWrQLen 24.42 # Average write queue length when enqueuing +system.physmem.readRowHits 144861 # Number of row buffer hits during reads +system.physmem.writeRowHits 97354 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.37 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.00 # Row buffer hit rate for writes +system.physmem.avgGap 9077427.64 # Average gap between requests +system.physmem.pageHitRate 78.78 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 255989160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 139676625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 715845000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 435002400 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 184681529760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 81048006450 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1625432730750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1892708780145 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.382186 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2703925000250 # Time in different power states +system.physmem_0.memoryStateTime::REF 94417960000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 29844456256 # Time in different power states +system.physmem_0.memoryStateTime::ACT 29202842250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 240098040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 131005875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 654716400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 470862720 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 184686106800 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 80123990850 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1626285316500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1892592097185 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.324331 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2705354976994 # Time in different power states -system.physmem_1.memoryStateTime::REF 94420300000 # Time in different power states +system.physmem_1.actEnergy 236915280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 129269250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 655964400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 417383280 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 184681529760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 80055144540 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1626303662250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1892479868760 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.301228 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2705388162750 # Time in different power states +system.physmem_1.memoryStateTime::REF 94417960000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 27840895506 # Time in different power states +system.physmem_1.memoryStateTime::ACT 27740163750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory @@ -333,15 +328,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 46937284 # Number of BP lookups -system.cpu.branchPred.condPredicted 24041936 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1233234 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 29553356 # Number of BTB lookups -system.cpu.branchPred.BTBHits 21362007 # Number of BTB hits +system.cpu.branchPred.lookups 46902830 # Number of BP lookups +system.cpu.branchPred.condPredicted 24030897 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1232795 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 29532360 # Number of BTB lookups +system.cpu.branchPred.BTBHits 21346058 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 72.282847 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 11754741 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 33891 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 72.280231 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 11742213 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 33846 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -372,84 +367,86 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 72371 # Table walker walks requested -system.cpu.dtb.walker.walksShort 72371 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29709 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22637 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 20025 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 52346 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 408.397967 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 2384.163324 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-4095 50769 96.99% 96.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::4096-8191 522 1.00% 97.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::8192-12287 392 0.75% 98.73% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::12288-16383 322 0.62% 99.35% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::16384-20479 112 0.21% 99.56% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::20480-24575 191 0.36% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::24576-28671 14 0.03% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::28672-32767 8 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::32768-36863 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::36864-40959 2 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walks 72877 # Table walker walks requested +system.cpu.dtb.walker.walksShort 72877 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29786 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22407 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 20684 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 52193 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 427.193302 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 2519.151181 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-4095 50372 96.51% 96.51% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::4096-8191 577 1.11% 97.62% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::8192-12287 541 1.04% 98.65% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::12288-16383 349 0.67% 99.32% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::16384-20479 64 0.12% 99.44% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::20480-24575 245 0.47% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::24576-28671 20 0.04% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::28672-32767 5 0.01% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::32768-36863 6 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::36864-40959 4 0.01% 99.98% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::40960-45055 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::45056-49151 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::45056-49151 3 0.01% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::49152-53247 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::61440-65535 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 52346 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 17999 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 11613.492583 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 9112.637070 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 7625.312992 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-16383 13355 74.20% 74.20% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::16384-32767 4455 24.75% 98.95% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::32768-49151 181 1.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::49152-65535 5 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::81920-98303 2 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkWaitTime::53248-57343 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 52193 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 18420 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 12316.720955 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 9894.996282 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 7919.116299 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-16383 13659 74.15% 74.15% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::16384-32767 4520 24.54% 98.69% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::32768-49151 229 1.24% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::49152-65535 5 0.03% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-81919 1 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 17999 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 117490693224 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.629020 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.491115 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 117435257724 99.95% 99.95% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 37744500 0.03% 99.98% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 7698500 0.01% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 6179000 0.01% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 1033000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 848500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 1404000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 520500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::16-17 7500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 117490693224 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6498 81.61% 81.61% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1464 18.39% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7962 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 72371 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkCompletionTime::total 18420 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 117420807224 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.629573 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.491742 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 117361135224 99.95% 99.95% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 40228000 0.03% 99.98% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 8514000 0.01% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 6836000 0.01% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 1132500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 742000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 1403500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 806000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::16-17 10000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 117420807224 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6507 81.76% 81.76% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1452 18.24% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7959 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 72877 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 72371 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7962 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 72877 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7959 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7962 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 80333 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7959 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 80836 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 25461869 # DTB read hits -system.cpu.dtb.read_misses 62291 # DTB read misses -system.cpu.dtb.write_hits 19915387 # DTB write hits -system.cpu.dtb.write_misses 10080 # DTB write misses +system.cpu.dtb.read_hits 25454298 # DTB read hits +system.cpu.dtb.read_misses 62609 # DTB read misses +system.cpu.dtb.write_hits 19910353 # DTB write hits +system.cpu.dtb.write_misses 10268 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_entries 4354 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 348 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 2290 # Number of TLB faults due to prefetch +system.cpu.dtb.align_faults 354 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 2301 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1335 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 25524160 # DTB read accesses -system.cpu.dtb.write_accesses 19925467 # DTB write accesses +system.cpu.dtb.perms_faults 1336 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 25516907 # DTB read accesses +system.cpu.dtb.write_accesses 19920621 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 45377256 # DTB hits -system.cpu.dtb.misses 72371 # DTB misses -system.cpu.dtb.accesses 45449627 # DTB accesses +system.cpu.dtb.hits 45364651 # DTB hits +system.cpu.dtb.misses 72877 # DTB misses +system.cpu.dtb.accesses 45437528 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -479,56 +476,56 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 11974 # Table walker walks requested -system.cpu.itb.walker.walksShort 11974 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 3948 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksShortTerminationLevel::Level2 7776 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 250 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 11724 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 570.794951 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 2803.545728 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-8191 11373 97.01% 97.01% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::8192-16383 269 2.29% 99.30% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::16384-24575 71 0.61% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::24576-32767 7 0.06% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walks 11947 # Table walker walks requested +system.cpu.itb.walker.walksShort 11947 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 3916 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 7772 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 259 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 11688 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 646.175565 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 3062.873414 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-8191 11278 96.49% 96.49% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::8192-16383 250 2.14% 98.63% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::16384-24575 145 1.24% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::24576-32767 11 0.09% 99.97% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::40960-49151 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::49152-57343 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::57344-65535 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::57344-65535 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::65536-73727 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::73728-81919 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 11724 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 3579 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 12176.865046 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 9546.126127 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7774.383636 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-8191 1294 36.16% 36.16% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::8192-16383 1330 37.16% 73.32% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-24575 901 25.17% 98.49% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::24576-32767 22 0.61% 99.11% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::32768-40959 25 0.70% 99.80% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::40960-49151 5 0.14% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkWaitTime::total 11688 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3588 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 13165.830546 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 10749.838149 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7878.482425 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-8191 1266 35.28% 35.28% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::8192-16383 1353 37.71% 72.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-24575 898 25.03% 98.02% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::24576-32767 28 0.78% 98.80% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::32768-40959 19 0.53% 99.33% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::40960-49151 22 0.61% 99.94% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::81920-90111 2 0.06% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 3579 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 23001352712 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.973391 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.161136 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 612637000 2.66% 2.66% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 22388223712 97.33% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 416000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::3 45500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::4 30500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 23001352712 # Table walker pending requests distribution +system.cpu.itb.walker.walkCompletionTime::total 3588 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 22931465712 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.972560 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.163591 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 629948000 2.75% 2.75% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 22300919212 97.25% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 517500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 46500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::4 34500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 22931465712 # Table walker pending requests distribution system.cpu.itb.walker.walkPageSizes::4K 3007 90.33% 90.33% # Table walker page sizes translated system.cpu.itb.walker.walkPageSizes::1M 322 9.67% 100.00% # Table walker page sizes translated system.cpu.itb.walker.walkPageSizes::total 3329 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 11974 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 11974 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 11947 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 11947 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3329 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 3329 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 15303 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 66270436 # ITB inst hits -system.cpu.itb.inst_misses 11974 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin::total 15276 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 66251443 # ITB inst hits +system.cpu.itb.inst_misses 11947 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -537,98 +534,98 @@ system.cpu.itb.flush_tlb 64 # Nu system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 3095 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 3094 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2189 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2204 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 66282410 # ITB inst accesses -system.cpu.itb.hits 66270436 # DTB hits -system.cpu.itb.misses 11974 # DTB misses -system.cpu.itb.accesses 66282410 # DTB accesses -system.cpu.numCycles 263104506 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 66263390 # ITB inst accesses +system.cpu.itb.hits 66251443 # DTB hits +system.cpu.itb.misses 11947 # DTB misses +system.cpu.itb.accesses 66263390 # DTB accesses +system.cpu.numCycles 263015768 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 104871759 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 184678718 # Number of instructions fetch has processed -system.cpu.fetch.Branches 46937284 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33116748 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 147875517 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6159108 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 184684 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 7836 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 337023 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 520063 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 109 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 66270632 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1094853 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5249 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 256876545 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.877001 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.234757 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 104824855 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 184645834 # Number of instructions fetch has processed +system.cpu.fetch.Branches 46902830 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33088271 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 147851260 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6154028 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 194015 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 8214 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 337761 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 519343 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 115 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 66251613 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1117287 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5276 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 256812577 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.876982 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.234768 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 157598366 61.35% 61.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 29238251 11.38% 72.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 14077167 5.48% 78.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 55962761 21.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 157563978 61.35% 61.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 29227624 11.38% 72.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 14070468 5.48% 78.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 55950507 21.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 256876545 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.178398 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.701922 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 78017085 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 107782223 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 64633482 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3841952 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2601803 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3422699 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 486058 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 157446500 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3690202 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2601803 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 83861883 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 10277178 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 74822964 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 62634848 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 22677869 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 146804130 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 949467 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 441862 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 64017 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 17858 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 19908152 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 150492299 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 678751292 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 164435882 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10966 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 141814735 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8677561 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2844686 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2648369 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13872312 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26410080 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21300681 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1687720 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2166938 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 143540852 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2119167 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 143328298 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 272168 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8409052 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14689564 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 125312 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 256876545 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.557966 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.879925 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 256812577 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.178327 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.702033 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 77991094 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 107772330 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 64608850 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3840943 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2599360 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3422500 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 485951 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 157387425 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3689294 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2599360 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 83831420 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 10325294 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 74929297 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 62613486 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 22513720 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 146758942 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 947731 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 441861 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 64728 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 18116 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 19773665 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 150448126 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 678536041 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 164391886 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10952 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 141768145 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 8679978 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2842610 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2646257 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13861181 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26401367 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21296245 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1688204 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2197018 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 143495141 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2119201 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 143282260 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 272024 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8407927 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14689646 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 125355 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 256812577 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.557925 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.879880 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 168573864 65.62% 65.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 45206232 17.60% 83.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 31980064 12.45% 95.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 10303635 4.01% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 812717 0.32% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 168546355 65.63% 65.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 45160300 17.58% 83.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 32009606 12.46% 95.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 10282549 4.00% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 813734 0.32% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -636,44 +633,44 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 256876545 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 256812577 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 7356620 32.59% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 33 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5633879 24.95% 57.54% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 9585743 42.46% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7349115 32.77% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 31 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5633990 25.12% 57.89% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 9444813 42.11% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 96002656 66.98% 66.98% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 114517 0.08% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 95970305 66.98% 66.98% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 114498 0.08% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.06% # Type of FU issued @@ -697,101 +694,101 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.06% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 8586 0.01% 67.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 8584 0.01% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 26193106 18.27% 85.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21007096 14.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 26184358 18.27% 85.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21002178 14.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 143328298 # Type of FU issued -system.cpu.iq.rate 0.544758 # Inst issue rate -system.cpu.iq.fu_busy_cnt 22576275 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.157514 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 566346237 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 154074171 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 140211060 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 35347 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 13216 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 143282260 # Type of FU issued +system.cpu.iq.rate 0.544767 # Inst issue rate +system.cpu.iq.fu_busy_cnt 22427949 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.156530 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 566041717 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 154027392 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 140167901 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 35353 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 13184 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 11430 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 165879208 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 23028 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 323617 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 165684822 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 23050 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 323667 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1493976 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1493736 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 505 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18357 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 705133 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18344 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 705002 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 87833 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6849 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 87759 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6780 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2601803 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 997477 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 311742 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 145861072 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 2599360 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 993976 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 306451 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 145815403 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26410080 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21300681 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1095001 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 17866 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 276819 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18357 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 317506 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 471434 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 788940 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 142382517 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25789725 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 873528 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 26401367 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21296245 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1095018 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 17939 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 271517 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18344 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 317394 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 471153 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 788547 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 142337327 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25781702 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 872174 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 201053 # number of nop insts executed -system.cpu.iew.exec_refs 46667574 # number of memory reference insts executed -system.cpu.iew.exec_branches 26530134 # Number of branches executed -system.cpu.iew.exec_stores 20877849 # Number of stores executed -system.cpu.iew.exec_rate 0.541163 # Inst execution rate -system.cpu.iew.wb_sent 141996041 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 140222490 # cumulative count of insts written-back -system.cpu.iew.wb_producers 63271750 # num instructions producing a value -system.cpu.iew.wb_consumers 95823649 # num instructions consuming a value +system.cpu.iew.exec_nop 201061 # number of nop insts executed +system.cpu.iew.exec_refs 46654499 # number of memory reference insts executed +system.cpu.iew.exec_branches 26517785 # Number of branches executed +system.cpu.iew.exec_stores 20872797 # Number of stores executed +system.cpu.iew.exec_rate 0.541174 # Inst execution rate +system.cpu.iew.wb_sent 141950761 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 140179331 # cumulative count of insts written-back +system.cpu.iew.wb_producers 63256602 # num instructions producing a value +system.cpu.iew.wb_consumers 95788019 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.532954 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.660294 # average fanout of values written-back +system.cpu.iew.wb_rate 0.532969 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.660381 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7612502 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1993855 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 755483 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 253938585 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.541099 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.141491 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7614067 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1993846 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 755141 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 253876624 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.541055 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.141749 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 180469459 71.07% 71.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 43296577 17.05% 88.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15470824 6.09% 94.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4378580 1.72% 95.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6397908 2.52% 98.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1648304 0.65% 99.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 799189 0.31% 99.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 418335 0.16% 99.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1059409 0.42% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 180454723 71.08% 71.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 43255238 17.04% 88.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15471181 6.09% 94.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4380130 1.73% 95.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6364867 2.51% 98.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1673276 0.66% 99.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 800938 0.32% 99.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 418318 0.16% 99.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1057953 0.42% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 253938585 # Number of insts commited each cycle -system.cpu.commit.committedInsts 113305988 # Number of instructions committed -system.cpu.commit.committedOps 137405868 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 253876624 # Number of insts commited each cycle +system.cpu.commit.committedInsts 113269928 # Number of instructions committed +system.cpu.commit.committedOps 137361316 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 45511652 # Number of memory references committed -system.cpu.commit.loads 24916104 # Number of loads committed -system.cpu.commit.membars 814017 # Number of memory barriers committed -system.cpu.commit.branches 26045610 # Number of branches committed +system.cpu.commit.refs 45498874 # Number of memory references committed +system.cpu.commit.loads 24907631 # Number of loads committed +system.cpu.commit.membars 814016 # Number of memory barriers committed +system.cpu.commit.branches 26032948 # Number of branches committed system.cpu.commit.fp_insts 11428 # Number of committed floating point instructions. -system.cpu.commit.int_insts 120229462 # Number of committed integer instructions. -system.cpu.commit.function_calls 4892502 # Number of function calls committed. +system.cpu.commit.int_insts 120189151 # Number of committed integer instructions. +system.cpu.commit.function_calls 4888294 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 91772138 66.79% 66.79% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 113493 0.08% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 91740391 66.79% 66.79% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 113468 0.08% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction @@ -815,489 +812,501 @@ system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 8585 0.01% 66.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 8583 0.01% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 24916104 18.13% 85.01% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 20595548 14.99% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 24907631 18.13% 85.01% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 20591243 14.99% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 137405868 # Class of committed instruction -system.cpu.commit.bw_lim_events 1059409 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 375672050 # The number of ROB reads -system.cpu.rob.rob_writes 292972268 # The number of ROB writes -system.cpu.timesIdled 891577 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 6227961 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 5392127867 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 113151083 # Number of Instructions Simulated -system.cpu.committedOps 137250963 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.325250 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.325250 # CPI: Total CPI of All Threads -system.cpu.ipc 0.430061 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.430061 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 155826636 # number of integer regfile reads -system.cpu.int_regfile_writes 88633021 # number of integer regfile writes -system.cpu.fp_regfile_reads 9606 # number of floating regfile reads +system.cpu.commit.op_class_0::total 137361316 # Class of committed instruction +system.cpu.commit.bw_lim_events 1057953 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 375595727 # The number of ROB reads +system.cpu.rob.rob_writes 292884314 # The number of ROB writes +system.cpu.timesIdled 891951 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6203191 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 5392076833 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 113115023 # Number of Instructions Simulated +system.cpu.committedOps 137206411 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.325206 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.325206 # CPI: Total CPI of All Threads +system.cpu.ipc 0.430069 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.430069 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 155781292 # number of integer regfile reads +system.cpu.int_regfile_writes 88602572 # number of integer regfile writes +system.cpu.fp_regfile_reads 9590 # number of floating regfile reads system.cpu.fp_regfile_writes 2716 # number of floating regfile writes -system.cpu.cc_regfile_reads 502981878 # number of cc regfile reads -system.cpu.cc_regfile_writes 53178096 # number of cc regfile writes -system.cpu.misc_regfile_reads 334359649 # number of misc regfile reads -system.cpu.misc_regfile_writes 1519760 # number of misc regfile writes -system.cpu.dcache.tags.replacements 839617 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.954240 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40126369 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 840129 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 47.762152 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 270754250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.954240 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999911 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999911 # Average percentage of cache occupancy +system.cpu.cc_regfile_reads 502823661 # number of cc regfile reads +system.cpu.cc_regfile_writes 53168068 # number of cc regfile writes +system.cpu.misc_regfile_reads 334407132 # number of misc regfile reads +system.cpu.misc_regfile_writes 1519751 # number of misc regfile writes +system.cpu.dcache.tags.replacements 839265 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.954798 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40095385 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 839777 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 47.745276 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 267431500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.954798 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999912 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999912 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 359 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 360 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 179354797 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 179354797 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23316087 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23316087 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 15561026 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 15561026 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 345829 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 345829 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 441066 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 441066 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 459481 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 459481 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 38877113 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 38877113 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 39222942 # number of overall hits -system.cpu.dcache.overall_hits::total 39222942 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 705718 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 705718 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3595150 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3595150 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 177438 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 177438 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 26862 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 26862 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 179307579 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 179307579 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23304230 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23304230 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 15542006 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 15542006 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 345703 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 345703 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 441081 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 441081 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 459484 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 459484 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 38846236 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 38846236 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 39191939 # number of overall hits +system.cpu.dcache.overall_hits::total 39191939 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 710133 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 710133 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3609878 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3609878 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 177558 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 177558 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 26867 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 26867 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 4300868 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4300868 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4478306 # number of overall misses -system.cpu.dcache.overall_misses::total 4478306 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10273111663 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10273111663 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 149502808344 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 149502808344 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 365521996 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 365521996 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 4320011 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4320011 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4497569 # number of overall misses +system.cpu.dcache.overall_misses::total 4497569 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10292232000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10292232000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 148465108677 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 148465108677 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 365302500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 365302500 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 209000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 209000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 159775920007 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 159775920007 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 159775920007 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 159775920007 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24021805 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24021805 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19156176 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19156176 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 523267 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 523267 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 467928 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 467928 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 459486 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 459486 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 43177981 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 43177981 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 43701248 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 43701248 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029378 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.029378 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.187676 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.187676 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.339096 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.339096 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057406 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057406 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_latency::cpu.data 158757340677 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 158757340677 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 158757340677 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 158757340677 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24014363 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24014363 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19151884 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19151884 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 523261 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 523261 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 467948 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 467948 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 459489 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 459489 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 43166247 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 43166247 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43689508 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43689508 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029571 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.029571 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188487 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.188487 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.339330 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.339330 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057414 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057414 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000011 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000011 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.099608 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.099608 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.102475 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.102475 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14556.964202 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14556.964202 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41584.581546 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41584.581546 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13607.400640 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13607.400640 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.100078 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.100078 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.102944 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.102944 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14493.386450 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14493.386450 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41127.458789 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41127.458789 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13596.698552 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13596.698552 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 41800 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 41800 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37149.691645 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37149.691645 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35677.758511 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 35677.758511 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 582483 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 36749.290841 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 36749.290841 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35298.478062 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35298.478062 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 590707 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 7397 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 7439 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 78.745843 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 79.406775 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 696320 # number of writebacks -system.cpu.dcache.writebacks::total 696320 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 291077 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 291077 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3294875 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3294875 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18482 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 18482 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3585952 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3585952 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3585952 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3585952 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414641 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 414641 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300275 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 300275 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119609 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 119609 # number of SoftPFReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8380 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 8380 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 696043 # number of writebacks +system.cpu.dcache.writebacks::total 696043 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 295841 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 295841 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3309634 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3309634 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18475 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 18475 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3605475 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3605475 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3605475 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3605475 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414292 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 414292 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300244 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 300244 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119628 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 119628 # number of SoftPFReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8392 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 8392 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 714916 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 714916 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 834525 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 834525 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 714536 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 714536 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 834164 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 834164 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31127 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 31127 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 58711 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5660697158 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5660697158 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13235281165 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 13235281165 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1562991253 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1562991253 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 123125251 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 123125251 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 201500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 201500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18895978323 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 18895978323 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20458969576 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 20458969576 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5831942750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5831942750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4511868951 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4511868951 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10343811701 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 10343811701 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017261 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017261 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015675 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015675 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228581 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228581 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017909 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017909 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5857375000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5857375000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13373750471 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 13373750471 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1627994000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1627994000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 128038500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 128038500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 204000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 204000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19231125471 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 19231125471 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20859119471 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 20859119471 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5908113500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5908113500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4570874950 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4570874950 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10478988450 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10478988450 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017252 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017252 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015677 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015677 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228620 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228620 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017934 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017934 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016557 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016557 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019096 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.019096 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13652.043956 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13652.043956 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44077.199784 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44077.199784 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13067.505397 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13067.505397 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14692.750716 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14692.750716 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 40300 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 40300 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26431.046896 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26431.046896 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24515.706032 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24515.706032 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 187359.615446 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 187359.615446 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 163568.334941 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163568.334941 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 176181.834767 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 176181.834767 # average overall mshr uncacheable latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016553 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016553 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019093 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019093 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14138.276868 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14138.276868 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44542.939979 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44542.939979 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13608.803959 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13608.803959 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15257.209247 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15257.209247 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 40800 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 40800 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26914.144943 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26914.144943 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25006.017367 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25006.017367 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189806.711215 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 189806.711215 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 165707.473535 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 165707.473535 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 178484.244009 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 178484.244009 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1892540 # number of replacements -system.cpu.icache.tags.tagsinuse 511.345997 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 64285030 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1893052 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 33.958407 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 13579028250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.345997 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.998723 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.998723 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1891955 # number of replacements +system.cpu.icache.tags.tagsinuse 511.348314 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 64263909 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1892467 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 33.957744 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 13555622500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.348314 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.998727 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.998727 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 228 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 68160699 # Number of tag accesses -system.cpu.icache.tags.data_accesses 68160699 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 64285030 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 64285030 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 64285030 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 64285030 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 64285030 # number of overall hits -system.cpu.icache.overall_hits::total 64285030 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1982600 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1982600 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1982600 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1982600 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1982600 # number of overall misses -system.cpu.icache.overall_misses::total 1982600 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 26922947970 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 26922947970 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 26922947970 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 26922947970 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 26922947970 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 26922947970 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 66267630 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 66267630 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 66267630 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 66267630 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 66267630 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 66267630 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029918 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.029918 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.029918 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.029918 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.029918 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.029918 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13579.616650 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13579.616650 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13579.616650 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13579.616650 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13579.616650 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13579.616650 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2392 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 68141093 # Number of tag accesses +system.cpu.icache.tags.data_accesses 68141093 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 64263909 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 64263909 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 64263909 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 64263909 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 64263909 # number of overall hits +system.cpu.icache.overall_hits::total 64263909 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1984699 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1984699 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1984699 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1984699 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1984699 # number of overall misses +system.cpu.icache.overall_misses::total 1984699 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 26888996997 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 26888996997 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 26888996997 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 26888996997 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 26888996997 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 26888996997 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 66248608 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 66248608 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 66248608 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 66248608 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 66248608 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 66248608 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029958 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.029958 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.029958 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.029958 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.029958 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.029958 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13548.148609 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13548.148609 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13548.148609 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13548.148609 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13548.148609 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13548.148609 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2508 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 125 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 127 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 19.136000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 19.748031 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 89529 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 89529 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 89529 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 89529 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 89529 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 89529 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1893071 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1893071 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1893071 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1893071 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1893071 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1893071 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3002 # number of ReadReq MSHR uncacheable -system.cpu.icache.ReadReq_mshr_uncacheable::total 3002 # number of ReadReq MSHR uncacheable -system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3002 # number of overall MSHR uncacheable misses -system.cpu.icache.overall_mshr_uncacheable_misses::total 3002 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23219754000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23219754000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23219754000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23219754000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23219754000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23219754000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 225366000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 225366000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 225366000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 225366000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028567 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028567 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028567 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.028567 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028567 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.028567 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12265.654062 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12265.654062 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12265.654062 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12265.654062 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12265.654062 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12265.654062 # average overall mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 75071.952032 # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 75071.952032 # average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 75071.952032 # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 75071.952032 # average overall mshr uncacheable latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 92212 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 92212 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 92212 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 92212 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 92212 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 92212 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1892487 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1892487 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1892487 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1892487 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1892487 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1892487 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3005 # number of ReadReq MSHR uncacheable +system.cpu.icache.ReadReq_mshr_uncacheable::total 3005 # number of ReadReq MSHR uncacheable +system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3005 # number of overall MSHR uncacheable misses +system.cpu.icache.overall_mshr_uncacheable_misses::total 3005 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24145787497 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 24145787497 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24145787497 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 24145787497 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24145787497 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 24145787497 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 225776500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 225776500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 225776500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 225776500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028566 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028566 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028566 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.028566 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028566 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.028566 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12758.760032 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12758.760032 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12758.760032 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12758.760032 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12758.760032 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12758.760032 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 75133.610649 # average ReadReq mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 75133.610649 # average ReadReq mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 75133.610649 # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 75133.610649 # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 103160 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65071.102218 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3020124 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 168359 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 17.938596 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 103023 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65070.034194 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5007824 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 168222 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 29.769138 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 49253.315053 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 11.936082 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 2.797931 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 10086.820532 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 5716.232619 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.751546 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000182 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 49133.665655 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 12.985449 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 2.797952 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 10208.479538 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 5712.105601 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.749720 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000198 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000043 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.153913 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.087223 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.992906 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65183 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.155769 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.087160 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.992890 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 17 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65182 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 17 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 152 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2920 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6837 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55246 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000244 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994614 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 28477722 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 28477722 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 56030 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12587 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 1873051 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 528182 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2469850 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 696320 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 696320 # number of Writeback hits +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 153 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2916 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6860 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55225 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000259 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994598 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 44376961 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 44376961 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 56023 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12549 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 68572 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 696043 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 696043 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 36 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 36 # number of UpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 157101 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 157101 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 56030 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 12587 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1873051 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 685283 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2626951 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 56030 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 12587 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1873051 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 685283 # number of overall hits -system.cpu.l2cache.overall_hits::total 2626951 # number of overall hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 157187 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 157187 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1872509 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1872509 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 527843 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 527843 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 56023 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 12549 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 1872509 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 685030 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2626111 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 56023 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 12549 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1872509 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 685030 # number of overall hits +system.cpu.l2cache.overall_hits::total 2626111 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 21 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 19985 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 14326 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 34339 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2720 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2720 # number of UpgradeReq misses +system.cpu.l2cache.ReadReq_misses::total 28 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2721 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2721 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 140540 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 140540 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 140423 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 140423 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 19944 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 19944 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 14346 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 14346 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 21 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 19985 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 154866 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 174879 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 19944 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 154769 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 174741 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 21 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 19985 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 154866 # number of overall misses -system.cpu.l2cache.overall_misses::total 174879 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1759750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 789750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1637862750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1227493750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2867906000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 966469 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 966469 # number of UpgradeReq miss cycles +system.cpu.l2cache.overall_misses::cpu.inst 19944 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 154769 # number of overall misses +system.cpu.l2cache.overall_misses::total 174741 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1844500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 579500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2424000 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 955000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 955000 # number of UpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 165000 # number of SCUpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::total 165000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11197753141 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 11197753141 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1759750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 789750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1637862750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 12425246891 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 14065659141 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1759750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 789750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1637862750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12425246891 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 14065659141 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 56051 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12594 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1893036 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 542508 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2504189 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 696320 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 696320 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11187095500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 11187095500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1623118000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 1623118000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1226117500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 1226117500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1844500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 579500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1623118000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12413213000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 14038755000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1844500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 579500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1623118000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12413213000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 14038755000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 56044 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12556 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 68600 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 696043 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 696043 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2757 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2757 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 5 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 297641 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 297641 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 56051 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 12594 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1893036 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 840149 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2801830 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 56051 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 12594 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1893036 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 840149 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2801830 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 297610 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 297610 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1892453 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1892453 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 542189 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 542189 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 56044 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 12556 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1892453 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 839799 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2800852 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 56044 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 12556 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1892453 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 839799 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2800852 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000375 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000556 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010557 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026407 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.013713 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986938 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986938 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000558 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.000408 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986942 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986942 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.400000 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.400000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.472180 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.472180 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.471836 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.471836 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010539 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010539 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.026459 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.026459 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000375 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000556 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010557 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.184332 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.062416 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000558 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010539 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.184293 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.062389 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000375 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000556 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010557 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.184332 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.062416 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 83797.619048 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 112821.428571 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81954.603453 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85682.936619 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 83517.458284 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 355.319485 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 355.319485 # average UpgradeReq miss latency +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000558 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010539 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.184293 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.062389 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 87833.333333 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 82785.714286 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 86571.428571 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 350.973907 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 350.973907 # average UpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 82500 # average SCUpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 82500 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79676.626875 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79676.626875 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 83797.619048 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 112821.428571 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81954.603453 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80232.245238 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 80430.807250 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 83797.619048 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 112821.428571 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81954.603453 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80232.245238 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 80430.807250 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79667.116498 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79667.116498 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81383.774569 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81383.774569 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85467.551931 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85467.551931 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 87833.333333 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 82785.714286 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81383.774569 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80204.776150 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 80340.360877 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 87833.333333 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 82785.714286 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81383.774569 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80204.776150 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 80340.360877 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1306,176 +1315,187 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 94866 # number of writebacks -system.cpu.l2cache.writebacks::total 94866 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 22 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 112 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 134 # number of ReadReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 94881 # number of writebacks +system.cpu.l2cache.writebacks::total 94881 # number of writebacks +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 22 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 22 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 111 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 111 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 22 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 112 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 134 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 111 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 133 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 22 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 112 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 134 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 111 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 133 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 21 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 19963 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 14214 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 34205 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2720 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2720 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 28 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2721 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2721 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 140540 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 140540 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 140423 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 140423 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 19922 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 19922 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 14235 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 14235 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 21 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 19963 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 154754 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 174745 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 19922 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 154658 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 174608 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 21 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 19963 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 154754 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 174745 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3002 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.overall_mshr_misses::cpu.inst 19922 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 154658 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 174608 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3005 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31127 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34129 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34132 # number of ReadReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3002 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3005 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61713 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1495250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 701750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1386544250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1041614500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2430355750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 48397220 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 48397220 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 140500 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 140500 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9440469859 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9440469859 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1495250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 701750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1386544250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10482084359 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 11870825609 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1495250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 701750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1386544250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10482084359 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 11870825609 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 181832000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5395669750 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5577501750 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4151610000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4151610000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 181832000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9547279750 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9729111750 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61716 # number of overall MSHR uncacheable misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1634500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 509500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2144000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 56503000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 56503000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 145000 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 145000 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9782865500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9782865500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1422648500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1422648500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1076334500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1076334500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1634500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 509500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1422648500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10859200000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12283992500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1634500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 509500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1422648500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10859200000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 12283992500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 188213500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5519024000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5707237500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4252080000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4252080000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 188213500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9771104000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9959317500 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000375 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010545 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026201 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013659 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986938 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986938 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000558 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000408 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986942 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986942 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.400000 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.472180 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.472180 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.471836 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.471836 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010527 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010527 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026255 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.026255 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000375 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010545 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.184198 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.062368 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000558 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010527 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.184161 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.062341 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000375 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010545 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.184198 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.062368 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 100250 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69455.705555 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73280.885043 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71052.645812 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17793.095588 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17793.095588 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70250 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70250 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67172.832354 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67172.832354 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 100250 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69455.705555 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67733.850879 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67932.276225 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 100250 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69455.705555 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67733.850879 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67932.276225 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 60570.286476 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173343.712854 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163424.118785 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 150507.903132 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150507.903132 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 60570.286476 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162614.837935 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 157650.928492 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000558 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010527 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.184161 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.062341 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 77833.333333 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 72785.714286 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 76571.428571 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20765.527380 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20765.527380 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 72500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 72500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69667.116498 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69667.116498 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71410.927618 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71410.927618 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75611.837021 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75611.837021 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 77833.333333 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 72785.714286 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71410.927618 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70214.279248 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70351.830958 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 77833.333333 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 72785.714286 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71410.927618 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70214.279248 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70351.830958 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 62633.444260 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 177306.646962 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 167210.755303 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 154150.232019 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 154150.232019 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 62633.444260 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 166427.143125 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 161373.347268 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2564424 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2564404 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 128192 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2563081 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 696320 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36268 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 827115 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1997055 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2757 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2761 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 297641 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 297641 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3792109 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2499777 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 32094 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 131034 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6455014 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121202208 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98530845 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 50376 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 224204 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 220007633 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 62589 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3624998 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.036134 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.186622 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 2762 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 297610 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 297610 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1892487 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 542422 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5643819 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2634611 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 32016 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 130644 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8441090 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121164944 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98490717 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 50224 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 224176 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 219930061 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 201613 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5797948 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.046562 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.210699 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3494014 96.39% 96.39% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 130984 3.61% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5527984 95.34% 95.34% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 269964 4.66% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3624998 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2504368734 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 5797948 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3520857499 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 322500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2847443747 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2842352755 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1338896897 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1306164667 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 19507738 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 19466986 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 75011458 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74632435 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 30182 # Transaction distribution system.iobus.trans_dist::ReadResp 30182 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution -system.iobus.trans_dist::WriteResp 22790 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.iobus.trans_dist::WriteResp 59014 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) @@ -1566,23 +1586,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 198816983 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 187477456 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36845510 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36738000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36423 # number of replacements -system.iocache.tags.tagsinuse 1.000480 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.000222 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36439 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 252520633000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.000480 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062530 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062530 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 252500924000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.000222 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062514 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062514 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1590,49 +1610,49 @@ system.iocache.tags.tag_accesses 328113 # Nu system.iocache.tags.data_accesses 328113 # Number of data accesses system.iocache.ReadReq_misses::realview.ide 233 # number of ReadReq misses system.iocache.ReadReq_misses::total 233 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses system.iocache.demand_misses::realview.ide 233 # number of demand (read+write) misses system.iocache.demand_misses::total 233 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 233 # number of overall misses system.iocache.overall_misses::total 233 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 28780877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 28780877 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6657450596 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 6657450596 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 28780877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 28780877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 28780877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 28780877 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 28674877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28674877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4272498579 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4272498579 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 28674877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 28674877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 28674877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 28674877 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 233 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 233 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ide 233 # number of demand (read+write) accesses system.iocache.demand_accesses::total 233 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ide 233 # number of overall (read+write) accesses system.iocache.overall_accesses::total 233 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 123523.077253 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 123523.077253 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183785.628202 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 183785.628202 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 123523.077253 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 123523.077253 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 123523.077253 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 123523.077253 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 22928 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 123068.141631 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 123068.141631 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 117946.625966 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 117946.625966 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 123068.141631 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 123068.141631 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 123068.141631 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 123068.141631 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3494 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.562106 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1640,88 +1660,90 @@ system.iocache.writebacks::writebacks 36190 # nu system.iocache.writebacks::total 36190 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ide 233 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 233 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ide 233 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 233 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 233 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 233 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 16449877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 16449877 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4773782616 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4773782616 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 16449877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 16449877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 16449877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 16449877 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 17024877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 17024877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2461298579 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2461298579 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 17024877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 17024877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 17024877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 17024877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 70600.330472 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70600.330472 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131785.076634 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131785.076634 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 70600.330472 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70600.330472 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 70600.330472 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70600.330472 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73068.141631 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 73068.141631 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67946.625966 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67946.625966 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 73068.141631 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 73068.141631 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 73068.141631 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 73068.141631 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 68567 # Transaction distribution -system.membus.trans_dist::ReadResp 68566 # Transaction distribution +system.membus.trans_dist::ReadReq 34132 # Transaction distribution +system.membus.trans_dist::ReadResp 68549 # Transaction distribution system.membus.trans_dist::WriteReq 27584 # Transaction distribution system.membus.trans_dist::WriteResp 27584 # Transaction distribution -system.membus.trans_dist::Writeback 131056 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4579 # Transaction distribution +system.membus.trans_dist::Writeback 131071 # Transaction distribution +system.membus.trans_dist::CleanEvict 8154 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4580 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4581 # Transaction distribution -system.membus.trans_dist::ReadExReq 138681 # Transaction distribution -system.membus.trans_dist::ReadExResp 138681 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4582 # Transaction distribution +system.membus.trans_dist::ReadExReq 138564 # Transaction distribution +system.membus.trans_dist::ReadExResp 138564 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 34418 # Transaction distribution +system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 465382 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 572946 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108886 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108886 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 681832 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 473273 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 580837 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108898 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108898 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 689735 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17186044 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 17349437 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21984893 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17178284 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 17341677 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19658797 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 497 # Total snoops (count) -system.membus.snoop_fanout::samples 406751 # Request fanout histogram +system.membus.snoop_fanout::samples 414951 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 406751 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 414951 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 406751 # Request fanout histogram -system.membus.reqLayer0.occupancy 83856500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 414951 # Request fanout histogram +system.membus.reqLayer0.occupancy 83605000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1725500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1746000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1057992643 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 911806448 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1020413671 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1019741659 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 37506490 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64533936 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 3492b3590..22877557e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,154 +1,154 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.817778 # Number of seconds simulated -sim_ticks 2817777605000 # Number of ticks simulated -final_tick 2817777605000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.817750 # Number of seconds simulated +sim_ticks 2817750443000 # Number of ticks simulated +final_tick 2817750443000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 298084 # Simulator instruction rate (inst/s) -host_op_rate 361954 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6653597695 # Simulator tick rate (ticks/s) -host_mem_usage 624156 # Number of bytes of host memory used -host_seconds 423.50 # Real time elapsed on the host -sim_insts 126237777 # Number of instructions simulated -sim_ops 153286368 # Number of ops (including micro ops) simulated +host_inst_rate 301376 # Simulator instruction rate (inst/s) +host_op_rate 365951 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6727532391 # Simulator tick rate (ticks/s) +host_mem_usage 628096 # Number of bytes of host memory used +host_seconds 418.84 # Real time elapsed on the host +sim_insts 126227981 # Number of instructions simulated +sim_ops 153274395 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 655396 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4517280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 653732 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4510496 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 125824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1063044 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 5888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 519744 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 4071296 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 124544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1058884 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 5696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 520896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 4080320 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10959816 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 655396 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 125824 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 519744 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1300964 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8260864 # Number of bytes written to this memory +system.physmem.bytes_read::total 10955912 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 653732 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 124544 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 520896 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1299172 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8264128 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::total 8278388 # Number of bytes written to this memory +system.physmem.bytes_written::total 8281652 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 18694 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 71101 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 18668 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 70995 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1966 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 16611 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 92 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 8121 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 63614 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1946 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 16546 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 89 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 8139 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 63755 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 180220 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 129076 # Number of write requests responded to by this memory +system.physmem.num_reads::total 180159 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 129127 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::total 133457 # Number of write requests responded to by this memory +system.physmem.num_writes::total 133508 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 91 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 232593 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1603136 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 232005 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1600744 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 44654 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 377263 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 2090 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 184452 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1444861 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 44200 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 375791 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 2021 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 184862 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1448077 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 341 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3889525 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 232593 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 44654 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 184452 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 461699 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2931695 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3888177 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 232005 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 44200 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 184862 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 461067 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2932881 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6216 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2937914 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2931695 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2939101 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2932881 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 91 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 232593 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1609352 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 232005 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1606960 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 44654 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 377266 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 2090 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 184452 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1444861 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 44200 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 375793 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 2021 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 184862 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1448077 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 341 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6827439 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 90406 # Number of read requests accepted -system.physmem.writeReqs 90720 # Number of write requests accepted -system.physmem.readBursts 90406 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 90720 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5783616 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 2368 # Total number of bytes read from write queue -system.physmem.bytesWritten 4983552 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5785924 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5805960 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 37 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 12831 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 2411 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 5941 # Per bank write bursts -system.physmem.perBankRdBursts::1 5711 # Per bank write bursts -system.physmem.perBankRdBursts::2 5475 # Per bank write bursts -system.physmem.perBankRdBursts::3 5399 # Per bank write bursts -system.physmem.perBankRdBursts::4 5366 # Per bank write bursts -system.physmem.perBankRdBursts::5 5838 # Per bank write bursts -system.physmem.perBankRdBursts::6 6281 # Per bank write bursts -system.physmem.perBankRdBursts::7 6483 # Per bank write bursts -system.physmem.perBankRdBursts::8 6268 # Per bank write bursts -system.physmem.perBankRdBursts::9 6346 # Per bank write bursts -system.physmem.perBankRdBursts::10 5330 # Per bank write bursts -system.physmem.perBankRdBursts::11 5015 # Per bank write bursts -system.physmem.perBankRdBursts::12 5399 # Per bank write bursts -system.physmem.perBankRdBursts::13 5276 # Per bank write bursts -system.physmem.perBankRdBursts::14 4950 # Per bank write bursts -system.physmem.perBankRdBursts::15 5291 # Per bank write bursts -system.physmem.perBankWrBursts::0 4893 # Per bank write bursts -system.physmem.perBankWrBursts::1 4429 # Per bank write bursts -system.physmem.perBankWrBursts::2 4791 # Per bank write bursts -system.physmem.perBankWrBursts::3 4794 # Per bank write bursts -system.physmem.perBankWrBursts::4 4700 # Per bank write bursts -system.physmem.perBankWrBursts::5 5367 # Per bank write bursts -system.physmem.perBankWrBursts::6 5289 # Per bank write bursts -system.physmem.perBankWrBursts::7 5346 # Per bank write bursts -system.physmem.perBankWrBursts::8 5326 # Per bank write bursts -system.physmem.perBankWrBursts::9 5240 # Per bank write bursts -system.physmem.perBankWrBursts::10 4672 # Per bank write bursts -system.physmem.perBankWrBursts::11 4285 # Per bank write bursts -system.physmem.perBankWrBursts::12 5029 # Per bank write bursts -system.physmem.perBankWrBursts::13 5084 # Per bank write bursts -system.physmem.perBankWrBursts::14 4218 # Per bank write bursts -system.physmem.perBankWrBursts::15 4405 # Per bank write bursts +system.physmem.bw_total::total 6827277 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 90477 # Number of read requests accepted +system.physmem.writeReqs 65811 # Number of write requests accepted +system.physmem.readBursts 90477 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 65811 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5784832 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 5696 # Total number of bytes read from write queue +system.physmem.bytesWritten 4210432 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5790468 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4211784 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 89 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 1 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 23137 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 5834 # Per bank write bursts +system.physmem.perBankRdBursts::1 5704 # Per bank write bursts +system.physmem.perBankRdBursts::2 5463 # Per bank write bursts +system.physmem.perBankRdBursts::3 5405 # Per bank write bursts +system.physmem.perBankRdBursts::4 5372 # Per bank write bursts +system.physmem.perBankRdBursts::5 5837 # Per bank write bursts +system.physmem.perBankRdBursts::6 6284 # Per bank write bursts +system.physmem.perBankRdBursts::7 6486 # Per bank write bursts +system.physmem.perBankRdBursts::8 6223 # Per bank write bursts +system.physmem.perBankRdBursts::9 6339 # Per bank write bursts +system.physmem.perBankRdBursts::10 5440 # Per bank write bursts +system.physmem.perBankRdBursts::11 5142 # Per bank write bursts +system.physmem.perBankRdBursts::12 5381 # Per bank write bursts +system.physmem.perBankRdBursts::13 5279 # Per bank write bursts +system.physmem.perBankRdBursts::14 4952 # Per bank write bursts +system.physmem.perBankRdBursts::15 5247 # Per bank write bursts +system.physmem.perBankWrBursts::0 4133 # Per bank write bursts +system.physmem.perBankWrBursts::1 3840 # Per bank write bursts +system.physmem.perBankWrBursts::2 4117 # Per bank write bursts +system.physmem.perBankWrBursts::3 4118 # Per bank write bursts +system.physmem.perBankWrBursts::4 3952 # Per bank write bursts +system.physmem.perBankWrBursts::5 4415 # Per bank write bursts +system.physmem.perBankWrBursts::6 4512 # Per bank write bursts +system.physmem.perBankWrBursts::7 4650 # Per bank write bursts +system.physmem.perBankWrBursts::8 4383 # Per bank write bursts +system.physmem.perBankWrBursts::9 4609 # Per bank write bursts +system.physmem.perBankWrBursts::10 3956 # Per bank write bursts +system.physmem.perBankWrBursts::11 3578 # Per bank write bursts +system.physmem.perBankWrBursts::12 4192 # Per bank write bursts +system.physmem.perBankWrBursts::13 4199 # Per bank write bursts +system.physmem.perBankWrBursts::14 3505 # Per bank write bursts +system.physmem.perBankWrBursts::15 3629 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 38 # Number of times write queue was full causing retry -system.physmem.totGap 2816211460500 # Total gap between requests +system.physmem.numWrRetry 11 # Number of times write queue was full causing retry +system.physmem.totGap 2816184296500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 1 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 90405 # Read request sizes (log2) +system.physmem.readPktSize::6 90476 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 90718 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 59525 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 27440 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2853 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 545 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 65809 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 59474 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 27494 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2874 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 538 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -175,7 +175,7 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 58 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 55 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 54 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 52 # What write queue length does an incoming req see @@ -185,164 +185,165 @@ system.physmem.wrQLenPdf::6 51 # Wh system.physmem.wrQLenPdf::7 51 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 51 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 50 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 50 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 50 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 982 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3077 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3425 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 3919 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 3373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 3722 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 3652 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 3489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4724 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 3857 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 3769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 3569 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 777 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 667 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 820 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1468 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1438 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1082 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 925 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 725 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 575 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 105 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 33321 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 323.130758 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 184.789706 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 346.993140 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12624 37.89% 37.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 7779 23.35% 61.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3018 9.06% 70.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1714 5.14% 75.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1413 4.24% 79.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 752 2.26% 81.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 537 1.61% 83.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 554 1.66% 85.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4930 14.80% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 33321 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 2995 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 30.170618 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 514.809638 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 2993 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1098 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3358 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4984 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4451 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 3853 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4093 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 3437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 3376 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 3245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 42 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 32481 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 307.722545 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 177.643491 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 335.464678 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12661 38.98% 38.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 7717 23.76% 62.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 2982 9.18% 71.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1687 5.19% 77.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1406 4.33% 81.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 745 2.29% 83.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 513 1.58% 85.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 495 1.52% 86.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4275 13.16% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 32481 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 3213 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.128852 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 487.877717 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 3211 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.03% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::27648-28671 1 0.03% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 2995 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 2995 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 25.999332 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.796866 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 47.448084 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-15 17 0.57% 0.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 2784 92.95% 93.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 41 1.37% 94.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 11 0.37% 95.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 6 0.20% 95.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 14 0.47% 95.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 11 0.37% 96.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 12 0.40% 96.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 7 0.23% 96.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 11 0.37% 97.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 7 0.23% 97.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 15 0.50% 98.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 14 0.47% 98.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 4 0.13% 98.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 1 0.03% 98.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 2 0.07% 98.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 4 0.13% 98.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 3 0.10% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 3 0.10% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 6 0.20% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 1 0.03% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 6 0.20% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 5 0.17% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::400-415 1 0.03% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 2 0.07% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 2 0.07% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 3 0.10% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 1 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::576-591 1 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 2995 # Writes before turning the bus around for reads -system.physmem.totQLat 1193098984 # Total ticks spent queuing -system.physmem.totMemAccLat 2887517734 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 451845000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13202.53 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::26624-27647 1 0.03% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 3213 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 3213 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.475568 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.644293 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.368139 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 6 0.19% 0.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 1 0.03% 0.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 1 0.03% 0.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 2 0.06% 0.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 2703 84.13% 84.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 65 2.02% 86.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 109 3.39% 89.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 35 1.09% 90.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 33 1.03% 91.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 100 3.11% 95.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 9 0.28% 95.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 3 0.09% 95.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 4 0.12% 95.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 8 0.25% 95.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 2 0.06% 95.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 1 0.03% 95.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 103 3.21% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 2 0.06% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 3 0.09% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 4 0.12% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 1 0.03% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.06% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.03% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.03% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 7 0.22% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.03% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.06% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.06% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 3213 # Writes before turning the bus around for reads +system.physmem.totQLat 1180806250 # Total ticks spent queuing +system.physmem.totMemAccLat 2875581250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 451940000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13063.75 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31952.53 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 31813.75 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.05 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.77 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 1.49 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.05 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.06 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.49 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 4.64 # Average write queue length when enqueuing -system.physmem.readRowHits 74590 # Number of row buffer hits during reads -system.physmem.writeRowHits 60325 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.54 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.45 # Row buffer hit rate for writes -system.physmem.avgGap 15548355.62 # Average gap between requests -system.physmem.pageHitRate 80.18 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 130667040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 71094375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 362653200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 256666320 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 178852415040 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 68967490005 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1611945575250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1860586561230 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.497599 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2632498894488 # Time in different power states -system.physmem_0.memoryStateTime::REF 91437840000 # Time in different power states +system.physmem.avgWrQLen 6.07 # Average write queue length when enqueuing +system.physmem.readRowHits 74627 # Number of row buffer hits during reads +system.physmem.writeRowHits 49067 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.56 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.56 # Row buffer hit rate for writes +system.physmem.avgGap 18019197.23 # Average gap between requests +system.physmem.pageHitRate 79.19 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 128285640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 69757875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 361803000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 218615760 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 178850889360 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 68913339435 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1610809853250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1859352544320 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.527151 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2632589257000 # Time in different power states +system.physmem_0.memoryStateTime::REF 91437060000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 14475823012 # Time in different power states +system.physmem_0.memoryStateTime::ACT 14382937750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 121239720 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 65934000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 342209400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 247918320 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 178852415040 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 68215091715 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1611413256750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1859258064945 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.496864 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2633620948492 # Time in different power states -system.physmem_1.memoryStateTime::REF 91437840000 # Time in different power states +system.physmem_1.actEnergy 117270720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 63772500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 343207800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 207690480 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 178850889360 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 68192676180 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1609047407250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1856822914290 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.575499 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2633644277500 # Time in different power states +system.physmem_1.memoryStateTime::REF 91437060000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 13360607258 # Time in different power states +system.physmem_1.memoryStateTime::ACT 13328364750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -392,48 +393,48 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 5755 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 5755 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 5755 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 5755 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 5755 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walksPending::samples 166069431868 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.475663 # Table walker pending requests distribution +system.cpu0.dtb.walker.walks 5725 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 5725 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 5725 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 5725 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 5725 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 166068997868 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.475665 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::stdev 0.499407 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 87076283368 52.43% 52.43% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 78993148500 47.57% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 166069431868 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 3189 67.65% 67.65% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1525 32.35% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 4714 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5755 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walksPending::0 87075845118 52.43% 52.43% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 78993152750 47.57% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 166068997868 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 3165 67.41% 67.41% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1530 32.59% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 4695 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5725 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5755 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4714 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5725 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4695 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4714 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 10469 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4695 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 10420 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 14452204 # DTB read hits -system.cpu0.dtb.read_misses 4833 # DTB read misses -system.cpu0.dtb.write_hits 11089888 # DTB write hits -system.cpu0.dtb.write_misses 922 # DTB write misses -system.cpu0.dtb.flush_tlb 189 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 445 # Number of times TLB was flushed by MVA +system.cpu0.dtb.read_hits 14454415 # DTB read hits +system.cpu0.dtb.read_misses 4808 # DTB read misses +system.cpu0.dtb.write_hits 11087884 # DTB write hits +system.cpu0.dtb.write_misses 917 # DTB write misses +system.cpu0.dtb.flush_tlb 190 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 446 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3319 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3341 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 937 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 964 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 217 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 14457037 # DTB read accesses -system.cpu0.dtb.write_accesses 11090810 # DTB write accesses +system.cpu0.dtb.perms_faults 218 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 14459223 # DTB read accesses +system.cpu0.dtb.write_accesses 11088801 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 25542092 # DTB hits -system.cpu0.dtb.misses 5755 # DTB misses -system.cpu0.dtb.accesses 25547847 # DTB accesses +system.cpu0.dtb.hits 25542299 # DTB hits +system.cpu0.dtb.misses 5725 # DTB misses +system.cpu0.dtb.accesses 25548024 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -463,35 +464,35 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 2817 # Table walker walks requested -system.cpu0.itb.walker.walksShort 2817 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walkWaitTime::samples 2817 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 2817 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 2817 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walksPending::samples 166069431868 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.475664 # Table walker pending requests distribution +system.cpu0.itb.walker.walks 2784 # Table walker walks requested +system.cpu0.itb.walker.walksShort 2784 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walkWaitTime::samples 2784 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 2784 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 2784 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 166068997868 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.475665 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::stdev 0.499407 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 87076165368 52.43% 52.43% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 78993266500 47.57% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 166069431868 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1542 75.55% 75.55% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 499 24.45% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2041 # Table walker page sizes translated +system.cpu0.itb.walker.walksPending::0 87075735118 52.43% 52.43% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 78993262750 47.57% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 166068997868 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1521 75.19% 75.19% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 502 24.81% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2023 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2817 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2817 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2784 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2784 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2041 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2041 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 4858 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 67891248 # ITB inst hits -system.cpu0.itb.inst_misses 2817 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2023 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2023 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 4807 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 67912569 # ITB inst hits +system.cpu0.itb.inst_misses 2784 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 189 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 445 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb 190 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 446 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu0.itb.flush_entries 2012 # Number of entries that have been flushed from TLB @@ -501,504 +502,504 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 67894065 # ITB inst accesses -system.cpu0.itb.hits 67891248 # DTB hits -system.cpu0.itb.misses 2817 # DTB misses -system.cpu0.itb.accesses 67894065 # DTB accesses -system.cpu0.numCycles 82517225 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 67915353 # ITB inst accesses +system.cpu0.itb.hits 67912569 # DTB hits +system.cpu0.itb.misses 2784 # DTB misses +system.cpu0.itb.accesses 67915353 # DTB accesses +system.cpu0.numCycles 82537208 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 66111161 # Number of instructions committed -system.cpu0.committedOps 80627134 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 70885778 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5615 # Number of float alu accesses -system.cpu0.num_func_calls 7285085 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 8754092 # number of instructions that are conditional controls -system.cpu0.num_int_insts 70885778 # number of integer instructions -system.cpu0.num_fp_insts 5615 # number of float instructions -system.cpu0.num_int_register_reads 131498293 # number of times the integer registers were read -system.cpu0.num_int_register_writes 49310474 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 4327 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1292 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 245812611 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 29370316 # number of times the CC registers were written -system.cpu0.num_mem_refs 26208491 # number of memory refs -system.cpu0.num_load_insts 14628012 # Number of load instructions -system.cpu0.num_store_insts 11580479 # Number of store instructions -system.cpu0.num_idle_cycles 77919171.769514 # Number of idle cycles -system.cpu0.num_busy_cycles 4598053.230486 # Number of busy cycles -system.cpu0.not_idle_fraction 0.055722 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.944278 # Percentage of idle cycles -system.cpu0.Branches 16437108 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2194 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 55772206 67.98% 67.98% # Class of executed instruction -system.cpu0.op_class::IntMult 58001 0.07% 68.05% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 4497 0.01% 68.06% # Class of executed instruction +system.cpu0.committedInsts 66134007 # Number of instructions committed +system.cpu0.committedOps 80648826 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 70905199 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5550 # Number of float alu accesses +system.cpu0.num_func_calls 7283350 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 8754499 # number of instructions that are conditional controls +system.cpu0.num_int_insts 70905199 # number of integer instructions +system.cpu0.num_fp_insts 5550 # number of float instructions +system.cpu0.num_int_register_reads 131519590 # number of times the integer registers were read +system.cpu0.num_int_register_writes 49325288 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 4326 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1228 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 245878640 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 29383702 # number of times the CC registers were written +system.cpu0.num_mem_refs 26210186 # number of memory refs +system.cpu0.num_load_insts 14630349 # Number of load instructions +system.cpu0.num_store_insts 11579837 # Number of store instructions +system.cpu0.num_idle_cycles 77938505.493998 # Number of idle cycles +system.cpu0.num_busy_cycles 4598702.506002 # Number of busy cycles +system.cpu0.not_idle_fraction 0.055717 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.944283 # Percentage of idle cycles +system.cpu0.Branches 16436363 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2195 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 55791644 67.98% 67.99% # Class of executed instruction +system.cpu0.op_class::IntMult 58049 0.07% 68.06% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 4498 0.01% 68.06% # Class of executed instruction system.cpu0.op_class::SimdFloatMult 0 0.00% 68.06% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.06% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::MemRead 14628012 17.83% 85.89% # Class of executed instruction -system.cpu0.op_class::MemWrite 11580479 14.11% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 14630349 17.83% 85.89% # Class of executed instruction +system.cpu0.op_class::MemWrite 11579837 14.11% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 82045389 # Class of executed instruction +system.cpu0.op_class::total 82066572 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 3057 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 831864 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.997018 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 47054976 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 832376 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 56.530914 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 3052 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 831549 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.997019 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 47051301 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 832061 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 56.547899 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 485.861119 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 16.669659 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 9.466239 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.948947 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.032558 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.018489 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 485.952083 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 16.619501 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 9.425436 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.949125 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.032460 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.018409 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 302 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 198551178 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 198551178 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 13770345 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 4433242 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 8498402 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 26701989 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 10695058 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 3174725 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 5187481 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 19057264 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 188196 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 61394 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 132351 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 381941 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 234602 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 80377 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 136196 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 451175 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236074 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 82808 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 140857 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 459739 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 24465403 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 7607967 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 13685883 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 45759253 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 24653599 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 7669361 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 13818234 # number of overall hits -system.cpu0.dcache.overall_hits::total 46141194 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 187937 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 59498 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 318451 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 565886 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 147418 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 35026 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 1470502 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1652946 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 54526 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 20446 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu2.data 66281 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 141253 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 4541 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 3227 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 9714 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 17482 # number of LoadLockedReq misses +system.cpu0.dcache.tags.tag_accesses 198549695 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 198549695 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 13772496 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 4439535 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 8487535 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 26699566 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 10693159 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 3177520 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 5185286 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 19055965 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 188127 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 61521 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu2.data 132231 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 381879 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 234713 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 80499 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 136030 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 451242 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236172 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 82928 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 140692 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 459792 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 24465655 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 7617055 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 13672821 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 45755531 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 24653782 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 7678576 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 13805052 # number of overall hits +system.cpu0.dcache.overall_hits::total 46137410 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 187736 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 59438 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 321333 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 568507 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 147259 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 35061 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 1471187 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1653507 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 54734 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 20499 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu2.data 66219 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 141452 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 4535 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 3220 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 9718 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 17473 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 3 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::cpu2.data 16 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 19 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 335355 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 94524 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1788953 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2218832 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 389881 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 114970 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1855234 # number of overall misses -system.cpu0.dcache.overall_misses::total 2360085 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 914696992 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 4873257385 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5787954377 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1450684328 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 71024926938 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 72475611266 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 43850500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 129200998 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 173051498 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 333505 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 333505 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 2365381320 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 75898184323 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 78263565643 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 2365381320 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 75898184323 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 78263565643 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 13958282 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 4492740 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 8816853 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 27267875 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 10842476 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 3209751 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 6657983 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 20710210 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 242722 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 81840 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 198632 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 523194 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 239143 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 83604 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 145910 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 468657 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 236077 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 82808 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 140873 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 459758 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 24800758 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 7702491 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 15474836 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 47978085 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 25043480 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 7784331 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 15673468 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 48501279 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.013464 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.013243 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.036118 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.020753 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.013596 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.010912 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.220863 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.079813 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224644 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.249829 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.333687 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.269982 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.018989 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.038599 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.066575 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.037302 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_misses::cpu0.data 334995 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 94499 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 1792520 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2222014 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 389729 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 114998 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 1858739 # number of overall misses +system.cpu0.dcache.overall_misses::total 2363466 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 910326500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 4892855500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5803182000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1430484500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 70357084944 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 71787569444 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 43754500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 128953000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 172707500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 313500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 313500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 2340811000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 75249940444 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 77590751444 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 2340811000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 75249940444 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 77590751444 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 13960232 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 4498973 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 8808868 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 27268073 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 10840418 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 3212581 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 6656473 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 20709472 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 242861 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 82020 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 198450 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 523331 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 239248 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 83719 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 145748 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 468715 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 236175 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 82928 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 140708 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 459811 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 24800650 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 7711554 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 15465341 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 47977545 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 25043511 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 7793574 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 15663791 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 48500876 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.013448 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.013211 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.036478 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.020849 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.013584 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.010914 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.221016 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.079843 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.225372 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.249927 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.333681 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.270292 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.018955 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.038462 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.066677 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.037279 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000013 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000114 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000041 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.013522 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.012272 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.115604 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.046247 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.015568 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.014769 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.118368 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.048660 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15373.575448 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15303.005439 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 10228.127886 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 41417.356478 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 48299.782617 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 43846.327264 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13588.627208 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13300.493926 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9898.838691 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 20844.062500 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 17552.894737 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 25024.134823 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 42426.035968 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 35272.416137 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 20573.900322 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 40910.302594 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33161.333445 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 378962 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 29004 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 19067 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 710 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 19.875282 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 40.850704 # average number of cycles each access was blocked +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.013508 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.012254 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.115906 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.046314 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.015562 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.014755 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.118665 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.048730 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15315.564117 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15226.744530 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 10207.758216 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 40799.877357 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 47823.346008 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 43415.340512 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13588.354037 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13269.499897 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9884.249986 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 19593.750000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16500 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 24770.748897 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 41979.972577 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 34919.110070 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 20355.232265 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 40484.403913 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 32829.222610 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 384529 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 27036 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 18388 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 711 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 20.911953 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 38.025316 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 690587 # number of writebacks -system.cpu0.dcache.writebacks::total 690587 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 87 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 157237 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 157324 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 1353907 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1353907 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 1937 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 6801 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 8738 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 87 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 1511144 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1511231 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 87 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 1511144 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1511231 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 59411 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 161214 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 220625 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 35026 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 116595 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 151621 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 20077 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 44216 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 64293 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1290 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 2913 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 4203 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.writebacks::writebacks 690633 # number of writebacks +system.cpu0.dcache.writebacks::total 690633 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 93 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 159890 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 159983 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 1354576 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1354576 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 1940 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 6930 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 8870 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 93 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 1514466 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1514559 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 93 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 1514466 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1514559 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 59345 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 161443 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 220788 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 35061 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 116611 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 151672 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 20123 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 43935 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 64058 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1280 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 2788 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 4068 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 16 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 16 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 94437 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 277809 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 372246 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 114514 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 322025 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 436539 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 5880 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 8599 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 14479 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 4601 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 6739 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 11340 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 10481 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 15338 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 25819 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 823130250 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 2155055358 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2978185608 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1391922672 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 5640631884 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7032554556 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 264066008 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 576983002 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 841049010 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19999250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 37322251 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 57321501 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 309495 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 309495 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 2215052922 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7795687242 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10010740164 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 2479118930 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 8372670244 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10851789174 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1043159500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1692820000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2735979500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 803109000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1311241000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2114350000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1846268500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 3004061000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4850329500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013224 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018285 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.008091 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.010912 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.017512 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007321 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.245320 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.222603 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.122886 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.015430 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.019964 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.008968 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 94406 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 278054 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 372460 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 114529 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 321989 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 436518 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 5882 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 8601 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 14483 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 4590 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 6802 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 11392 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 10472 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 15403 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 25875 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 849299000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 2242226500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3091525500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1395423500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 5679297435 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7074720935 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 276712000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 590115500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 866827500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 20457500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 37492500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 57950000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 297500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 297500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 2244722500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7921523935 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10166246435 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 2521434500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 8511639435 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11033073935 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1056963000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1715153500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2772116500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 811573000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1342286000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2153859000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1868536000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 3057439500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4925975500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013191 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018327 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.008097 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.010914 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.017518 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007324 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.245343 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.221391 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.122404 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.015289 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.019129 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.008679 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000114 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000035 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.012261 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.017952 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.007759 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.014711 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.020546 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.009001 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13854.845904 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13367.668800 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13498.858280 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39739.698281 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 48377.991200 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46382.457285 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13152.662649 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 13049.190384 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13081.502030 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15503.294574 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12812.307243 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13638.234832 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 19343.437500 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19343.437500 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23455.350361 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 28061.319979 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26892.807885 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21649.046667 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 26000.062865 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24858.693436 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 177408.078231 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 196862.425863 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 188961.910353 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 174550.967181 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 194575.011129 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 186450.617284 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 176153.849823 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 195857.412961 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 187858.921724 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.012242 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.017979 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.007763 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.014695 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.020556 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.009000 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14311.214087 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13888.657297 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14002.235176 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39799.877357 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 48702.930555 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46644.871400 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13751.031158 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 13431.557983 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13531.916388 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15982.421875 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 13447.812052 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14245.329400 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 18593.750000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18593.750000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23777.328771 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 28489.156549 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27294.867731 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22015.685983 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 26434.565886 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25275.186670 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 179694.491670 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 199413.265899 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191404.853967 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 176813.289760 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 197336.959718 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189067.679073 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 178431.627196 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 198496.364345 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 190375.864734 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1799096 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.534039 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 100909280 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1799607 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 56.072954 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 10982089250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 477.173904 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 21.006307 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 13.353828 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.931980 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.041028 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.026082 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999090 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 1799604 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.542681 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 100855692 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1800115 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 56.027360 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 10987259500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 478.414957 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 20.920922 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 12.206802 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.934404 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.040861 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.023841 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999107 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 243 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 154 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 236 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 157 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 104560332 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 104560332 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 67029897 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 21781554 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 12097829 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 100909280 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 67029897 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 21781554 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 12097829 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 100909280 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 67029897 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 21781554 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 12097829 # number of overall hits -system.cpu0.icache.overall_hits::total 100909280 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 863392 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 250227 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 737787 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1851406 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 863392 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 250227 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 737787 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1851406 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 863392 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 250227 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 737787 # number of overall misses -system.cpu0.icache.overall_misses::total 1851406 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 3390224750 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 10026619709 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13416844459 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 3390224750 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 10026619709 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13416844459 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 3390224750 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 10026619709 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13416844459 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 67893289 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 22031781 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 12835616 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 102760686 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 67893289 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 22031781 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 12835616 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 102760686 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 67893289 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 22031781 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 12835616 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 102760686 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012717 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011358 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.057480 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.018017 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012717 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011358 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.057480 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.018017 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.012717 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011358 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.057480 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.018017 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13548.596874 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13590.127922 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 7246.840757 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13548.596874 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13590.127922 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 7246.840757 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13548.596874 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13590.127922 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 7246.840757 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 7212 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 104509492 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 104509492 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 67050712 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 21807219 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 11997761 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 100855692 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 67050712 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 21807219 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 11997761 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 100855692 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 67050712 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 21807219 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 11997761 # number of overall hits +system.cpu0.icache.overall_hits::total 100855692 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 863880 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 249894 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 739869 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1853643 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 863880 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 249894 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 739869 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1853643 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 863880 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 249894 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 739869 # number of overall misses +system.cpu0.icache.overall_misses::total 1853643 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 3388286000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 10019746984 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 13408032984 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 3388286000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 10019746984 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 13408032984 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 3388286000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 10019746984 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 13408032984 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 67914592 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 22057113 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 12737630 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 102709335 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 67914592 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 22057113 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 12737630 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 102709335 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 67914592 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 22057113 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 12737630 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 102709335 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012720 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011329 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.058085 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.018047 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012720 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011329 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.058085 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.018047 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.012720 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011329 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.058085 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.018047 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13558.892971 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13542.596033 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 7233.341579 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13558.892971 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13542.596033 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 7233.341579 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13558.892971 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13542.596033 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 7233.341579 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 7691 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 416 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 418 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.336538 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.399522 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 51759 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 51759 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 51759 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 51759 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 51759 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 51759 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 250227 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 686028 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 936255 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 250227 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 686028 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 936255 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 250227 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 686028 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 936255 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 3014176750 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 8498569729 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11512746479 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 3014176750 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 8498569729 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11512746479 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 3014176750 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 8498569729 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11512746479 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011358 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.053447 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009111 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.011358 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.053447 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.009111 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.011358 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.053447 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.009111 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12045.769441 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12388.079975 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12296.592786 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12045.769441 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12388.079975 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12296.592786 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12045.769441 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12388.079975 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12296.592786 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 53485 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 53485 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 53485 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 53485 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 53485 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 53485 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 249894 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 686384 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 936278 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 249894 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 686384 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 936278 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 249894 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 686384 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 936278 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 3138392000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 8843257984 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11981649984 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 3138392000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 8843257984 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11981649984 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 3138392000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 8843257984 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11981649984 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011329 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.053886 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009116 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.011329 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.053886 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.009116 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.011329 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.053886 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.009116 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12558.892971 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12883.834681 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12797.107252 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12558.892971 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12883.834681 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12797.107252 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12558.892971 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12883.834681 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12797.107252 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1029,56 +1030,56 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 1874 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 1874 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 637 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1237 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 1874 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 1874 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 1874 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 1601 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 12056.839475 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 10248.777265 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 6448.828751 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 390 24.36% 24.36% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 856 53.47% 77.83% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 354 22.11% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walks 1911 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 1911 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 628 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1283 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 1911 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 1911 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 1911 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 1624 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 12817.118227 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 11165.640992 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6539.405372 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 417 25.68% 25.68% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 849 52.28% 77.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 357 21.98% 99.94% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::81920-90111 1 0.06% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 1601 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 1000015500 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1000015500 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 1000015500 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 972 60.71% 60.71% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 629 39.29% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 1601 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 1874 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkCompletionTime::total 1624 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1000016000 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1000016000 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1000016000 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1004 61.82% 61.82% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 620 38.18% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 1624 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 1911 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 1874 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1601 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 1911 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1624 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1601 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 3475 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1624 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 3535 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 4664064 # DTB read hits -system.cpu1.dtb.read_misses 1628 # DTB read misses -system.cpu1.dtb.write_hits 3297220 # DTB write hits -system.cpu1.dtb.write_misses 246 # DTB write misses -system.cpu1.dtb.flush_tlb 168 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 112 # Number of times TLB was flushed by MVA +system.cpu1.dtb.read_hits 4670594 # DTB read hits +system.cpu1.dtb.read_misses 1655 # DTB read misses +system.cpu1.dtb.write_hits 3300164 # DTB write hits +system.cpu1.dtb.write_misses 256 # DTB write misses +system.cpu1.dtb.flush_tlb 167 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 123 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1307 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1332 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 257 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 252 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 60 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 4665692 # DTB read accesses -system.cpu1.dtb.write_accesses 3297466 # DTB write accesses +system.cpu1.dtb.perms_faults 65 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 4672249 # DTB read accesses +system.cpu1.dtb.write_accesses 3300420 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 7961284 # DTB hits -system.cpu1.dtb.misses 1874 # DTB misses -system.cpu1.dtb.accesses 7963158 # DTB accesses +system.cpu1.dtb.hits 7970758 # DTB hits +system.cpu1.dtb.misses 1911 # DTB misses +system.cpu1.dtb.accesses 7972669 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1108,128 +1109,128 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 876 # Table walker walks requested -system.cpu1.itb.walker.walksShort 876 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 230 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 646 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 876 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 876 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 876 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 692 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 12877.167630 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 11119.022104 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 6272.001420 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::2048-4095 140 20.23% 20.23% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::10240-12287 230 33.24% 53.47% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-14335 143 20.66% 74.13% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-22527 156 22.54% 96.68% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::22528-24575 23 3.32% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 692 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 935 # Table walker walks requested +system.cpu1.itb.walker.walksShort 935 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 229 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 706 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 935 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 935 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 935 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 723 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 13501.383126 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 11823.554991 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 6487.735992 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-6143 166 22.96% 22.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::10240-12287 228 31.54% 54.50% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-14335 139 19.23% 73.72% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::14336-16383 7 0.97% 74.69% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::22528-24575 183 25.31% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 723 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 462 66.76% 66.76% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 230 33.24% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 692 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 494 68.33% 68.33% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 229 31.67% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 723 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 876 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 876 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 935 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 935 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 692 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 692 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 1568 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 22031781 # ITB inst hits -system.cpu1.itb.inst_misses 876 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 723 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 723 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 1658 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 22057113 # ITB inst hits +system.cpu1.itb.inst_misses 935 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 168 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 112 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb 167 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 123 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 752 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 783 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 22032657 # ITB inst accesses -system.cpu1.itb.hits 22031781 # DTB hits -system.cpu1.itb.misses 876 # DTB misses -system.cpu1.itb.accesses 22032657 # DTB accesses -system.cpu1.numCycles 158012603 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 22058048 # ITB inst accesses +system.cpu1.itb.hits 22057113 # DTB hits +system.cpu1.itb.misses 935 # DTB misses +system.cpu1.itb.accesses 22058048 # DTB accesses +system.cpu1.numCycles 158011873 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 21317281 # Number of instructions committed -system.cpu1.committedOps 25549926 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 22701009 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 1608 # Number of float alu accesses -system.cpu1.num_func_calls 2410952 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2737582 # number of instructions that are conditional controls -system.cpu1.num_int_insts 22701009 # number of integer instructions -system.cpu1.num_fp_insts 1608 # number of float instructions -system.cpu1.num_int_register_reads 41843043 # number of times the integer registers were read -system.cpu1.num_int_register_writes 15920660 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1288 # number of times the floating registers were read +system.cpu1.committedInsts 21342205 # Number of instructions committed +system.cpu1.committedOps 25582989 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 22730381 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 1657 # Number of float alu accesses +system.cpu1.num_func_calls 2417962 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2740367 # number of instructions that are conditional controls +system.cpu1.num_int_insts 22730381 # number of integer instructions +system.cpu1.num_fp_insts 1657 # number of float instructions +system.cpu1.num_int_register_reads 41903720 # number of times the integer registers were read +system.cpu1.num_int_register_writes 15946634 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1337 # number of times the floating registers were read system.cpu1.num_fp_register_writes 320 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 92840963 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 9448697 # number of times the CC registers were written -system.cpu1.num_mem_refs 8172131 # number of memory refs -system.cpu1.num_load_insts 4710232 # Number of load instructions -system.cpu1.num_store_insts 3461899 # Number of store instructions -system.cpu1.num_idle_cycles 151539718.287508 # Number of idle cycles -system.cpu1.num_busy_cycles 6472884.712492 # Number of busy cycles -system.cpu1.not_idle_fraction 0.040964 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.959036 # Percentage of idle cycles -system.cpu1.Branches 5298424 # Number of branches fetched -system.cpu1.op_class::No_OpClass 41 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 18071289 68.81% 68.81% # Class of executed instruction -system.cpu1.op_class::IntMult 19339 0.07% 68.88% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 1186 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::MemRead 4710232 17.93% 86.82% # Class of executed instruction -system.cpu1.op_class::MemWrite 3461899 13.18% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 92962985 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 9452948 # number of times the CC registers were written +system.cpu1.num_mem_refs 8180627 # number of memory refs +system.cpu1.num_load_insts 4716601 # Number of load instructions +system.cpu1.num_store_insts 3464026 # Number of store instructions +system.cpu1.num_idle_cycles 151538894.643419 # Number of idle cycles +system.cpu1.num_busy_cycles 6472978.356581 # Number of busy cycles +system.cpu1.not_idle_fraction 0.040965 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.959035 # Percentage of idle cycles +system.cpu1.Branches 5307887 # Number of branches fetched +system.cpu1.op_class::No_OpClass 38 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 18096671 68.81% 68.81% # Class of executed instruction +system.cpu1.op_class::IntMult 19327 0.07% 68.89% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 1187 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::MemRead 4716601 17.94% 86.83% # Class of executed instruction +system.cpu1.op_class::MemWrite 3464026 13.17% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 26263986 # Class of executed instruction +system.cpu1.op_class::total 26297850 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 17390044 # Number of BP lookups -system.cpu2.branchPred.condPredicted 9451928 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 400737 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 10830418 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 8125283 # Number of BTB hits +system.cpu2.branchPred.lookups 17205761 # Number of BP lookups +system.cpu2.branchPred.condPredicted 9385761 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 401350 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 10751395 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 8022189 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 75.022802 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 4068079 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 21097 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 74.615331 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 4025562 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 21207 # Number of incorrect RAS predictions. system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1259,88 +1260,89 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.dtb.walker.walks 43271 # Table walker walks requested -system.cpu2.dtb.walker.walksShort 43271 # Table walker walks initiated with short descriptors -system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 13795 # Level at which table walker walks with short descriptors terminate -system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 11030 # Level at which table walker walks with short descriptors terminate -system.cpu2.dtb.walker.walksSquashedBefore 18446 # Table walks squashed before starting -system.cpu2.dtb.walker.walkWaitTime::samples 24825 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::mean 526.888218 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::stdev 3382.784717 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::0-16383 24602 99.10% 99.10% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::16384-32767 180 0.73% 99.83% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::32768-49151 23 0.09% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::49152-65535 14 0.06% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::65536-81919 3 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walks 43873 # Table walker walks requested +system.cpu2.dtb.walker.walksShort 43873 # Table walker walks initiated with short descriptors +system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 13923 # Level at which table walker walks with short descriptors terminate +system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 10993 # Level at which table walker walks with short descriptors terminate +system.cpu2.dtb.walker.walksSquashedBefore 18957 # Table walks squashed before starting +system.cpu2.dtb.walker.walkWaitTime::samples 24916 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::mean 571.078825 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::stdev 3693.718026 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::0-16383 24688 99.08% 99.08% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::16384-32767 176 0.71% 99.79% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::32768-49151 30 0.12% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::49152-65535 9 0.04% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::65536-81919 9 0.04% 99.98% # Table walker wait (enqueue to first request) latency system.cpu2.dtb.walker.walkWaitTime::81920-98303 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::98304-114687 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::98304-114687 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::114688-131071 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu2.dtb.walker.walkWaitTime::131072-147455 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::total 24825 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkCompletionTime::samples 9018 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::mean 12445.276336 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::gmean 10074.043051 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::stdev 7598.717395 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::0-8191 2712 30.07% 30.07% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::8192-16383 3866 42.87% 72.94% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::16384-24575 2205 24.45% 97.39% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::24576-32767 103 1.14% 98.54% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::32768-40959 58 0.64% 99.18% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::40960-49151 71 0.79% 99.97% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::49152-57343 1 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::57344-65535 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkWaitTime::total 24916 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkCompletionTime::samples 9164 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::mean 13158.828023 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::gmean 10878.635204 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::stdev 7680.126787 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::0-8191 2739 29.89% 29.89% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::8192-16383 3883 42.37% 72.26% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::16384-24575 2316 25.27% 97.53% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::24576-32767 72 0.79% 98.32% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::32768-40959 91 0.99% 99.31% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::40960-49151 60 0.65% 99.97% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::57344-65535 1 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::65536-73727 1 0.01% 99.99% # Table walker service (enqueue to completion) latency system.cpu2.dtb.walker.walkCompletionTime::81920-90111 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::total 9018 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walksPending::samples 60407494468 # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::mean 0.614556 # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::stdev 0.505382 # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::0-1 60349981968 99.90% 99.90% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::2-3 42488500 0.07% 99.98% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::4-5 7802000 0.01% 99.99% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::6-7 2924500 0.00% 99.99% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::8-9 1368500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::10-11 844500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::12-13 331000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::14-15 1040000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::16-17 124500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::18-19 121000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::20-21 186000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::22-23 81500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::24-25 109000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::26-27 11000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walkCompletionTime::total 9164 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walksPending::samples 60380803468 # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::mean 0.564289 # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::stdev 0.516018 # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::0-1 60322207968 99.90% 99.90% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::2-3 41747500 0.07% 99.97% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::4-5 8670500 0.01% 99.99% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::6-7 3297500 0.01% 99.99% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::8-9 1514000 0.00% 99.99% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::10-11 972000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::12-13 454500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::14-15 1161000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::16-17 173500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::18-19 164000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::20-21 123500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::22-23 89000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::24-25 134500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::26-27 15500 0.00% 100.00% # Table walker pending requests distribution system.cpu2.dtb.walker.walksPending::28-29 5500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::30-31 75000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::total 60407494468 # Table walker pending requests distribution -system.cpu2.dtb.walker.walkPageSizes::4K 2796 73.35% 73.35% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::1M 1016 26.65% 100.00% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::total 3812 # Table walker page sizes translated -system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 43271 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walksPending::30-31 73000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::total 60380803468 # Table walker pending requests distribution +system.cpu2.dtb.walker.walkPageSizes::4K 2766 73.10% 73.10% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::1M 1018 26.90% 100.00% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::total 3784 # Table walker page sizes translated +system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 43873 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 43271 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 3812 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 43873 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 3784 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 3812 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin::total 47083 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 3784 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin::total 47657 # Table walker requests started/completed, data/inst system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 9630626 # DTB read hits -system.cpu2.dtb.read_misses 37535 # DTB read misses -system.cpu2.dtb.write_hits 7130235 # DTB write hits -system.cpu2.dtb.write_misses 5736 # DTB write misses +system.cpu2.dtb.read_hits 9620013 # DTB read hits +system.cpu2.dtb.read_misses 37991 # DTB read misses +system.cpu2.dtb.write_hits 7129568 # DTB write hits +system.cpu2.dtb.write_misses 5882 # DTB write misses system.cpu2.dtb.flush_tlb 179 # Number of times complete TLB was flushed -system.cpu2.dtb.flush_tlb_mva 360 # Number of times TLB was flushed by MVA +system.cpu2.dtb.flush_tlb_mva 348 # Number of times TLB was flushed by MVA system.cpu2.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 2330 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 520 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 952 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 2312 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 478 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 974 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 414 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 9668161 # DTB read accesses -system.cpu2.dtb.write_accesses 7135971 # DTB write accesses +system.cpu2.dtb.perms_faults 415 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 9658004 # DTB read accesses +system.cpu2.dtb.write_accesses 7135450 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 16760861 # DTB hits -system.cpu2.dtb.misses 43271 # DTB misses -system.cpu2.dtb.accesses 16804132 # DTB accesses +system.cpu2.dtb.hits 16749581 # DTB hits +system.cpu2.dtb.misses 43873 # DTB misses +system.cpu2.dtb.accesses 16793454 # DTB accesses system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1370,395 +1372,392 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.walker.walks 6235 # Table walker walks requested -system.cpu2.itb.walker.walksShort 6235 # Table walker walks initiated with short descriptors -system.cpu2.itb.walker.walksShortTerminationLevel::Level1 2044 # Level at which table walker walks with short descriptors terminate -system.cpu2.itb.walker.walksShortTerminationLevel::Level2 4088 # Level at which table walker walks with short descriptors terminate -system.cpu2.itb.walker.walksSquashedBefore 103 # Table walks squashed before starting -system.cpu2.itb.walker.walkWaitTime::samples 6132 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::mean 1114.562948 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::stdev 4869.153513 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::0-8191 5831 95.09% 95.09% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::8192-16383 152 2.48% 97.57% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::16384-24575 99 1.61% 99.18% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::24576-32767 29 0.47% 99.66% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::32768-40959 9 0.15% 99.80% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::40960-49151 4 0.07% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::49152-57343 3 0.05% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::57344-65535 1 0.02% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::65536-73727 2 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::90112-98303 1 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::106496-114687 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::total 6132 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkCompletionTime::samples 1857 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::mean 12539.311255 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::gmean 10038.361952 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::stdev 8040.211817 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::0-4095 547 29.46% 29.46% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::4096-8191 43 2.32% 31.77% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::8192-12287 410 22.08% 53.85% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::12288-16383 373 20.09% 73.94% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::16384-20479 9 0.48% 74.42% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::20480-24575 413 22.24% 96.66% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::24576-28671 14 0.75% 97.42% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::28672-32767 13 0.70% 98.12% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::32768-36863 11 0.59% 98.71% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::36864-40959 8 0.43% 99.14% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::40960-45055 10 0.54% 99.68% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::45056-49151 1 0.05% 99.73% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::49152-53247 1 0.05% 99.78% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::53248-57343 2 0.11% 99.89% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::57344-61439 1 0.05% 99.95% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::61440-65535 1 0.05% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::total 1857 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walksPending::samples 13162833212 # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::mean 0.828087 # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::stdev 0.377922 # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::0 2265327000 17.21% 17.21% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::1 10895443212 82.77% 99.98% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::2 1802500 0.01% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::3 162000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::4 51500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::5 47000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::total 13162833212 # Table walker pending requests distribution -system.cpu2.itb.walker.walkPageSizes::4K 1358 77.42% 77.42% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::1M 396 22.58% 100.00% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::total 1754 # Table walker page sizes translated +system.cpu2.itb.walker.walks 5947 # Table walker walks requested +system.cpu2.itb.walker.walksShort 5947 # Table walker walks initiated with short descriptors +system.cpu2.itb.walker.walksShortTerminationLevel::Level1 1786 # Level at which table walker walks with short descriptors terminate +system.cpu2.itb.walker.walksShortTerminationLevel::Level2 4054 # Level at which table walker walks with short descriptors terminate +system.cpu2.itb.walker.walksSquashedBefore 107 # Table walks squashed before starting +system.cpu2.itb.walker.walkWaitTime::samples 5840 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::mean 1732.534247 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::stdev 7455.028366 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::0-8191 5455 93.41% 93.41% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::8192-16383 164 2.81% 96.22% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::16384-24575 114 1.95% 98.17% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::24576-32767 45 0.77% 98.94% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::32768-40959 19 0.33% 99.26% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::40960-49151 8 0.14% 99.40% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::49152-57343 13 0.22% 99.62% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::57344-65535 3 0.05% 99.67% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::65536-73727 6 0.10% 99.78% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::73728-81919 3 0.05% 99.83% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::81920-90111 5 0.09% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::90112-98303 1 0.02% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::98304-106495 2 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::106496-114687 1 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::122880-131071 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::total 5840 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkCompletionTime::samples 1844 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::mean 13438.177874 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::gmean 11167.697103 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::stdev 8164.078124 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::0-8191 568 30.80% 30.80% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::8192-16383 796 43.17% 73.97% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::16384-24575 418 22.67% 96.64% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::24576-32767 27 1.46% 98.10% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::32768-40959 12 0.65% 98.75% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::40960-49151 15 0.81% 99.57% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::49152-57343 4 0.22% 99.78% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::57344-65535 3 0.16% 99.95% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::65536-73727 1 0.05% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::total 1844 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walksPending::samples 13135820712 # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::mean 0.816052 # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::stdev 0.388899 # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::0 2421306500 18.43% 18.43% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::1 10711149212 81.54% 99.97% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::2 2311000 0.02% 99.99% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::3 636500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::4 285000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::5 97500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::6 35000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::total 13135820712 # Table walker pending requests distribution +system.cpu2.itb.walker.walkPageSizes::4K 1342 77.26% 77.26% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::1M 395 22.74% 100.00% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::total 1737 # Table walker page sizes translated system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 6235 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::total 6235 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 5947 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::total 5947 # Table walker requests started/completed, data/inst system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 1754 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::total 1754 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin::total 7989 # Table walker requests started/completed, data/inst -system.cpu2.itb.inst_hits 12837123 # ITB inst hits -system.cpu2.itb.inst_misses 6235 # ITB inst misses +system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 1737 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Completed::total 1737 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin::total 7684 # Table walker requests started/completed, data/inst +system.cpu2.itb.inst_hits 12739134 # ITB inst hits +system.cpu2.itb.inst_misses 5947 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses system.cpu2.itb.flush_tlb 179 # Number of times complete TLB was flushed -system.cpu2.itb.flush_tlb_mva 360 # Number of times TLB was flushed by MVA +system.cpu2.itb.flush_tlb_mva 348 # Number of times TLB was flushed by MVA system.cpu2.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 1683 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 1664 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1125 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 1123 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 12843358 # ITB inst accesses -system.cpu2.itb.hits 12837123 # DTB hits -system.cpu2.itb.misses 6235 # DTB misses -system.cpu2.itb.accesses 12843358 # DTB accesses -system.cpu2.numCycles 69616646 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 12745081 # ITB inst accesses +system.cpu2.itb.hits 12739134 # DTB hits +system.cpu2.itb.misses 5947 # DTB misses +system.cpu2.itb.accesses 12745081 # DTB accesses +system.cpu2.numCycles 69598203 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 26594039 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 69071466 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 17390044 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 12193362 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 39655163 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 2070826 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 93322 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 918 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 302 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 323029 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 106475 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 727 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 12835626 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 269064 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 2716 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 67809362 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.223662 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.348600 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 26515709 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 68908003 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 17205761 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 12047751 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 39848524 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 2067901 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 93242 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 1673 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 258 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 197550 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 103741 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 733 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 12737635 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 269288 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 2836 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 67795354 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.222311 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.353518 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 49260090 72.64% 72.64% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 2390617 3.53% 76.17% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 1561768 2.30% 78.47% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 4865604 7.18% 85.65% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 1097205 1.62% 87.27% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 701816 1.03% 88.30% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 3870082 5.71% 94.01% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 751059 1.11% 95.12% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 3311121 4.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 49366248 72.82% 72.82% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 2347568 3.46% 76.28% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 1568593 2.31% 78.59% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 4737747 6.99% 85.58% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 1131198 1.67% 87.25% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 711180 1.05% 88.30% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 3791892 5.59% 93.89% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 790451 1.17% 95.06% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3350477 4.94% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 67809362 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.249797 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.992169 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 18546973 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 36871218 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 10413141 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 1051163 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 926599 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 1313756 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 110434 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 59271705 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 356279 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 926599 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 19159512 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 3828211 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 27033628 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 10840093 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 6021054 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 56800254 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 1622 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 892733 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 160451 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 4475802 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 58727822 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 260839504 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 63695069 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 4195 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 48596346 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 10131460 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 953771 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 889969 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 6004915 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 10275852 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 7909386 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 1396867 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 1932490 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 54546075 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 673336 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 51866821 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 68048 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 8110099 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 18430167 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 68913 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 67809362 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.764892 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.469149 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 67795354 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.247216 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.990083 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 18554298 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 36869392 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 10385190 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 1060917 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 925294 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 1315001 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 110273 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 59218991 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 355421 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 925294 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 19165450 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 3849841 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 27045066 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 10823220 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 5986178 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 56757014 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 1753 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 886942 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 164990 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 4446768 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 58681863 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 260617277 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 63638433 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 4180 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 48518636 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 10163211 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 951510 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 887874 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 5959133 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 10269621 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 7907555 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 1397245 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 1927093 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 54497262 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 673331 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 51805193 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 68913 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 8128009 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 18480591 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 69367 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 67795354 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.764141 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.469300 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 47470041 70.01% 70.01% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 6738750 9.94% 79.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 5086869 7.50% 87.44% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 4143776 6.11% 93.56% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 1653610 2.44% 95.99% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1071590 1.58% 97.57% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 1124885 1.66% 99.23% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 357423 0.53% 99.76% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 162418 0.24% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 47462334 70.01% 70.01% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 6771907 9.99% 80.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 5071293 7.48% 87.48% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 4140398 6.11% 93.58% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 1621050 2.39% 95.98% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1073842 1.58% 97.56% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 1127363 1.66% 99.22% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 365418 0.54% 99.76% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 161749 0.24% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 67809362 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 67795354 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 76711 9.73% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 2 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 365050 46.29% 56.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 346827 43.98% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 78874 9.93% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 1 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 365128 45.98% 55.91% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 350163 44.09% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 102 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 34390478 66.31% 66.31% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 39542 0.08% 66.38% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 66.38% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 66.38% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 66.38% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 66.38% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 66.38% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 66.38% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 66.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 66.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 66.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 1 0.00% 66.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 66.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 66.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 1 0.00% 66.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 66.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 66.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 66.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 66.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 2888 0.01% 66.39% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 66.39% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 66.39% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.39% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 9917724 19.12% 85.51% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 7516080 14.49% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 104 0.00% 0.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 34340504 66.29% 66.29% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 39551 0.08% 66.36% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 66.36% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 66.36% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 66.36% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 66.36% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 66.36% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 66.36% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 66.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 66.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 66.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 1 0.00% 66.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 66.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 66.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 1 0.00% 66.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 66.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 66.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 66.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 66.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 2876 0.01% 66.37% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 66.37% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 66.37% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.37% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 9906412 19.12% 85.49% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 7515741 14.51% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 51866821 # Type of FU issued -system.cpu2.iq.rate 0.745035 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 788590 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.015204 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 172390251 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 63361989 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 50322136 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 9391 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 4966 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 4144 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 52650258 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 5051 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 268895 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 51805193 # Type of FU issued +system.cpu2.iq.rate 0.744347 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 794166 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.015330 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 172259378 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 63331070 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 50263649 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 9441 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 4992 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 4167 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 52594172 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 5083 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 269403 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1610409 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1859 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 38198 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 800698 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1615728 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1799 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 38192 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 801002 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 130635 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 68542 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 130832 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 65205 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 926599 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 3277236 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 403345 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 55328961 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 92252 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 10275852 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 7909386 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 360332 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 33301 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 361214 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 38198 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 183568 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 164696 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 348264 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 51429187 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 9738477 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 394455 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 925294 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 3298023 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 403705 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 55280627 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 94381 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 10269621 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 7907555 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 360066 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 33263 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 361678 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 38192 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 184473 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 164818 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 349291 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 51367571 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 9727601 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 393852 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 109550 # number of nop insts executed -system.cpu2.iew.exec_refs 17180160 # number of memory reference insts executed -system.cpu2.iew.exec_branches 9476518 # Number of branches executed -system.cpu2.iew.exec_stores 7441683 # Number of stores executed -system.cpu2.iew.exec_rate 0.738748 # Inst execution rate -system.cpu2.iew.wb_sent 51031347 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 50326280 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 26469079 # num instructions producing a value -system.cpu2.iew.wb_consumers 46041332 # num instructions consuming a value +system.cpu2.iew.exec_nop 110034 # number of nop insts executed +system.cpu2.iew.exec_refs 17167980 # number of memory reference insts executed +system.cpu2.iew.exec_branches 9465672 # Number of branches executed +system.cpu2.iew.exec_stores 7440379 # Number of stores executed +system.cpu2.iew.exec_rate 0.738059 # Inst execution rate +system.cpu2.iew.wb_sent 50970582 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 50267816 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 26418019 # num instructions producing a value +system.cpu2.iew.wb_consumers 45975704 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.722906 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.574898 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.722257 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.574608 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 8143906 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 604423 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 291897 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 66086949 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.713825 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.622364 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 8162826 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 603964 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 292667 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 66072678 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.712969 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.621762 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 48131767 72.83% 72.83% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 7989880 12.09% 84.92% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 3968576 6.01% 90.93% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 1690353 2.56% 93.48% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 906489 1.37% 94.86% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 608385 0.92% 95.78% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 1262051 1.91% 97.69% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 299318 0.45% 98.14% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1230130 1.86% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 48122515 72.83% 72.83% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 8016673 12.13% 84.97% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 3951454 5.98% 90.95% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 1700222 2.57% 93.52% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 874557 1.32% 94.84% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 615125 0.93% 95.77% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 1261958 1.91% 97.68% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 299480 0.45% 98.14% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1230694 1.86% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 66086949 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 38874571 # Number of instructions committed -system.cpu2.commit.committedOps 47174544 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 66072678 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 38816949 # Number of instructions committed +system.cpu2.commit.committedOps 47107760 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 15774131 # Number of memory references committed -system.cpu2.commit.loads 8665443 # Number of loads committed -system.cpu2.commit.membars 227144 # Number of memory barriers committed -system.cpu2.commit.branches 8900555 # Number of branches committed -system.cpu2.commit.fp_insts 4112 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 41283041 # Number of committed integer instructions. -system.cpu2.commit.function_calls 1636102 # Number of function calls committed. +system.cpu2.commit.refs 15760446 # Number of memory references committed +system.cpu2.commit.loads 8653893 # Number of loads committed +system.cpu2.commit.membars 226862 # Number of memory barriers committed +system.cpu2.commit.branches 8887739 # Number of branches committed +system.cpu2.commit.fp_insts 4128 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 41222164 # Number of committed integer instructions. +system.cpu2.commit.function_calls 1631970 # Number of function calls committed. system.cpu2.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 31359241 66.47% 66.47% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 38284 0.08% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 2888 0.01% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 8665443 18.37% 84.93% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 7108688 15.07% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 31306209 66.46% 66.46% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 38229 0.08% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 2876 0.01% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 8653893 18.37% 84.91% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 7106553 15.09% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 47174544 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1230130 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 112818862 # The number of ROB reads -system.cpu2.rob.rob_writes 112362949 # The number of ROB writes -system.cpu2.timesIdled 279332 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1807284 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 5249914577 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 38809335 # Number of Instructions Simulated -system.cpu2.committedOps 47109308 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.793812 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.793812 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.557472 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.557472 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 56301107 # number of integer regfile reads -system.cpu2.int_regfile_writes 31916155 # number of integer regfile writes -system.cpu2.fp_regfile_reads 15723 # number of floating regfile reads -system.cpu2.fp_regfile_writes 13758 # number of floating regfile writes -system.cpu2.cc_regfile_reads 181999487 # number of cc regfile reads -system.cpu2.cc_regfile_writes 19225356 # number of cc regfile writes -system.cpu2.misc_regfile_reads 94261250 # number of misc regfile reads -system.cpu2.misc_regfile_writes 485009 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 30180 # Transaction distribution -system.iobus.trans_dist::ReadResp 30180 # Transaction distribution -system.iobus.trans_dist::WriteReq 59003 # Transaction distribution -system.iobus.trans_dist::WriteResp 22779 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54126 # Packet count per connected master and slave (bytes) +system.cpu2.commit.op_class_0::total 47107760 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1230694 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 112781874 # The number of ROB reads +system.cpu2.rob.rob_writes 112267275 # The number of ROB writes +system.cpu2.timesIdled 279594 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1802849 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 5249879064 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 38751769 # Number of Instructions Simulated +system.cpu2.committedOps 47042580 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.796001 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.796001 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.556793 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.556793 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 56233169 # number of integer regfile reads +system.cpu2.int_regfile_writes 31866388 # number of integer regfile writes +system.cpu2.fp_regfile_reads 15654 # number of floating regfile reads +system.cpu2.fp_regfile_writes 13819 # number of floating regfile writes +system.cpu2.cc_regfile_reads 181781148 # number of cc regfile reads +system.cpu2.cc_regfile_writes 19208893 # number of cc regfile writes +system.cpu2.misc_regfile_reads 94223470 # number of misc regfile reads +system.cpu2.misc_regfile_writes 484431 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 30182 # Transaction distribution +system.iobus.trans_dist::ReadResp 30182 # Transaction distribution +system.iobus.trans_dist::WriteReq 59005 # Transaction distribution +system.iobus.trans_dist::WriteResp 59005 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54134 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) @@ -1779,11 +1778,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 105414 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 105422 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178366 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67843 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 178374 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67851 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) @@ -1804,11 +1803,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 159071 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 159079 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480319 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 18225000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2480327 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 18337000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1830,29 +1829,29 @@ system.iobus.reqLayer19.occupancy 2000 # La system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 2714000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 2698000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 1000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 15729000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 15728000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 25000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 124959118 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 107120699 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 39808000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 39854000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 23061006 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 20948000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36442 # number of replacements -system.iocache.tags.tagsinuse 0.992064 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.991924 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 244950709509 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.992064 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062004 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062004 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 244949964009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 0.991924 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.061995 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.061995 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1860,377 +1859,389 @@ system.iocache.tags.tag_accesses 328284 # Nu system.iocache.tags.data_accesses 328284 # Number of data accesses system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses system.iocache.ReadReq_misses::total 252 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses system.iocache.demand_misses::total 252 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 252 # number of overall misses system.iocache.overall_misses::total 252 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 14858930 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 14858930 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 4185043182 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 4185043182 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 14858930 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 14858930 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 14858930 # number of overall miss cycles -system.iocache.overall_miss_latency::total 14858930 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 14446931 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 14446931 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 2442151768 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 2442151768 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 14446931 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 14446931 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 14446931 # number of overall miss cycles +system.iocache.overall_miss_latency::total 14446931 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 58964.007937 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 58964.007937 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 115532.331659 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 115532.331659 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 58964.007937 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 58964.007937 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 58964.007937 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 58964.007937 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 14316 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 57329.091270 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 57329.091270 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 67418.058966 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 67418.058966 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 57329.091270 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 57329.091270 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 57329.091270 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 57329.091270 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 2165 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.612471 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 125 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 125 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 22752 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 22752 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 125 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 125 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 125 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 125 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 8240930 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 8240930 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 3001927194 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 3001927194 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 8240930 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8240930 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 8240930 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8240930 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.496032 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.496032 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 0.628092 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.628092 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.demand_mshr_miss_rate::realview.ide 0.496032 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.496032 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::realview.ide 0.496032 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.496032 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 65927.440000 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 65927.440000 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131941.244462 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131941.244462 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 65927.440000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 65927.440000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 65927.440000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 65927.440000 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::realview.ide 122 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 122 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 20704 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 20704 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::realview.ide 122 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 122 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 122 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 122 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 8346931 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 8346931 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 1406951768 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 1406951768 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 8346931 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8346931 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 8346931 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8346931 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.484127 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.484127 # mshr miss rate for ReadReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.571555 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.571555 # mshr miss rate for WriteLineReq accesses +system.iocache.demand_mshr_miss_rate::realview.ide 0.484127 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.484127 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ide 0.484127 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.484127 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68417.467213 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68417.467213 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67955.552937 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67955.552937 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 68417.467213 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68417.467213 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 68417.467213 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68417.467213 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 100862 # number of replacements -system.l2c.tags.tagsinuse 65121.580421 # Cycle average of tags in use -system.l2c.tags.total_refs 2889469 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 166056 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 17.400570 # Average number of references to valid blocks. +system.l2c.tags.replacements 100800 # number of replacements +system.l2c.tags.tagsinuse 65125.449839 # Cycle average of tags in use +system.l2c.tags.total_refs 4808585 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 165996 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 28.968078 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 49829.873035 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.939329 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 49726.772555 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.939327 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000095 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5354.052994 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2949.398573 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5415.190350 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2959.237721 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.969230 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1018.817810 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 810.859726 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 62.513746 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 3585.332677 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 1507.823205 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.760344 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu1.inst 1018.129085 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 815.178543 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 59.704078 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 3616.145822 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 1512.183033 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.758770 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000030 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.081696 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.045004 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.082629 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.045154 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.015546 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.012373 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000954 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.054708 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.023008 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.993676 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 50 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65144 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 50 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu1.inst 0.015535 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.012439 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000911 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.055178 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.023074 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.993736 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 48 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65148 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 48 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 347 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2979 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 8228 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53568 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000763 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.994019 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 27412273 # Number of tag accesses -system.l2c.tags.data_accesses 27412273 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 4625 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 2417 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 853709 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 239887 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 1714 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 910 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 248258 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 78311 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 26936 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 6133 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 677801 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 203846 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2344547 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 690587 # number of Writeback hits -system.l2c.Writeback_hits::total 690587 # number of Writeback hits +system.l2c.tags.age_task_id_blocks_1024::1 322 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2981 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 8244 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 53579 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000732 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.994080 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 42763917 # Number of tag accesses +system.l2c.tags.data_accesses 42763917 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 4590 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 2386 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 1717 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 931 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 27091 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 5953 # number of ReadReq hits +system.l2c.ReadReq_hits::total 42668 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 690633 # number of Writeback hits +system.l2c.Writeback_hits::total 690633 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 10 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 33 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 47 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu2.data 10 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 81710 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 20207 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 55512 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 157429 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 4625 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 2417 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 853709 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 321597 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 1714 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 910 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 248258 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 98518 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 26936 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 6133 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 677801 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 259358 # number of demand (read+write) hits -system.l2c.demand_hits::total 2501976 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 4625 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 2417 # number of overall hits -system.l2c.overall_hits::cpu0.inst 853709 # number of overall hits -system.l2c.overall_hits::cpu0.data 321597 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 1714 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 910 # number of overall hits -system.l2c.overall_hits::cpu1.inst 248258 # number of overall hits -system.l2c.overall_hits::cpu1.data 98518 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 26936 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 6133 # number of overall hits -system.l2c.overall_hits::cpu2.inst 677801 # number of overall hits -system.l2c.overall_hits::cpu2.data 259358 # number of overall hits -system.l2c.overall_hits::total 2501976 # number of overall hits +system.l2c.UpgradeReq_hits::cpu2.data 34 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 48 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu2.data 11 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 11 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 81720 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 20255 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 55422 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 157397 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 854225 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 247947 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu2.inst 678133 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 1780305 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 239843 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 78268 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu2.data 203677 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 521788 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 4590 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 2386 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 854225 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 321563 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 1717 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 931 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 247947 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 98523 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.dtb.walker 27091 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.itb.walker 5953 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 678133 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 259099 # number of demand (read+write) hits +system.l2c.demand_hits::total 2502158 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 4590 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 2386 # number of overall hits +system.l2c.overall_hits::cpu0.inst 854225 # number of overall hits +system.l2c.overall_hits::cpu0.data 321563 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 1717 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 931 # number of overall hits +system.l2c.overall_hits::cpu1.inst 247947 # number of overall hits +system.l2c.overall_hits::cpu1.data 98523 # number of overall hits +system.l2c.overall_hits::cpu2.dtb.walker 27091 # number of overall hits +system.l2c.overall_hits::cpu2.itb.walker 5953 # number of overall hits +system.l2c.overall_hits::cpu2.inst 678133 # number of overall hits +system.l2c.overall_hits::cpu2.data 259099 # number of overall hits +system.l2c.overall_hits::total 2502158 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 9677 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 7117 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1966 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 2467 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 92 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 8131 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 4488 # number of ReadReq misses -system.l2c.ReadReq_misses::total 33944 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1342 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 299 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 1074 # number of UpgradeReq misses +system.l2c.ReadReq_misses::cpu2.dtb.walker 89 # number of ReadReq misses +system.l2c.ReadReq_misses::total 95 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1320 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 342 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 1053 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 2715 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu0.data 3 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu2.data 6 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 9 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 64356 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 14516 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 59985 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 138857 # number of ReadExReq misses +system.l2c.SCUpgradeReq_misses::cpu2.data 5 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 8 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 64209 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 14460 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 60110 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 138779 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 9651 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 1946 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu2.inst 8147 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 19744 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 7162 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 2480 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu2.data 4481 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 14123 # number of ReadSharedReq misses system.l2c.demand_misses::cpu0.dtb.walker 4 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 9677 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 71473 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 9651 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 71371 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1966 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 16983 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.dtb.walker 92 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 8131 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 64473 # number of demand (read+write) misses -system.l2c.demand_misses::total 172801 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1946 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 16940 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.dtb.walker 89 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 8147 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 64591 # number of demand (read+write) misses +system.l2c.demand_misses::total 172741 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 4 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 9677 # number of overall misses -system.l2c.overall_misses::cpu0.data 71473 # number of overall misses +system.l2c.overall_misses::cpu0.inst 9651 # number of overall misses +system.l2c.overall_misses::cpu0.data 71371 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1966 # number of overall misses -system.l2c.overall_misses::cpu1.data 16983 # number of overall misses -system.l2c.overall_misses::cpu2.dtb.walker 92 # number of overall misses -system.l2c.overall_misses::cpu2.inst 8131 # number of overall misses -system.l2c.overall_misses::cpu2.data 64473 # number of overall misses -system.l2c.overall_misses::total 172801 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1946 # number of overall misses +system.l2c.overall_misses::cpu1.data 16940 # number of overall misses +system.l2c.overall_misses::cpu2.dtb.walker 89 # number of overall misses +system.l2c.overall_misses::cpu2.inst 8147 # number of overall misses +system.l2c.overall_misses::cpu2.data 64591 # number of overall misses +system.l2c.overall_misses::total 172741 # number of overall misses system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 82500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 157235750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 203986258 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 7890000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 682853750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 390763250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1442811508 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 93497 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2.data 280991 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 374488 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu2.data 63499 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 63499 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1135317971 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 4897657997 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6032975968 # number of ReadExReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 7918000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 8000500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 92500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2.data 339500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 432000 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu2.data 127000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 127000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 1119587000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 4880855000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6000442000 # number of ReadExReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu1.inst 159178000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu2.inst 680250500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 839428500 # number of ReadCleanReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 203493500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu2.data 391802000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 595295500 # number of ReadSharedReq miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 82500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 157235750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1339304229 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.dtb.walker 7890000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 682853750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 5288421247 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 7475787476 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 159178000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1323080500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.dtb.walker 7918000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 680250500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 5272657000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 7443166500 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 82500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 157235750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1339304229 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.dtb.walker 7890000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 682853750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 5288421247 # number of overall miss cycles -system.l2c.overall_miss_latency::total 7475787476 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 4629 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 2418 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 863386 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 247004 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 1715 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 910 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 250224 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 80778 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.dtb.walker 27028 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.itb.walker 6133 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 685932 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 208334 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2378491 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 690587 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 690587 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1352 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 303 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 1107 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2762 # number of UpgradeReq accesses(hits+misses) +system.l2c.overall_miss_latency::cpu1.inst 159178000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1323080500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.dtb.walker 7918000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 680250500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 5272657000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 7443166500 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 4594 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 2387 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 1718 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 931 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.dtb.walker 27180 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.itb.walker 5953 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 42763 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 690633 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 690633 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1330 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 346 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 1087 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2763 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu0.data 3 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu2.data 16 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 19 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 146066 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 34723 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 115497 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 296286 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 4629 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 2418 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 863386 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 393070 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 1715 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 910 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 250224 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 115501 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.dtb.walker 27028 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.itb.walker 6133 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 685932 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 323831 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2674777 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 4629 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 2418 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 863386 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 393070 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 1715 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 910 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 250224 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 115501 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.dtb.walker 27028 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.itb.walker 6133 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 685932 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 323831 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2674777 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000864 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000414 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.011208 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.028813 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000583 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.007857 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.030540 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.003404 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.011854 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.021542 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.014271 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.992604 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.986799 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 0.970190 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.982983 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_accesses::cpu0.data 145929 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 34715 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 115532 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 296176 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 863876 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 249893 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu2.inst 686280 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 1800049 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 247005 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 80748 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu2.data 208158 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 535911 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 4594 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 2387 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 863876 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 392934 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 1718 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 931 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 249893 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 115463 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.dtb.walker 27180 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.itb.walker 5953 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 686280 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 323690 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2674899 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 4594 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 2387 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 863876 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 392934 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 1718 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 931 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 249893 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 115463 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.dtb.walker 27180 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.itb.walker 5953 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 686280 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 323690 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2674899 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000871 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000419 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000582 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.003274 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.002222 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.992481 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.988439 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 0.968721 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.982628 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu2.data 0.375000 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.473684 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.440595 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.418051 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 0.519364 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.468659 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000864 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000414 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.011208 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.181833 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000583 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.007857 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.147038 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.dtb.walker 0.003404 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.011854 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.199095 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.064604 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000864 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000414 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.011208 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.181833 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000583 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.007857 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.147038 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.dtb.walker 0.003404 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.011854 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.199095 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.064604 # miss rate for overall accesses +system.l2c.SCUpgradeReq_miss_rate::cpu2.data 0.312500 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.421053 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.440002 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.416535 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 0.520289 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.468569 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.011172 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.007787 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.011871 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.010969 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.028995 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.030713 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.021527 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.026353 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000871 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000419 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.011172 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.181636 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000582 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.007787 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.146714 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.dtb.walker 0.003274 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.011871 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.199546 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.064579 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000871 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000419 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.011172 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.181636 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000582 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.007787 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.146714 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.dtb.walker 0.003274 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.011871 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.199546 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.064579 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 82500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 79977.492370 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 82685.957844 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 85760.869565 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 83981.521338 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 87068.460339 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 42505.641881 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 312.698997 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 261.630354 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 137.932965 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu2.data 10583.166667 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 7055.444444 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 78211.488771 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 81648.045295 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 43447.402493 # average ReadExReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 88966.292135 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 84215.789474 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 270.467836 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 322.412156 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 159.116022 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu2.data 25400 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 15875 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 77426.486860 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 81198.719015 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 43237.391824 # average ReadExReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 81797.533402 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 83497.054130 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 42515.625000 # average ReadCleanReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 82053.830645 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 87436.286543 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 42150.782412 # average ReadSharedReq miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 82500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 79977.492370 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 78861.463169 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 85760.869565 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 83981.521338 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 82025.363284 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 43262.408643 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 81797.533402 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 78103.925620 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 88966.292135 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 83497.054130 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 81631.450202 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 43088.592170 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 82500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 79977.492370 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 78861.463169 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 85760.869565 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 83981.521338 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 82025.363284 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 43262.408643 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 81797.533402 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 78103.925620 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 88966.292135 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 83497.054130 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 81631.450202 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 43088.592170 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2239,210 +2250,221 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 92886 # number of writebacks -system.l2c.writebacks::total 92886 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu2.inst 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2.data 44 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu2.inst 7 # number of demand (read+write) MSHR hits +system.l2c.writebacks::writebacks 92937 # number of writebacks +system.l2c.writebacks::total 92937 # number of writebacks +system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 5 # number of ReadCleanReq MSHR hits +system.l2c.ReadCleanReq_mshr_hits::total 5 # number of ReadCleanReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu2.data 44 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 44 # number of ReadSharedReq MSHR hits +system.l2c.demand_mshr_hits::cpu2.inst 5 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu2.data 44 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 51 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu2.inst 7 # number of overall MSHR hits +system.l2c.demand_mshr_hits::total 49 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu2.inst 5 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu2.data 44 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 51 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 49 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 1966 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 2467 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 92 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 8124 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 4444 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 17094 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 299 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 1074 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 1373 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu2.data 6 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 6 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 14516 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 59985 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 74501 # number of ReadExReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 89 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 90 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 342 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 1053 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 1395 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu2.data 5 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 5 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 14460 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 60110 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 74570 # number of ReadExReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 1946 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 8142 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::total 10088 # number of ReadCleanReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 2480 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu2.data 4437 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 6917 # number of ReadSharedReq MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 1966 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 16983 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.dtb.walker 92 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 8124 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 64429 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 91595 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 1946 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 16940 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.dtb.walker 89 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 8142 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 64547 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 91665 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 1966 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 16983 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.dtb.walker 92 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 8124 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 64429 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 91595 # number of overall MSHR misses -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 5880 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu2.data 8599 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 14479 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 4601 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu2.data 6739 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 11340 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 10481 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu2.data 15338 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 25819 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 70000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 132598250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 173127242 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 6735500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 580526000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 331871000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1224927992 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5327299 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 19051574 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 24378873 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data 109005 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 109005 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 953509029 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 4148606003 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5102115032 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 70000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 132598250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 1126636271 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 6735500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 580526000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 4480477003 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 6327043024 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 70000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 132598250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 1126636271 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 6735500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 580526000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 4480477003 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 6327043024 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 960816500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 1572406000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 2533222500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 743288000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 1223622500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1966910500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1704104500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 2796028500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 4500133000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000583 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.007857 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030540 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.003404 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.011844 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.021331 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.007187 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.986799 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.970190 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.497104 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.375000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.315789 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.418051 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.519364 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.251450 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000583 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007857 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.147038 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.003404 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.011844 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.198959 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.034244 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000583 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007857 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.147038 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.003404 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.011844 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.198959 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.034244 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 70000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 67445.701933 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 70177.236319 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 73211.956522 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 71458.148695 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 74678.442844 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 71658.359190 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17817.053512 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 17738.895717 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17755.916242 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 18167.500000 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 18167.500000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65686.761436 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69160.723564 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 68483.846284 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 70000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 67445.701933 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66339.060884 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 73211.956522 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 71458.148695 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 69541.309084 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 69076.292636 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67445.701933 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66339.060884 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 73211.956522 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 71458.148695 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 69541.309084 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 69076.292636 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163404.166667 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 182859.169671 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 174958.388010 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 161549.228429 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 181573.304645 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 173448.897707 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 162589.876920 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 182294.203938 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 174295.402610 # average overall mshr uncacheable latency +system.l2c.overall_mshr_misses::cpu1.inst 1946 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 16940 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.dtb.walker 89 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 8142 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 64547 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 91665 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 5882 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu2.data 8601 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 14483 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 4590 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu2.data 6802 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 11392 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 10472 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu2.data 15403 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 25875 # number of overall MSHR uncacheable misses +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 72500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 7028000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 7100500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 7101000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 21856500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 28957500 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data 108000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 108000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 974987000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 4279755000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5254742000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 139718000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 598575000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 738293000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 178693500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 344725500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 523419000 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 72500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 139718000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1153680500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 7028000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 598575000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 4624480500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 6523554500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 72500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 139718000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1153680500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 7028000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 598575000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 4624480500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6523554500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 983438000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 1607640500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 2591078500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 758788000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 1264062500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2022850500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1742226000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 2871703000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4613929000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000582 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.003274 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.002105 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.988439 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.968721 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.504886 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.312500 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.263158 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.416535 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.520289 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.251776 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.007787 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.011864 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.005604 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.030713 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.021316 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.012907 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000582 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007787 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.146714 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.003274 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.011864 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.199410 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.034269 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000582 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007787 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.146714 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.003274 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.011864 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.199410 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.034269 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 72500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 78966.292135 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 78894.444444 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20763.157895 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20756.410256 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20758.064516 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 21600 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 21600 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 67426.486860 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 71198.719015 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 70467.238836 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 71797.533402 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 73516.949153 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73185.269627 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 72053.830645 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 77693.373901 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 75671.389331 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 72500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71797.533402 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 68103.925620 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 78966.292135 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73516.949153 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 71645.165538 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 71167.343043 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 72500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71797.533402 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 68103.925620 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 78966.292135 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73516.949153 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 71645.165538 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 71167.343043 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 167194.491670 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 186913.207767 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 178904.819443 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 165313.289760 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 185836.886210 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 177567.635183 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 166369.938885 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 186437.901707 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 178316.096618 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 74250 # Transaction distribution -system.membus.trans_dist::ReadResp 74249 # Transaction distribution -system.membus.trans_dist::WriteReq 27555 # Transaction distribution -system.membus.trans_dist::WriteResp 27555 # Transaction distribution -system.membus.trans_dist::Writeback 129076 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4552 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 9 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4561 # Transaction distribution -system.membus.trans_dist::ReadExReq 137020 # Transaction distribution -system.membus.trans_dist::ReadExResp 137020 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105414 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 40110 # Transaction distribution +system.membus.trans_dist::ReadResp 74274 # Transaction distribution +system.membus.trans_dist::WriteReq 27559 # Transaction distribution +system.membus.trans_dist::WriteResp 27559 # Transaction distribution +system.membus.trans_dist::Writeback 129127 # Transaction distribution +system.membus.trans_dist::CleanEvict 7993 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4555 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 8 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4563 # Transaction distribution +system.membus.trans_dist::ReadExReq 136939 # Transaction distribution +system.membus.trans_dist::ReadExResp 136939 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 34165 # Transaction distribution +system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105422 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 1990 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 471581 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 578995 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109017 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 109017 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 688012 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159071 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2000 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 479379 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 586811 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109150 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 109150 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 695961 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159079 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 3980 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16928828 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 17091899 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4642624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 4642624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21734523 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 283 # Total snoops (count) -system.membus.snoop_fanout::samples 408724 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4000 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16928316 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 17091415 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2324480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2324480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19415895 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 278 # Total snoops (count) +system.membus.snoop_fanout::samples 416813 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 408724 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 416813 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 408724 # Request fanout histogram -system.membus.reqLayer0.occupancy 45631500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 416813 # Request fanout histogram +system.membus.reqLayer0.occupancy 45715500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 463000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 475000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 565034415 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 457691597 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 525270598 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 520011564 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 23441994 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 36772084 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2475,50 +2497,53 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 2441800 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2441792 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 27555 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 27555 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 690587 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 22777 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2762 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 105713 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2441896 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 27559 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 27559 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 756453 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1923004 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2763 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 19 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2781 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 296286 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296286 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3617238 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2478347 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 29055 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 87637 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 6212277 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 115207096 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97661699 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 48712 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 154828 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 213072335 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 51752 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3495385 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.029269 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.168561 # Request fanout histogram +system.toL2Bus.trans_dist::UpgradeResp 2782 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 296176 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296176 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1800158 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 536033 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 20704 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5399808 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2615033 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28551 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 87799 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8131191 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 115239416 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97644319 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 47800 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 155188 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 213086723 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 121684 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 5505945 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.031256 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.174010 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 3393077 97.07% 97.07% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 102308 2.93% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 5333849 96.87% 96.87% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 172096 3.13% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3495385 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1275217471 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 177000 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 5505945 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1781656500 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 172500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1406471499 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1404823682 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 694961258 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 679741283 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 11749485 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 11544481 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 39124219 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 39263676 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index 30daa6157..a839f8e59 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,138 +1,138 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.804323 # Number of seconds simulated -sim_ticks 2804323403500 # Number of ticks simulated -final_tick 2804323403500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.804297 # Number of seconds simulated +sim_ticks 2804296829000 # Number of ticks simulated +final_tick 2804296829000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 112232 # Simulator instruction rate (inst/s) -host_op_rate 136221 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2690265937 # Simulator tick rate (ticks/s) -host_mem_usage 630508 # Number of bytes of host memory used -host_seconds 1042.40 # Real time elapsed on the host -sim_insts 116990114 # Number of instructions simulated -sim_ops 141995948 # Number of ops (including micro ops) simulated +host_inst_rate 111214 # Simulator instruction rate (inst/s) +host_op_rate 134984 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2666624096 # Simulator tick rate (ticks/s) +host_mem_usage 631592 # Number of bytes of host memory used +host_seconds 1051.63 # Real time elapsed on the host +sim_insts 116955586 # Number of instructions simulated +sim_ops 141953418 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 4352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 4480 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 690752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4989088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 4032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 687552 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4838856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 694336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4949664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 4608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 683520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4874120 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11215656 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 690752 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 687552 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1378304 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8426048 # Number of bytes written to this memory +system.physmem.bytes_read::total 11211752 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 694336 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 683520 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1377856 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8431616 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::total 8443572 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 68 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8449140 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 70 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 10793 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 78473 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 63 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 10743 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 75609 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 10849 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 77857 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 72 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 10680 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 76160 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 175765 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 131657 # Number of write requests responded to by this memory +system.physmem.num_reads::total 175704 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 131744 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::total 136038 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 1552 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 136125 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 1598 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 246317 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1779070 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1438 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 245176 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1725499 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 247597 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1765029 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1643 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 243740 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1738090 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 342 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3999416 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 246317 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 245176 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 491493 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3004663 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3998062 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 247597 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 243740 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 491337 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3006677 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6246 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3010912 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3004663 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 1552 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3012926 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3006677 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 1598 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 246317 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1785316 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1438 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 245176 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1725501 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 247597 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1771275 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1643 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 243740 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1738093 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 342 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7010328 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 175766 # Number of read requests accepted -system.physmem.writeReqs 172232 # Number of write requests accepted -system.physmem.readBursts 175766 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 172232 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11239872 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9152 # Total number of bytes read from write queue -system.physmem.bytesWritten 9513088 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11215720 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10759988 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 143 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 23563 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4633 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11568 # Per bank write bursts -system.physmem.perBankRdBursts::1 11615 # Per bank write bursts -system.physmem.perBankRdBursts::2 11475 # Per bank write bursts -system.physmem.perBankRdBursts::3 10984 # Per bank write bursts -system.physmem.perBankRdBursts::4 11566 # Per bank write bursts -system.physmem.perBankRdBursts::5 11265 # Per bank write bursts -system.physmem.perBankRdBursts::6 12051 # Per bank write bursts -system.physmem.perBankRdBursts::7 11828 # Per bank write bursts -system.physmem.perBankRdBursts::8 10136 # Per bank write bursts -system.physmem.perBankRdBursts::9 10546 # Per bank write bursts -system.physmem.perBankRdBursts::10 10466 # Per bank write bursts -system.physmem.perBankRdBursts::11 9460 # Per bank write bursts -system.physmem.perBankRdBursts::12 10169 # Per bank write bursts -system.physmem.perBankRdBursts::13 11261 # Per bank write bursts -system.physmem.perBankRdBursts::14 10850 # Per bank write bursts -system.physmem.perBankRdBursts::15 10383 # Per bank write bursts -system.physmem.perBankWrBursts::0 9594 # Per bank write bursts -system.physmem.perBankWrBursts::1 9874 # Per bank write bursts -system.physmem.perBankWrBursts::2 9855 # Per bank write bursts -system.physmem.perBankWrBursts::3 9284 # Per bank write bursts -system.physmem.perBankWrBursts::4 9607 # Per bank write bursts -system.physmem.perBankWrBursts::5 9407 # Per bank write bursts -system.physmem.perBankWrBursts::6 10082 # Per bank write bursts -system.physmem.perBankWrBursts::7 9751 # Per bank write bursts -system.physmem.perBankWrBursts::8 8758 # Per bank write bursts -system.physmem.perBankWrBursts::9 9037 # Per bank write bursts -system.physmem.perBankWrBursts::10 8724 # Per bank write bursts -system.physmem.perBankWrBursts::11 8208 # Per bank write bursts -system.physmem.perBankWrBursts::12 8857 # Per bank write bursts -system.physmem.perBankWrBursts::13 9711 # Per bank write bursts -system.physmem.perBankWrBursts::14 9203 # Per bank write bursts -system.physmem.perBankWrBursts::15 8690 # Per bank write bursts +system.physmem.bw_total::total 7010988 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 175705 # Number of read requests accepted +system.physmem.writeReqs 136125 # Number of write requests accepted +system.physmem.readBursts 175705 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 136125 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11235200 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9920 # Total number of bytes read from write queue +system.physmem.bytesWritten 8462208 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11211816 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8449140 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 155 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 40824 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11564 # Per bank write bursts +system.physmem.perBankRdBursts::1 11591 # Per bank write bursts +system.physmem.perBankRdBursts::2 11445 # Per bank write bursts +system.physmem.perBankRdBursts::3 11009 # Per bank write bursts +system.physmem.perBankRdBursts::4 11560 # Per bank write bursts +system.physmem.perBankRdBursts::5 11263 # Per bank write bursts +system.physmem.perBankRdBursts::6 12057 # Per bank write bursts +system.physmem.perBankRdBursts::7 11817 # Per bank write bursts +system.physmem.perBankRdBursts::8 10124 # Per bank write bursts +system.physmem.perBankRdBursts::9 10528 # Per bank write bursts +system.physmem.perBankRdBursts::10 10442 # Per bank write bursts +system.physmem.perBankRdBursts::11 9442 # Per bank write bursts +system.physmem.perBankRdBursts::12 10178 # Per bank write bursts +system.physmem.perBankRdBursts::13 11257 # Per bank write bursts +system.physmem.perBankRdBursts::14 10875 # Per bank write bursts +system.physmem.perBankRdBursts::15 10398 # Per bank write bursts +system.physmem.perBankWrBursts::0 8593 # Per bank write bursts +system.physmem.perBankWrBursts::1 8838 # Per bank write bursts +system.physmem.perBankWrBursts::2 8913 # Per bank write bursts +system.physmem.perBankWrBursts::3 8377 # Per bank write bursts +system.physmem.perBankWrBursts::4 8541 # Per bank write bursts +system.physmem.perBankWrBursts::5 8325 # Per bank write bursts +system.physmem.perBankWrBursts::6 9064 # Per bank write bursts +system.physmem.perBankWrBursts::7 8810 # Per bank write bursts +system.physmem.perBankWrBursts::8 7663 # Per bank write bursts +system.physmem.perBankWrBursts::9 7908 # Per bank write bursts +system.physmem.perBankWrBursts::10 7816 # Per bank write bursts +system.physmem.perBankWrBursts::11 7099 # Per bank write bursts +system.physmem.perBankWrBursts::12 7741 # Per bank write bursts +system.physmem.perBankWrBursts::13 8641 # Per bank write bursts +system.physmem.perBankWrBursts::14 8211 # Per bank write bursts +system.physmem.perBankWrBursts::15 7682 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 53 # Number of times write queue was full causing retry -system.physmem.totGap 2804323239500 # Total gap between requests +system.physmem.numWrRetry 12 # Number of times write queue was full causing retry +system.physmem.totGap 2804296665000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 542 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 175210 # Read request sizes (log2) +system.physmem.readPktSize::6 175149 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 167851 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 103659 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 61692 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 8548 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1701 # What read queue length does an incoming req see +system.physmem.writePktSize::6 131744 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 103856 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 61431 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 8514 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1726 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see @@ -161,201 +161,210 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 92 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1608 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1764 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3817 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5886 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6368 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6937 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7418 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8443 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7584 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9641 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8002 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7571 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2323 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1908 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1755 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2551 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1872 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1780 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1497 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1882 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1465 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1064 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 410 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 207 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 382 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 112 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65975 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 314.556969 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 183.654540 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 335.497717 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24476 37.10% 37.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 15740 23.86% 60.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6623 10.04% 71.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3719 5.64% 76.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2901 4.40% 81.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1575 2.39% 83.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1142 1.73% 85.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1107 1.68% 86.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8692 13.17% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65975 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6306 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.843324 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 438.660877 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6303 99.95% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-6143 1 0.02% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::6144-8191 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::32768-34815 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6306 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6306 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.571519 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.321112 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 39.451011 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-15 32 0.51% 0.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 5917 93.83% 94.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 88 1.40% 95.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 21 0.33% 96.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 16 0.25% 96.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 33 0.52% 96.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 35 0.56% 97.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 27 0.43% 97.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 13 0.21% 98.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 17 0.27% 98.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 5 0.08% 98.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 20 0.32% 98.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 18 0.29% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 8 0.13% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 5 0.08% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 2 0.03% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 2 0.03% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 9 0.14% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 4 0.06% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 6 0.10% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 4 0.06% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 11 0.17% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 1 0.02% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 4 0.06% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 1 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 6 0.10% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::608-623 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6306 # Writes before turning the bus around for reads -system.physmem.totQLat 2686692750 # Total ticks spent queuing -system.physmem.totMemAccLat 5979624000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 878115000 # Total ticks spent in databus transfers -system.physmem.avgQLat 15298.07 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::6 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2023 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6609 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6980 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6950 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8092 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9427 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8643 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7882 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8446 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8628 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7270 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6904 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 321 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 59 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 65040 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 302.849692 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 178.291679 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 326.303136 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24533 37.72% 37.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 15784 24.27% 61.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6682 10.27% 72.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3695 5.68% 77.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2905 4.47% 82.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1458 2.24% 84.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1174 1.81% 86.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1054 1.62% 88.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7755 11.92% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65040 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6683 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.267993 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 478.078944 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6681 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::6144-8191 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::36864-38911 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6683 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6683 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.784827 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.157430 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.794900 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 18 0.27% 0.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 6 0.09% 0.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 6 0.09% 0.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 12 0.18% 0.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5769 86.32% 86.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 120 1.80% 88.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 172 2.57% 91.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 80 1.20% 92.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 71 1.06% 93.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 155 2.32% 95.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 21 0.31% 96.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 14 0.21% 96.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 11 0.16% 96.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 6 0.09% 96.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 8 0.12% 96.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.03% 96.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 156 2.33% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 4 0.06% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.06% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 5 0.07% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 3 0.04% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 3 0.04% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 4 0.06% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.01% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 3 0.04% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 14 0.21% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.01% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 2 0.03% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.03% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 3 0.04% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::204-207 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6683 # Writes before turning the bus around for reads +system.physmem.totQLat 2675585250 # Total ticks spent queuing +system.physmem.totMemAccLat 5967147750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 877750000 # Total ticks spent in databus transfers +system.physmem.avgQLat 15241.16 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 34048.07 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 33991.16 # Average memory access latency per DRAM burst system.physmem.avgRdBW 4.01 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.39 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 3.02 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 4.00 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.84 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.01 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.06 # Data bus utilization in percentage +system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.64 # Average read queue length when enqueuing -system.physmem.avgWrQLen 11.09 # Average write queue length when enqueuing -system.physmem.readRowHits 145297 # Number of row buffer hits during reads -system.physmem.writeRowHits 112992 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.73 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 76.00 # Row buffer hit rate for writes -system.physmem.avgGap 8058446.43 # Average gap between requests -system.physmem.pageHitRate 79.65 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 264138840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 144123375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 720337800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 501901920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 183164495280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 78122450385 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1614063177750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1876980625350 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.317704 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2685041541216 # Time in different power states -system.physmem_0.memoryStateTime::REF 93642380000 # Time in different power states +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.63 # Average read queue length when enqueuing +system.physmem.avgWrQLen 10.95 # Average write queue length when enqueuing +system.physmem.readRowHits 145103 # Number of row buffer hits during reads +system.physmem.writeRowHits 97628 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.66 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.83 # Row buffer hit rate for writes +system.physmem.avgGap 8993030.39 # Average gap between requests +system.physmem.pageHitRate 78.86 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 260993880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 142407375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 719979000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 450107280 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 183162969600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 78025608810 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1614134111250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1876896177195 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.293165 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2685155496500 # Time in different power states +system.physmem_0.memoryStateTime::REF 93641600000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 25639471784 # Time in different power states +system.physmem_0.memoryStateTime::ACT 25499722000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 234632160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 128023500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 649513800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 461298240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 183164495280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 76868306460 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1615163304000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1876669573440 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.206785 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2686874826210 # Time in different power states -system.physmem_1.memoryStateTime::REF 93642380000 # Time in different power states +system.physmem_1.actEnergy 230708520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 125882625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 649303200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 406691280 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 183162969600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 76764954915 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1615239948000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1876580458140 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.180581 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2687003305500 # Time in different power states +system.physmem_1.memoryStateTime::REF 93641600000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 23802212540 # Time in different power states +system.physmem_1.memoryStateTime::ACT 23651154500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.bytes_read::cpu0.inst 640 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 640 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 640 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 640 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 10 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 10 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 228 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 228 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 228 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 228 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 228 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 228 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 704 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 11 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 251 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 251 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 251 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 251 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 251 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 251 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 26894349 # Number of BP lookups -system.cpu0.branchPred.condPredicted 13975311 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 545296 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 16832825 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 12628735 # Number of BTB hits +system.cpu0.branchPred.lookups 26812041 # Number of BP lookups +system.cpu0.branchPred.condPredicted 13971263 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 545954 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 16789639 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 12578074 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 75.024454 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 6673545 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 29900 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 74.915691 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 6641912 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 29629 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -386,84 +395,93 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 59638 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 59638 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 19278 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 14808 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 25552 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 34086 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 541.028575 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 3545.315816 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-16383 33770 99.07% 99.07% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::16384-32767 252 0.74% 99.81% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::32768-49151 35 0.10% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::49152-65535 20 0.06% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-81919 3 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::81920-98303 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::98304-114687 3 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walks 60251 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 60251 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 19166 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 14911 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 26174 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 34077 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 605.672448 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 3875.346595 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-16383 33739 99.01% 99.01% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::16384-32767 267 0.78% 99.79% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::32768-49151 41 0.12% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::49152-65535 11 0.03% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-81919 12 0.04% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::81920-98303 1 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::98304-114687 2 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::114688-131071 2 0.01% 99.99% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::131072-147455 2 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 34086 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 11896 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 11442.270763 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 9167.474880 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 7450.500727 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-8191 3982 33.47% 33.47% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::8192-16383 5461 45.91% 79.38% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-24575 2160 18.16% 97.54% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::24576-32767 140 1.18% 98.71% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-40959 47 0.40% 99.11% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::40960-49151 93 0.78% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::49152-57343 3 0.03% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::57344-65535 3 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-73727 4 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-90111 1 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::90112-98303 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkWaitTime::total 34077 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 12355 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 12355.685957 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 10118.887695 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 7958.316755 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-8191 4001 32.38% 32.38% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::8192-16383 5682 45.99% 78.37% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-24575 2378 19.25% 97.62% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::24576-32767 80 0.65% 98.27% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-40959 88 0.71% 98.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::40960-49151 103 0.83% 99.81% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::49152-57343 4 0.03% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::57344-65535 1 0.01% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-73727 1 0.01% 99.86% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::73728-81919 1 0.01% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-90111 7 0.06% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::90112-98303 8 0.06% 99.99% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::106496-114687 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 11896 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 76466975540 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.696036 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.478552 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-3 76445440540 99.97% 99.97% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-7 15483000 0.02% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-11 3531500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-15 1916000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-19 394500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::20-23 120500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::24-27 34000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::28-31 54000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::32-35 1500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 76466975540 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 3544 69.19% 69.19% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1578 30.81% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 5122 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 59638 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkCompletionTime::total 12355 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 80764749336 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.624014 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.503698 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 80684502836 99.90% 99.90% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 56898500 0.07% 99.97% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 12104000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 4341500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 2388000 0.00% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 1576500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 755000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 1408500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 265500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::18-19 266500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::20-21 51500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::22-23 38500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::24-25 30000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::26-27 29500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::28-29 26000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::30-31 67000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 80764749336 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 3631 69.79% 69.79% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1572 30.21% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 5203 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 60251 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 59638 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5122 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 60251 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5203 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5122 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 64760 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5203 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 65454 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 13978309 # DTB read hits -system.cpu0.dtb.read_misses 51149 # DTB read misses -system.cpu0.dtb.write_hits 10338750 # DTB write hits -system.cpu0.dtb.write_misses 8489 # DTB write misses -system.cpu0.dtb.flush_tlb 181 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 456 # Number of times TLB was flushed by MVA +system.cpu0.dtb.read_hits 14022096 # DTB read hits +system.cpu0.dtb.read_misses 51656 # DTB read misses +system.cpu0.dtb.write_hits 10360983 # DTB write hits +system.cpu0.dtb.write_misses 8595 # DTB write misses +system.cpu0.dtb.flush_tlb 179 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 463 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3463 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 922 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1428 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3475 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 881 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1392 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 586 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 14029458 # DTB read accesses -system.cpu0.dtb.write_accesses 10347239 # DTB write accesses +system.cpu0.dtb.perms_faults 599 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 14073752 # DTB read accesses +system.cpu0.dtb.write_accesses 10369578 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 24317059 # DTB hits -system.cpu0.dtb.misses 59638 # DTB misses -system.cpu0.dtb.accesses 24376697 # DTB accesses +system.cpu0.dtb.hits 24383079 # DTB hits +system.cpu0.dtb.misses 60251 # DTB misses +system.cpu0.dtb.accesses 24443330 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -493,806 +511,806 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 8503 # Table walker walks requested -system.cpu0.itb.walker.walksShort 8503 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3306 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5069 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 128 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 8375 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1173.014925 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 5467.905811 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-8191 7973 95.20% 95.20% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::8192-16383 197 2.35% 97.55% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::16384-24575 109 1.30% 98.85% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::24576-32767 49 0.59% 99.44% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-40959 12 0.14% 99.58% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::40960-49151 14 0.17% 99.75% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::49152-57343 5 0.06% 99.81% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::57344-65535 7 0.08% 99.89% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-73727 2 0.02% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::73728-81919 4 0.05% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::90112-98303 2 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walks 8217 # Table walker walks requested +system.cpu0.itb.walker.walksShort 8217 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 2960 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5117 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 140 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 8077 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1443.543395 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 6102.235478 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-8191 7600 94.09% 94.09% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::8192-16383 232 2.87% 96.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::16384-24575 133 1.65% 98.61% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::24576-32767 50 0.62% 99.23% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-40959 22 0.27% 99.50% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::40960-49151 13 0.16% 99.67% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::49152-57343 11 0.14% 99.80% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::57344-65535 2 0.02% 99.83% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-73727 8 0.10% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::73728-81919 1 0.01% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::81920-90111 4 0.05% 99.99% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::98304-106495 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 8375 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2444 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12500.308511 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 9992.698413 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 7939.202624 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 801 32.77% 32.77% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 949 38.83% 71.60% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 632 25.86% 97.46% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 25 1.02% 98.49% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 24 0.98% 99.47% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::40960-49151 9 0.37% 99.84% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::49152-57343 2 0.08% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkWaitTime::total 8077 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2488 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 13472.467846 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11168.518762 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 7984.929111 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 793 31.87% 31.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 981 39.43% 71.30% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 648 26.05% 97.35% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 24 0.96% 98.31% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 15 0.60% 98.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::40960-49151 24 0.96% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.92% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::57344-65535 1 0.04% 99.96% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::65536-73727 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2444 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 29185295284 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.914937 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.279656 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 2486739500 8.52% 8.52% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 26695454284 91.47% 99.99% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 2358500 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 523000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 145500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::5 74500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 29185295284 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1760 75.99% 75.99% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 556 24.01% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2316 # Table walker page sizes translated +system.cpu0.itb.walker.walkCompletionTime::total 2488 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 37746197376 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.883119 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.321811 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 4416616428 11.70% 11.70% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 33326087448 88.29% 99.99% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 2489000 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 727000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 244500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::5 33000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 37746197376 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1794 76.41% 76.41% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 554 23.59% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2348 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 8503 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 8503 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 8217 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 8217 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2316 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2316 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 10819 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 20234859 # ITB inst hits -system.cpu0.itb.inst_misses 8503 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2348 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2348 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 10565 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 20173848 # ITB inst hits +system.cpu0.itb.inst_misses 8217 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 181 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 456 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb 179 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 463 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2268 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2291 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1416 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1412 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 20243362 # ITB inst accesses -system.cpu0.itb.hits 20234859 # DTB hits -system.cpu0.itb.misses 8503 # DTB misses -system.cpu0.itb.accesses 20243362 # DTB accesses -system.cpu0.numCycles 106376136 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 20182065 # ITB inst accesses +system.cpu0.itb.hits 20173848 # DTB hits +system.cpu0.itb.misses 8217 # DTB misses +system.cpu0.itb.accesses 20182065 # DTB accesses +system.cpu0.numCycles 106431987 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 39965142 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 103919162 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 26894349 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 19302280 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 61475471 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3204102 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 133084 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 4359 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 386 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 482542 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 142714 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 389 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 20233629 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 371892 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3629 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 103806101 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.204244 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.303663 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 39926124 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 104046311 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 26812041 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 19219986 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 61721491 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3201846 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 134355 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 4118 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 472 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 336728 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 143479 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 355 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 20172603 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 372165 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3674 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 103868008 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.205189 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.307808 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 75119256 72.36% 72.36% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 3853264 3.71% 76.08% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 2394905 2.31% 78.38% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 8055629 7.76% 86.14% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1633408 1.57% 87.72% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 1025690 0.99% 88.71% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 6108914 5.88% 94.59% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 1037923 1.00% 95.59% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4577112 4.41% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 75224337 72.42% 72.42% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 3826153 3.68% 76.11% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 2403715 2.31% 78.42% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 7967440 7.67% 86.09% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1659017 1.60% 87.69% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 1036461 1.00% 88.69% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 6057785 5.83% 94.52% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 1065173 1.03% 95.54% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4627927 4.46% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 103806101 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.252823 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.976903 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 27584011 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 57734540 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 15584006 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1449686 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1453608 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1869283 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 150514 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 86108463 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 484067 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1453608 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 28423517 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 6508141 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 43695790 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 16185317 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 7539460 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 82326363 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 3052 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 1072870 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 278724 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 5472953 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 84763927 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 379438570 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 91864230 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 6406 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 71037693 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 13726234 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1533064 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 1439152 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 8446360 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 14835811 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 11457004 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1997727 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 2772041 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 79153572 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1058697 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 75784801 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 96696 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 11308863 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 24599963 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 115562 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 103806101 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.730061 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.422275 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 103868008 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.251917 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.977585 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 27603064 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 57749227 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 15599106 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1464170 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1452197 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1874763 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 150759 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 86325331 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 486551 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1452197 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 28440398 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 6572412 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 43697521 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 16217184 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 7488032 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 82550644 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 3098 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 1081958 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 289974 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 5413982 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 85027824 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 380373358 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 92135642 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 6326 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 71200016 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 13827808 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1531327 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 1437175 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 8438984 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 14879838 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 11477452 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1996170 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 2776563 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 79349721 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1058033 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 75951748 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 96660 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 11354988 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 24738171 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 114625 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 103868008 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.731233 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.423636 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 73542195 70.85% 70.85% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10050115 9.68% 80.53% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 7748986 7.46% 87.99% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 6432670 6.20% 94.19% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2352911 2.27% 96.46% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1476701 1.42% 97.88% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 1498599 1.44% 99.32% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 479431 0.46% 99.78% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 224493 0.22% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 73542868 70.80% 70.80% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10072511 9.70% 80.50% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 7759579 7.47% 87.97% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 6464332 6.22% 94.20% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2333365 2.25% 96.44% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1472075 1.42% 97.86% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 1515581 1.46% 99.32% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 481814 0.46% 99.78% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 225883 0.22% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 103806101 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 103868008 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 98458 8.93% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 1 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 516893 46.87% 55.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 487368 44.20% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 101947 9.17% 9.17% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 2 0.00% 9.17% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 9.17% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 9.17% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 9.17% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 9.17% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 9.17% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 9.17% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 9.17% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 9.17% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 9.17% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 9.17% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 9.17% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 9.17% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 9.17% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 9.17% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 9.17% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 9.17% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 9.17% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 9.17% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 9.17% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 9.17% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 9.17% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 9.17% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 9.17% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 9.17% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 9.17% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.17% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 9.17% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 527360 47.45% 56.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 481989 43.37% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 2186 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 50425393 66.54% 66.54% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 57237 0.08% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 4320 0.01% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 1 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 14387296 18.98% 85.61% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 10908366 14.39% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 2185 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 50526992 66.53% 66.53% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 57691 0.08% 66.60% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.60% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.60% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.60% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.60% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.60% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.60% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 66.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 4308 0.01% 66.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.61% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 14430381 19.00% 85.61% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 10930190 14.39% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 75784801 # Type of FU issued -system.cpu0.iq.rate 0.712423 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1102720 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.014551 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 256560915 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 91566516 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 73457837 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 14204 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 7630 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 6340 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 76877738 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 7597 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 359549 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 75951748 # Type of FU issued +system.cpu0.iq.rate 0.713618 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1111298 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.014632 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 256965506 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 91807957 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 73625831 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 13956 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 7486 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 6230 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 77053395 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 7466 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 363562 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2204717 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2719 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 54058 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1152347 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2216786 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2550 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 53728 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1148638 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 205467 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 94593 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 206531 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 94919 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1453608 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 5664191 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 635354 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 80356167 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 128884 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 14835811 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 11457004 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 551529 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 43992 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 579512 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 54058 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 250397 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 220538 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 470935 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 75169409 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 14142783 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 555867 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1452197 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 5712747 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 651844 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 80559572 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 134213 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 14879838 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 11477452 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 551306 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 44233 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 595893 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 53728 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 250776 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 220293 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 471069 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 75340518 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 14186156 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 551092 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 143898 # number of nop insts executed -system.cpu0.iew.exec_refs 24942986 # number of memory reference insts executed -system.cpu0.iew.exec_branches 14187310 # Number of branches executed -system.cpu0.iew.exec_stores 10800203 # Number of stores executed -system.cpu0.iew.exec_rate 0.706638 # Inst execution rate -system.cpu0.iew.wb_sent 74627910 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 73464177 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 38231116 # num instructions producing a value -system.cpu0.iew.wb_consumers 66477839 # num instructions consuming a value +system.cpu0.iew.exec_nop 151818 # number of nop insts executed +system.cpu0.iew.exec_refs 25009470 # number of memory reference insts executed +system.cpu0.iew.exec_branches 14210768 # Number of branches executed +system.cpu0.iew.exec_stores 10823314 # Number of stores executed +system.cpu0.iew.exec_rate 0.707875 # Inst execution rate +system.cpu0.iew.wb_sent 74794094 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 73632061 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 38328256 # num instructions producing a value +system.cpu0.iew.wb_consumers 66642343 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.690608 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.575096 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.691823 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.575134 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 11279021 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 943135 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 396816 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 101272480 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.681216 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.570732 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 11328784 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 943408 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 397191 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 101330688 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.682350 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.572509 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 74367990 73.43% 73.43% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 12119249 11.97% 85.40% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 6128079 6.05% 91.45% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2581969 2.55% 94.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1298466 1.28% 95.28% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 821679 0.81% 96.09% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 1839446 1.82% 97.91% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 396658 0.39% 98.30% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1718944 1.70% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 74383354 73.41% 73.41% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 12129402 11.97% 85.38% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 6135914 6.06% 91.43% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2613445 2.58% 94.01% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1268685 1.25% 95.26% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 826588 0.82% 96.08% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 1844857 1.82% 97.90% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 402953 0.40% 98.30% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1725490 1.70% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 101272480 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 56718354 # Number of instructions committed -system.cpu0.commit.committedOps 68988407 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 101330688 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 56867581 # Number of instructions committed +system.cpu0.commit.committedOps 69142978 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 22935751 # Number of memory references committed -system.cpu0.commit.loads 12631094 # Number of loads committed -system.cpu0.commit.membars 378784 # Number of memory barriers committed -system.cpu0.commit.branches 13402892 # Number of branches committed -system.cpu0.commit.fp_insts 6286 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 60396974 # Number of committed integer instructions. -system.cpu0.commit.function_calls 2623511 # Number of function calls committed. +system.cpu0.commit.refs 22991866 # Number of memory references committed +system.cpu0.commit.loads 12663052 # Number of loads committed +system.cpu0.commit.membars 379145 # Number of memory barriers committed +system.cpu0.commit.branches 13422378 # Number of branches committed +system.cpu0.commit.fp_insts 6158 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 60521589 # Number of committed integer instructions. +system.cpu0.commit.function_calls 2622248 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 45992810 66.67% 66.67% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 55529 0.08% 66.75% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.75% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.75% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.75% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.75% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.75% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.75% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.75% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.75% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.75% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.75% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.75% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.75% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.75% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.75% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.75% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.75% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.75% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.75% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.75% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.75% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.75% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.75% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.75% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 4317 0.01% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 46090829 66.66% 66.66% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 55975 0.08% 66.74% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.74% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.74% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.74% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.74% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.74% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.74% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.74% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.74% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.74% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.74% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.74% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.74% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.74% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.74% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.74% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.74% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.74% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.74% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.74% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.74% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.74% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.74% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.74% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 4308 0.01% 66.75% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.75% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.75% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.75% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 12631094 18.31% 85.06% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 10304657 14.94% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 12663052 18.31% 85.06% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 10328814 14.94% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 68988407 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1718944 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 167372763 # The number of ROB reads -system.cpu0.rob.rob_writes 163072923 # The number of ROB writes -system.cpu0.timesIdled 393865 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 2570035 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2956119679 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 56633353 # Number of Instructions Simulated -system.cpu0.committedOps 68903406 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.878330 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.878330 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.532388 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.532388 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 81817364 # number of integer regfile reads -system.cpu0.int_regfile_writes 46775146 # number of integer regfile writes -system.cpu0.fp_regfile_reads 16878 # number of floating regfile reads -system.cpu0.fp_regfile_writes 13235 # number of floating regfile writes -system.cpu0.cc_regfile_reads 265909763 # number of cc regfile reads -system.cpu0.cc_regfile_writes 27649979 # number of cc regfile writes -system.cpu0.misc_regfile_reads 144518865 # number of misc regfile reads -system.cpu0.misc_regfile_writes 724107 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 853909 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.982202 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 42514992 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 854421 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 49.758833 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 105520250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 184.898512 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 327.083689 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.361130 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.638835 # Average percentage of cache occupancy +system.cpu0.commit.op_class_0::total 69142978 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1725490 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 167648310 # The number of ROB reads +system.cpu0.rob.rob_writes 163485257 # The number of ROB writes +system.cpu0.timesIdled 393439 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 2563979 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2956083785 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 56777369 # Number of Instructions Simulated +system.cpu0.committedOps 69052766 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.874549 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.874549 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.533462 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.533462 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 82027611 # number of integer regfile reads +system.cpu0.int_regfile_writes 46869593 # number of integer regfile writes +system.cpu0.fp_regfile_reads 16807 # number of floating regfile reads +system.cpu0.fp_regfile_writes 13164 # number of floating regfile writes +system.cpu0.cc_regfile_reads 266520742 # number of cc regfile reads +system.cpu0.cc_regfile_writes 27747679 # number of cc regfile writes +system.cpu0.misc_regfile_reads 144321385 # number of misc regfile reads +system.cpu0.misc_regfile_writes 724502 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 852950 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.982213 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 42504025 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 853462 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 49.801895 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 105251500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 187.204537 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 324.777676 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.365634 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.634331 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999965 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 188 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 189859724 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 189859724 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 12422539 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 12908546 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 25331085 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 7676552 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 8235772 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 15912324 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 178433 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 183837 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 362270 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 209755 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 237006 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 446761 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 216045 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 243370 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 459415 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 20099091 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 21144318 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 41243409 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 20277524 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 21328155 # number of overall hits -system.cpu0.dcache.overall_hits::total 41605679 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 408353 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 423480 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 831833 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1950457 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1746190 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 3696647 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 84124 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 98955 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 183079 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13813 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 14039 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 27852 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21 # number of StoreCondReq misses +system.cpu0.dcache.tags.tag_accesses 189817658 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 189817658 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 12454816 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 12866965 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 25321781 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 7691483 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 8218685 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 15910168 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 178893 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 183845 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 362738 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 209855 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 236893 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 446748 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 216102 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 243311 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 459413 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 20146299 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 21085650 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 41231949 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 20325192 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 21269495 # number of overall hits +system.cpu0.dcache.overall_hits::total 41594687 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 412638 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 421416 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 834054 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1958462 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 1736177 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 3694639 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 85616 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 97979 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 183595 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13773 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 14074 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 27847 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 27 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::cpu1.data 34 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 55 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2358810 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 2169670 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 4528480 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2442934 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 2268625 # number of overall misses -system.cpu0.dcache.overall_misses::total 4711559 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6108609853 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 6466487368 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 12575097221 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 85969014596 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 79541032692 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 165510047288 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 182474999 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 208223500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 390698499 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 466006 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 533501 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 999507 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 92077624449 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 86007520060 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 178085144509 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 92077624449 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 86007520060 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 178085144509 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 12830892 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 13332026 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 26162918 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 9627009 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 9981962 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 19608971 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 262557 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 282792 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 545349 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 223568 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 251045 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 474613 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 216066 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 243404 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 459470 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 22457901 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 23313988 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 45771889 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 22720458 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 23596780 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 46317238 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.031826 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.031764 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.031794 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.202603 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.174935 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.188518 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.320403 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.349921 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.335710 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.061784 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.055922 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.058684 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000097 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_misses::total 61 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 2371100 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 2157593 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 4528693 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 2456716 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 2255572 # number of overall misses +system.cpu0.dcache.overall_misses::total 4712288 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6076761000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 6454165500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 12530926500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 84857330299 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 79343865125 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 164201195424 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 181836500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 208543500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 390380000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 611500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 544500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 1156000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 90934091299 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 85798030625 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 176732121924 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 90934091299 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 85798030625 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 176732121924 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 12867454 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 13288381 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 26155835 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 9649945 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 9954862 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 19604807 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 264509 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 281824 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 546333 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 223628 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 250967 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 474595 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 216129 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 243345 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 459474 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 22517399 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 23243243 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 45760642 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 22781908 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 23525067 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 46306975 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.032068 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.031713 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.031888 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.202951 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.174405 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.188456 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.323679 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.347660 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.336050 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.061589 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.056079 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.058675 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000125 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000140 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000120 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.105033 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.093063 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.098936 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.107521 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.096141 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.101724 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14959.140383 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15269.876660 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15117.333913 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44076.344465 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 45551.190129 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 44773.019249 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13210.381452 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14831.790014 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14027.664046 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22190.761905 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15691.205882 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 18172.854545 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39035.625781 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 39640.830200 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 39325.589273 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37691.408957 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 37911.739516 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 37797.498558 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 1124276 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 180492 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 53485 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 2944 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 21.020398 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 61.308424 # average number of cycles each access was blocked +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000133 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.105301 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.092827 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.098965 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.107836 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.095880 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.101762 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14726.615096 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15315.425850 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15024.118942 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43328.555928 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 45700.331893 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 44443.095908 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13202.388732 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14817.642461 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14018.745287 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22648.148148 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 16014.705882 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 18950.819672 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 38351.014845 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 39765.623371 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 39024.972972 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37014.490604 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 38038.258422 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 37504.524750 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 1148125 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 185430 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 52981 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 2987 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 21.670505 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 62.079009 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 704443 # number of writebacks -system.cpu0.dcache.writebacks::total 704443 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 195410 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 211050 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 406460 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1794100 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1602957 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 3397057 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 9538 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 8888 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18426 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1989510 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 1814007 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 3803517 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1989510 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 1814007 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 3803517 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 212943 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 212430 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 425373 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 156357 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 143233 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 299590 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 58111 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 64761 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 122872 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 4275 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5151 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9426 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21 # number of StoreCondReq MSHR misses +system.cpu0.dcache.writebacks::writebacks 703579 # number of writebacks +system.cpu0.dcache.writebacks::total 703579 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 198603 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 210557 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 409160 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1801482 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1593619 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 3395101 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 9550 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 9160 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18710 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2000085 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1804176 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 3804261 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2000085 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1804176 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 3804261 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 214035 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 210859 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 424894 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 156980 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 142558 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 299538 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 58648 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 64092 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 122740 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 4223 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 4914 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9137 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 27 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 34 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 55 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 369300 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 355663 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 724963 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 427411 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 420424 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 847835 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16558 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 14569 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.StoreCondReq_mshr_misses::total 61 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 371015 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 353417 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 724432 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 429663 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 417509 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 847172 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16542 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 14585 # number of ReadReq MSHR uncacheable system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31127 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16166 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 11418 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16149 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 11435 # number of WriteReq MSHR uncacheable system.cpu0.dcache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 32724 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 25987 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 32691 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 26020 # number of overall MSHR uncacheable misses system.cpu0.dcache.overall_mshr_uncacheable_misses::total 58711 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2911652660 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2946522646 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5858175306 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7110951020 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6670158760 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 13781109780 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 777722500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 894500250 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1672222750 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 53569251 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 82009500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 135578751 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 434494 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 482499 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 916993 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10022603680 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 9616681406 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 19639285086 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10800326180 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 10511181656 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 21311507836 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3107181500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2733353000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5840534500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2374455377 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2136736500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4511191877 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5481636877 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 4870089500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10351726377 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016596 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.015934 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016259 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.016241 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014349 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015278 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.221327 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.229006 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225309 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.019122 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.020518 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.019860 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000097 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3018980500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 3044091500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6063072000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7145217382 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6750047429 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 13895264811 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 806467500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 918616000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1725083500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 54857500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 82625000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 137482500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 584500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 510500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1095000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10164197882 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 9794138929 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 19958336811 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10970665382 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 10712754929 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 21683420311 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3143585500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2772334000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5915919500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2404168377 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2168590500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4572758877 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5547753877 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 4940924500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10488678377 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016634 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.015868 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.016267 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014320 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015279 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.221724 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.227419 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224662 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.018884 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.019580 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.019252 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000125 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000140 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000120 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016444 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.015255 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.015839 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018812 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.017817 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018305 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13673.389874 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13870.558047 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13771.855068 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45478.942548 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 46568.589361 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45999.899129 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13383.395571 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13812.329180 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13609.469611 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12530.818947 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15921.083285 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14383.487269 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20690.190476 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14191.147059 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 16672.600000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27139.462984 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27038.745683 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27090.051611 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25269.181607 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25001.383499 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25136.386014 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 187654.396666 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 187614.318073 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 187635.637871 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 146879.585364 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 187137.545980 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163543.789044 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 167511.211252 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 187404.837034 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 176316.642145 # average overall mshr uncacheable latency +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000133 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016477 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.015205 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.015831 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018860 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.017747 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018295 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14105.078609 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14436.621154 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14269.610774 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45516.737049 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47349.481818 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46388.988412 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13750.980426 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14332.771641 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14054.778393 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12990.172863 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16814.204314 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15046.787786 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21648.148148 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 15014.705882 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 17950.819672 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27395.652149 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27712.698962 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27550.324683 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25533.186199 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25658.740121 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25595.062527 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190036.603796 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 190081.179294 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190057.490282 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 148874.133197 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 189644.993441 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 165775.771353 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 169702.789055 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 189889.488855 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 178649.288498 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1944350 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.567211 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 39122099 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1944862 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 20.115617 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 9678062250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 228.929190 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 282.638021 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.447127 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.552027 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999155 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 1944870 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.570452 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 39033281 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1945382 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 20.064584 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 9679828500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 227.356025 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 284.214426 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.444055 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.555106 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999161 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 236 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 145 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 43155983 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 43155983 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 19191895 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 19930204 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 39122099 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 19191895 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 19930204 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 39122099 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 19191895 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 19930204 # number of overall hits -system.cpu0.icache.overall_hits::total 39122099 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1041065 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 1047869 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 2088934 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1041065 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 1047869 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 2088934 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1041065 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 1047869 # number of overall misses -system.cpu0.icache.overall_misses::total 2088934 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14016266373 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 14162867905 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 28179134278 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 14016266373 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 14162867905 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 28179134278 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 14016266373 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 14162867905 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 28179134278 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 20232960 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 20978073 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 41211033 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 20232960 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 20978073 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 41211033 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 20232960 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 20978073 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 41211033 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.051454 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.049951 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.050689 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.051454 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.049951 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.050689 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.051454 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.049951 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.050689 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13463.392173 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13515.876417 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13489.719770 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13463.392173 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13515.876417 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13489.719770 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13463.392173 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13515.876417 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13489.719770 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 10636 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 43073652 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 43073652 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 19127800 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 19905481 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 39033281 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 19127800 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 19905481 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 39033281 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 19127800 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 19905481 # number of overall hits +system.cpu0.icache.overall_hits::total 39033281 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1044128 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 1050765 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 2094893 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1044128 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 1050765 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 2094893 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1044128 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 1050765 # number of overall misses +system.cpu0.icache.overall_misses::total 2094893 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14016783986 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 14160518990 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 28177302976 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 14016783986 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 14160518990 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 28177302976 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 14016783986 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 14160518990 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 28177302976 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 20171928 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 20956246 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 41128174 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 20171928 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 20956246 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 41128174 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 20171928 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 20956246 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 41128174 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.051761 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.050141 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.050936 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.051761 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.050141 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.050936 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.051761 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.050141 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.050936 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13424.392398 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13476.390049 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13450.473593 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13424.392398 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13476.390049 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13450.473593 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13424.392398 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13476.390049 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13450.473593 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 10866 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 597 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 629 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.815745 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.275040 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 71345 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 72638 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 143983 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 71345 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu1.inst 72638 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 143983 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 71345 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu1.inst 72638 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 143983 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 969720 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 975231 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1944951 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 969720 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 975231 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1944951 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 969720 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 975231 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1944951 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 666 # number of ReadReq MSHR uncacheable -system.cpu0.icache.ReadReq_mshr_uncacheable::total 666 # number of ReadReq MSHR uncacheable -system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 666 # number of overall MSHR uncacheable misses -system.cpu0.icache.overall_mshr_uncacheable_misses::total 666 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11896534814 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 12012713558 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 23909248372 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11896534814 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 12012713558 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 23909248372 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11896534814 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 12012713558 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 23909248372 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 52863250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 52863250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 52863250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 52863250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.047928 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.046488 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.047195 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.047928 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.046488 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.047195 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.047928 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.046488 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.047195 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12268.010162 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12317.813480 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12292.982380 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12268.010162 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12317.813480 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12292.982380 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12268.010162 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12317.813480 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12292.982380 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 79374.249249 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 79374.249249 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 79374.249249 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 79374.249249 # average overall mshr uncacheable latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 74230 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 75184 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 149414 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 74230 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu1.inst 75184 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 149414 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 74230 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu1.inst 75184 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 149414 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 969898 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 975581 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1945479 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 969898 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 975581 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1945479 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 969898 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 975581 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1945479 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 670 # number of ReadReq MSHR uncacheable +system.cpu0.icache.ReadReq_mshr_uncacheable::total 670 # number of ReadReq MSHR uncacheable +system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 670 # number of overall MSHR uncacheable misses +system.cpu0.icache.overall_mshr_uncacheable_misses::total 670 # number of overall MSHR uncacheable misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12381694490 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 12496898492 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 24878592982 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12381694490 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 12496898492 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 24878592982 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12381694490 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 12496898492 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 24878592982 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 52946500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 52946500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 52946500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 52946500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.048082 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.046553 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.047303 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.048082 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.046553 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.047303 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.048082 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.046553 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.047303 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12765.975896 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12809.698520 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12787.901068 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12765.975896 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12809.698520 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12787.901068 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12765.975896 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12809.698520 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12787.901068 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 79024.626866 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 79024.626866 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 79024.626866 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 79024.626866 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 27831531 # Number of BP lookups -system.cpu1.branchPred.condPredicted 14488346 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 557776 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 17618092 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 13095982 # Number of BTB hits +system.cpu1.branchPred.lookups 27779338 # Number of BP lookups +system.cpu1.branchPred.condPredicted 14456404 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 556707 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 17586832 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 13077233 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 74.332578 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 6872630 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 30030 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 74.358094 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 6867114 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 29983 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1322,88 +1340,90 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 58148 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 58148 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 20423 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 13441 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 24284 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 33864 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 507.057642 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 3287.460249 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-16383 33558 99.10% 99.10% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::16384-32767 245 0.72% 99.82% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-49151 40 0.12% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::49152-65535 17 0.05% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-81919 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walks 59343 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 59343 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 20532 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 13405 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 25406 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 33937 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 563.264284 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 3642.212390 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-16383 33612 99.04% 99.04% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::16384-32767 250 0.74% 99.78% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::32768-49151 49 0.14% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::49152-65535 14 0.04% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-81919 8 0.02% 99.99% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::81920-98303 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::98304-114687 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::98304-114687 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::114688-131071 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::131072-147455 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 33864 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 11833 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 12004.944308 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 9742.881321 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 7470.572043 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 3519 29.74% 29.74% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 5647 47.72% 77.46% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 2322 19.62% 97.08% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 174 1.47% 98.55% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-40959 60 0.51% 99.06% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 104 0.88% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-57343 1 0.01% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::57344-65535 3 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::81920-90111 3 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 11833 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 89903617428 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.686126 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.480378 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-1 89833985928 99.92% 99.92% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2-3 50516000 0.06% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-5 9974500 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6-7 3130500 0.00% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-9 1885500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10-11 1212500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-13 715000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14-15 1356000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-17 345000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::18-19 227000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::20-21 44000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::22-23 32500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::24-25 52500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::26-27 22500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::28-29 23000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::30-31 95000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 89903617428 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 3585 68.60% 68.60% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 1641 31.40% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 5226 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 58148 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkWaitTime::total 33937 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 12361 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 12657.592428 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 10412.763280 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 7705.801044 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 3725 30.14% 30.14% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 5842 47.26% 77.40% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 2426 19.63% 97.02% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 136 1.10% 98.12% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 110 0.89% 99.01% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 110 0.89% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-57343 5 0.04% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-73727 2 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::73728-81919 2 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::81920-90111 3 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 12361 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 85582012132 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.698276 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.478879 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-1 85506656132 99.91% 99.91% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2-3 54226500 0.06% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-5 10815500 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6-7 3396500 0.00% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-9 2104000 0.00% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10-11 1227000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-13 804500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14-15 1696500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-17 468000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::18-19 271500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::20-21 107000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::22-23 23500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::24-25 101500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::26-27 14500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::28-29 14000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::30-31 85500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 85582012132 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 3538 68.22% 68.22% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 1648 31.78% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 5186 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 59343 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 58148 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5226 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 59343 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5186 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5226 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 63374 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5186 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 64529 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 14522717 # DTB read hits -system.cpu1.dtb.read_misses 49745 # DTB read misses -system.cpu1.dtb.write_hits 10695995 # DTB write hits -system.cpu1.dtb.write_misses 8403 # DTB write misses -system.cpu1.dtb.flush_tlb 177 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 461 # Number of times TLB was flushed by MVA +system.cpu1.dtb.read_hits 14473413 # DTB read hits +system.cpu1.dtb.read_misses 50516 # DTB read misses +system.cpu1.dtb.write_hits 10662986 # DTB write hits +system.cpu1.dtb.write_misses 8827 # DTB write misses +system.cpu1.dtb.flush_tlb 179 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 454 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 3436 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 922 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 1213 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 3428 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 911 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 1182 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 578 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 14572462 # DTB read accesses -system.cpu1.dtb.write_accesses 10704398 # DTB write accesses +system.cpu1.dtb.perms_faults 534 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 14523929 # DTB read accesses +system.cpu1.dtb.write_accesses 10671813 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 25218712 # DTB hits -system.cpu1.dtb.misses 58148 # DTB misses -system.cpu1.dtb.accesses 25276860 # DTB accesses +system.cpu1.dtb.hits 25136399 # DTB hits +system.cpu1.dtb.misses 59343 # DTB misses +system.cpu1.dtb.accesses 25195742 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1433,387 +1453,389 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 7828 # Table walker walks requested -system.cpu1.itb.walker.walksShort 7828 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2631 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 5055 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 142 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 7686 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 1468.839448 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 6467.961047 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-8191 7241 94.21% 94.21% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::8192-16383 210 2.73% 96.94% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::16384-24575 113 1.47% 98.41% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::24576-32767 52 0.68% 99.09% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-40959 17 0.22% 99.31% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::40960-49151 18 0.23% 99.54% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::49152-57343 9 0.12% 99.66% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::57344-65535 10 0.13% 99.79% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-73727 7 0.09% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::73728-81919 6 0.08% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::81920-90111 3 0.04% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 7686 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 2491 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 12581.694099 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 10170.903635 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 7854.515527 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-8191 763 30.63% 30.63% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-16383 1045 41.95% 72.58% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-24575 622 24.97% 97.55% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-32767 29 1.16% 98.72% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-40959 22 0.88% 99.60% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-49151 6 0.24% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::57344-65535 1 0.04% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-73727 1 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::98304-106495 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 2491 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 25478819488 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.779989 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.414945 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 5610872428 22.02% 22.02% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 19864341560 77.96% 99.99% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 2357000 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 850000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 398500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 25478819488 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 1770 75.35% 75.35% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 579 24.65% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 2349 # Table walker page sizes translated +system.cpu1.itb.walker.walks 8383 # Table walker walks requested +system.cpu1.itb.walker.walksShort 8383 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 3253 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 4959 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 171 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 8212 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1247.503653 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 5444.991786 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-8191 7787 94.82% 94.82% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::8192-16383 188 2.29% 97.11% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::16384-24575 140 1.70% 98.82% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::24576-32767 47 0.57% 99.39% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-40959 15 0.18% 99.57% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::40960-49151 15 0.18% 99.76% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::49152-57343 8 0.10% 99.85% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::57344-65535 6 0.07% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-73727 4 0.05% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::81920-90111 2 0.02% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 8212 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 2522 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 13607.454401 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 11346.951670 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 7824.124854 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-4095 43 1.70% 1.70% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 713 28.27% 29.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 591 23.43% 53.41% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 450 17.84% 71.25% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 33 1.31% 72.56% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 613 24.31% 96.87% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 21 0.83% 97.70% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 20 0.79% 98.49% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-36863 10 0.40% 98.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 3 0.12% 99.01% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 20 0.79% 99.80% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::45056-49151 3 0.12% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::53248-57343 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 2522 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 25452156488 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.888283 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.315639 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 2847537836 11.19% 11.19% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 22601300152 88.80% 99.99% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 2634500 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 584500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 99500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 25452156488 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 1775 75.50% 75.50% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 576 24.50% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 2351 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 7828 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 7828 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 8383 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 8383 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2349 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2349 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 10177 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 20979938 # ITB inst hits -system.cpu1.itb.inst_misses 7828 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2351 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2351 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 10734 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 20958158 # ITB inst hits +system.cpu1.itb.inst_misses 8383 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 177 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 461 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb 179 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 454 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2294 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2298 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1372 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1383 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 20987766 # ITB inst accesses -system.cpu1.itb.hits 20979938 # DTB hits -system.cpu1.itb.misses 7828 # DTB misses -system.cpu1.itb.accesses 20987766 # DTB accesses -system.cpu1.numCycles 108755615 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 20966541 # ITB inst accesses +system.cpu1.itb.hits 20958158 # DTB hits +system.cpu1.itb.misses 8383 # DTB misses +system.cpu1.itb.accesses 20966541 # DTB accesses +system.cpu1.numCycles 108767456 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 40802320 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 108613899 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 27831531 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 19968612 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 63156510 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3276855 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 120748 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 7463 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 413 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 335058 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 133595 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 290 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 20978077 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 379105 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3473 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 106194788 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.229505 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.326126 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 40797494 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 108309619 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 27779338 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 19944347 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 62902331 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3273623 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 135203 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 7501 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 353 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 608716 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 138611 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 328 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 20956250 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 381072 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3851 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 106227312 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.226074 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.322776 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 76382363 71.93% 71.93% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 3967856 3.74% 75.66% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 2509209 2.36% 78.03% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 8248224 7.77% 85.79% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1616537 1.52% 87.32% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 1210559 1.14% 88.46% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 6288171 5.92% 94.38% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 1186864 1.12% 95.49% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4785005 4.51% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 76467157 71.98% 71.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 3961882 3.73% 75.71% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 2508117 2.36% 78.08% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 8239256 7.76% 85.83% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1628076 1.53% 87.36% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 1204845 1.13% 88.50% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 6274984 5.91% 94.41% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 1183680 1.11% 95.52% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4759315 4.48% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 106194788 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.255909 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.998697 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 27865394 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 59086633 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 16014101 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 1741536 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1486862 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 2014125 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 153633 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 90617334 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 499096 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1486862 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 28829421 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 4993628 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 46364703 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 16784538 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 7735362 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 86665296 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 1758 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 1681489 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 204965 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 5046479 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 89687558 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 399294691 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 96716693 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 5355 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 75738735 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 13948807 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1608168 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1506785 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 10100252 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 15391291 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 11882778 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 2188376 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 2888870 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 83375619 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1158159 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 79910899 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 92494 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 11441232 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 25615832 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 107265 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 106194788 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.752494 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.434563 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 106227312 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.255401 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.995791 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 27883552 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 59140248 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 15967546 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 1750379 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1485269 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 2004727 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 153597 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 90349816 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 499958 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1485269 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 28837036 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 5092551 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 46434989 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 16757814 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 7619325 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 86416848 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 2460 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 1673796 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 189232 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 4958723 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 89422811 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 398213792 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 96413461 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 5558 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 75531757 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 13891038 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1607608 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1506576 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 10031791 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 15342800 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 11846385 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 2170677 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 2932432 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 83143036 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1157387 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 79677045 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 92227 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 11399767 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 25586754 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 106787 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 106227312 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.750062 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.431163 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 74167073 69.84% 69.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 10703729 10.08% 79.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 8178605 7.70% 87.62% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 6800959 6.40% 94.03% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 2513016 2.37% 96.39% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1570037 1.48% 97.87% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1528184 1.44% 99.31% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 489750 0.46% 99.77% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 243435 0.23% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 74225476 69.87% 69.87% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 10735161 10.11% 79.98% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 8165707 7.69% 87.67% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 6810651 6.41% 94.08% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 2489155 2.34% 96.42% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1551071 1.46% 97.88% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1525154 1.44% 99.32% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 483878 0.46% 99.77% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 241059 0.23% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 106194788 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 106227312 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 110018 9.66% 9.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 6 0.00% 9.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 521312 45.77% 55.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 507746 44.58% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 112109 9.87% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 6 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 520489 45.82% 55.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 503315 44.31% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 151 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 53586361 67.06% 67.06% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 59349 0.07% 67.13% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 67.13% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 67.13% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 67.13% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 67.13% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 67.13% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 67.13% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 67.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 67.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 67.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 1 0.00% 67.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 67.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 67.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 67.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 67.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 67.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 67.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 67.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 1 0.00% 67.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 2 0.00% 67.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 4262 0.01% 67.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 67.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 1 0.00% 67.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.14% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 14931900 18.69% 85.82% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 11328871 14.18% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 152 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 53438266 67.07% 67.07% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 58943 0.07% 67.14% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 67.14% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 67.14% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 67.14% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 67.14% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 67.14% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 67.14% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 67.14% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 67.14% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 67.14% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 1 0.00% 67.14% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 67.14% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 67.14% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 67.14% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 67.14% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 67.14% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 67.14% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.14% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 67.14% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.14% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.14% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 1 0.00% 67.14% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.14% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 2 0.00% 67.14% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 4274 0.01% 67.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 67.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 67.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.15% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 14882536 18.68% 85.83% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 11292868 14.17% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 79910899 # Type of FU issued -system.cpu1.iq.rate 0.734775 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 1139082 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.014254 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 267236203 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 96019084 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 77543645 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 11959 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 6290 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5191 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 81043377 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 6453 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 351971 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 79677045 # Type of FU issued +system.cpu1.iq.rate 0.732545 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 1135919 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.014257 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 266797245 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 95743822 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 77316154 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 12303 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 6570 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 5329 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 80806190 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 6622 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 349291 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2202451 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 2360 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 51509 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1138977 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2194104 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 2343 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 51353 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1130901 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 192557 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 108870 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 191600 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 108001 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1486862 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 4086013 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 663456 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 84657415 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 129656 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 15391291 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 11882778 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 585252 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 42277 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 608480 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 51509 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 260306 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 223242 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 483548 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 79294806 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 14687602 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 558095 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1485269 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 4109384 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 740435 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 84415132 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 132598 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 15342800 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 11846385 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 585452 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 40704 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 687401 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 51353 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 260476 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 222264 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 482740 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 79065408 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 14638962 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 552436 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 123637 # number of nop insts executed -system.cpu1.iew.exec_refs 25906137 # number of memory reference insts executed -system.cpu1.iew.exec_branches 14775343 # Number of branches executed -system.cpu1.iew.exec_stores 11218535 # Number of stores executed -system.cpu1.iew.exec_rate 0.729110 # Inst execution rate -system.cpu1.iew.wb_sent 78721983 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 77548836 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 40818570 # num instructions producing a value -system.cpu1.iew.wb_consumers 71550295 # num instructions consuming a value +system.cpu1.iew.exec_nop 114709 # number of nop insts executed +system.cpu1.iew.exec_refs 25822462 # number of memory reference insts executed +system.cpu1.iew.exec_branches 14738058 # Number of branches executed +system.cpu1.iew.exec_stores 11183500 # Number of stores executed +system.cpu1.iew.exec_rate 0.726922 # Inst execution rate +system.cpu1.iew.wb_sent 78493230 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 77321483 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 40676282 # num instructions producing a value +system.cpu1.iew.wb_consumers 71272745 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.713056 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.570488 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.710888 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.570713 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 11482053 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 1050894 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 406174 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 103612507 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.706116 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.593552 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 11437303 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 1050600 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 405128 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 103651619 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.703948 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.590010 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 75208979 72.59% 72.59% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 12628786 12.19% 84.78% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6551089 6.32% 91.10% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 2721278 2.63% 93.72% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1429301 1.38% 95.10% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 940289 0.91% 96.01% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1888025 1.82% 97.83% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 437231 0.42% 98.26% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1807529 1.74% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 75257268 72.61% 72.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 12658548 12.21% 84.82% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6546278 6.32% 91.13% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 2731593 2.64% 93.77% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1415647 1.37% 95.14% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 932934 0.90% 96.04% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1873819 1.81% 97.84% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 434966 0.42% 98.26% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1800566 1.74% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 103612507 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 60426665 # Number of instructions committed -system.cpu1.commit.committedOps 73162446 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 103651619 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 60242910 # Number of instructions committed +system.cpu1.commit.committedOps 72965345 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 23932641 # Number of memory references committed -system.cpu1.commit.loads 13188840 # Number of loads committed -system.cpu1.commit.membars 435550 # Number of memory barriers committed -system.cpu1.commit.branches 14000562 # Number of branches committed -system.cpu1.commit.fp_insts 5142 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 64124542 # Number of committed integer instructions. -system.cpu1.commit.function_calls 2721670 # Number of function calls committed. +system.cpu1.commit.refs 23864180 # Number of memory references committed +system.cpu1.commit.loads 13148696 # Number of loads committed +system.cpu1.commit.membars 435175 # Number of memory barriers committed +system.cpu1.commit.branches 13969261 # Number of branches committed +system.cpu1.commit.fp_insts 5270 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 63961435 # Number of committed integer instructions. +system.cpu1.commit.function_calls 2719031 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 49168040 67.20% 67.20% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 57503 0.08% 67.28% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.28% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.28% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.28% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.28% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.28% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.28% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.28% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.28% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.28% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.28% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.28% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.28% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.28% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.28% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.28% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.28% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.28% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.28% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.28% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.28% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.28% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.28% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.28% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 4262 0.01% 67.29% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 49039858 67.21% 67.21% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 57036 0.08% 67.29% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.29% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.29% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.29% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.29% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.29% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.29% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.29% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.29% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.29% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.29% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.29% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.29% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.29% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.29% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.29% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.29% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.29% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.29% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.29% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.29% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.29% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.29% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.29% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 4271 0.01% 67.29% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.29% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.29% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.29% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 13188840 18.03% 85.32% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 10743801 14.68% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 13148696 18.02% 85.31% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 10715484 14.69% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 73162446 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1807529 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 173729017 # The number of ROB reads -system.cpu1.rob.rob_writes 171875858 # The number of ROB writes -system.cpu1.timesIdled 390006 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 2560827 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2437360736 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 60356761 # Number of Instructions Simulated -system.cpu1.committedOps 73092542 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.801880 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.801880 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.554976 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.554976 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 86251314 # number of integer regfile reads -system.cpu1.int_regfile_writes 49415173 # number of integer regfile writes -system.cpu1.fp_regfile_reads 15994 # number of floating regfile reads -system.cpu1.fp_regfile_writes 13022 # number of floating regfile writes -system.cpu1.cc_regfile_reads 279979126 # number of cc regfile reads -system.cpu1.cc_regfile_writes 29562027 # number of cc regfile writes -system.cpu1.misc_regfile_reads 148792397 # number of misc regfile reads -system.cpu1.misc_regfile_writes 795609 # number of misc regfile writes +system.cpu1.commit.op_class_0::total 72965345 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1800566 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 173538824 # The number of ROB reads +system.cpu1.rob.rob_writes 171385524 # The number of ROB writes +system.cpu1.timesIdled 389774 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 2540144 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2437281840 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 60178217 # Number of Instructions Simulated +system.cpu1.committedOps 72900652 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.807422 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.807422 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.553274 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.553274 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 85982923 # number of integer regfile reads +system.cpu1.int_regfile_writes 49280931 # number of integer regfile writes +system.cpu1.fp_regfile_reads 16090 # number of floating regfile reads +system.cpu1.fp_regfile_writes 13091 # number of floating regfile writes +system.cpu1.cc_regfile_reads 279167136 # number of cc regfile reads +system.cpu1.cc_regfile_writes 29456801 # number of cc regfile writes +system.cpu1.misc_regfile_reads 148724045 # number of misc regfile reads +system.cpu1.misc_regfile_writes 795207 # number of misc regfile writes system.iobus.trans_dist::ReadReq 30198 # Transaction distribution system.iobus.trans_dist::ReadResp 30198 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution -system.iobus.trans_dist::WriteResp 22790 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.iobus.trans_dist::WriteResp 59014 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) @@ -1904,356 +1926,368 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 198975032 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 187534443 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36852019 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36770000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36409 # number of replacements -system.iocache.tags.tagsinuse 0.981278 # Cycle average of tags in use -system.iocache.tags.total_refs 30 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36425 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0.000824 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 234149213000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.981278 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.061330 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.061330 # Average percentage of cache occupancy +system.iocache.tags.replacements 36410 # number of replacements +system.iocache.tags.tagsinuse 0.981092 # Cycle average of tags in use +system.iocache.tags.total_refs 29 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 36426 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0.000796 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 234155624000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 0.981092 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.061318 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.061318 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328227 # Number of tag accesses -system.iocache.tags.data_accesses 328227 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::realview.ide 29 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 29 # number of WriteInvalidateReq hits +system.iocache.tags.tag_accesses 328228 # Number of tag accesses +system.iocache.tags.data_accesses 328228 # Number of data accesses +system.iocache.WriteLineReq_hits::realview.ide 28 # number of WriteLineReq hits +system.iocache.WriteLineReq_hits::total 28 # number of WriteLineReq hits system.iocache.ReadReq_misses::realview.ide 249 # number of ReadReq misses system.iocache.ReadReq_misses::total 249 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 36195 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 36195 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::realview.ide 36196 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 36196 # number of WriteLineReq misses system.iocache.demand_misses::realview.ide 249 # number of demand (read+write) misses system.iocache.demand_misses::total 249 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 249 # number of overall misses system.iocache.overall_misses::total 249 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 30962377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 30962377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6648903636 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 6648903636 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 30962377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 30962377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 30962377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 30962377 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 30881877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 30881877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4272011566 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4272011566 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 30881877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 30881877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 30881877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 30881877 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 249 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ide 249 # number of demand (read+write) accesses system.iocache.demand_accesses::total 249 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ide 249 # number of overall (read+write) accesses system.iocache.overall_accesses::total 249 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.999199 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 0.999199 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::realview.ide 0.999227 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 0.999227 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124346.895582 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124346.895582 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183696.743639 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 183696.743639 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124346.895582 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124346.895582 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124346.895582 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124346.895582 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 22802 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 124023.602410 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124023.602410 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118024.410598 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118024.410598 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124023.602410 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124023.602410 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124023.602410 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124023.602410 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3472 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.567396 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 36160 # number of writebacks -system.iocache.writebacks::total 36160 # number of writebacks +system.iocache.writebacks::writebacks 36161 # number of writebacks +system.iocache.writebacks::total 36161 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ide 249 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36195 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 36195 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 36196 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 36196 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ide 249 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 249 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 249 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 17850377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 17850377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4766725674 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4766725674 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 17850377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 17850377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 17850377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 17850377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 18431877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 18431877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2462211566 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2462211566 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 18431877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 18431877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 18431877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 18431877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 0.999199 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.999199 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.999227 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.999227 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 71688.261044 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 71688.261044 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131695.694820 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131695.694820 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 71688.261044 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 71688.261044 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 71688.261044 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 71688.261044 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74023.602410 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 74023.602410 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68024.410598 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68024.410598 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 74023.602410 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 74023.602410 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 74023.602410 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 74023.602410 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 104656 # number of replacements -system.l2c.tags.tagsinuse 65129.158587 # Cycle average of tags in use -system.l2c.tags.total_refs 3113742 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 169901 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 18.326802 # Average number of references to valid blocks. +system.l2c.tags.replacements 104591 # number of replacements +system.l2c.tags.tagsinuse 65128.853062 # Cycle average of tags in use +system.l2c.tags.total_refs 5158175 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 169835 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 30.371684 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 48669.329761 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 43.033999 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 48560.603393 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 44.868379 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000245 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4678.591805 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2387.812073 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 44.916630 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 5867.753400 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3437.720673 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.742635 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000657 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 4741.126354 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2359.678514 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 45.227842 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 5921.248068 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3456.100266 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.740976 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000685 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.071390 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.036435 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000685 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.089535 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.052455 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.993792 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 70 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65175 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 70 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 366 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3243 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 9051 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52499 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.001068 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.994492 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 29235849 # Number of tag accesses -system.l2c.tags.data_accesses 29235849 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 36383 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 8250 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 959469 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 268247 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 36362 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 7924 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 964356 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 274193 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2555184 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 704443 # number of Writeback hits -system.l2c.Writeback_hits::total 704443 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 48 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 39 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 87 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 14 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 32 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 46 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 82853 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 73309 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 156162 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 36383 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 8250 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 959469 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 351100 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 36362 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 7924 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 964356 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 347502 # number of demand (read+write) hits -system.l2c.demand_hits::total 2711346 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 36383 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 8250 # number of overall hits -system.l2c.overall_hits::cpu0.inst 959469 # number of overall hits -system.l2c.overall_hits::cpu0.data 351100 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 36362 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 7924 # number of overall hits -system.l2c.overall_hits::cpu1.inst 964356 # number of overall hits -system.l2c.overall_hits::cpu1.data 347502 # number of overall hits -system.l2c.overall_hits::total 2711346 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 68 # number of ReadReq misses +system.l2c.tags.occ_percent::cpu0.inst 0.072344 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.036006 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000690 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.090351 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.052736 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.993787 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 74 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65170 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 74 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 365 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3250 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 9056 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52484 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.001129 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.994415 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 45590460 # Number of tag accesses +system.l2c.tags.data_accesses 45590460 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 36255 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 7974 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 36433 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 8351 # number of ReadReq hits +system.l2c.ReadReq_hits::total 89013 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 703579 # number of Writeback hits +system.l2c.Writeback_hits::total 703579 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 56 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 38 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 94 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 19 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 29 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 48 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 83887 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 72292 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 156179 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 959569 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 964750 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 1924319 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 270036 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 271500 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 541536 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 36255 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 7974 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 959569 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 353923 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 36433 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 8351 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 964750 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 343792 # number of demand (read+write) hits +system.l2c.demand_hits::total 2711047 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 36255 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 7974 # number of overall hits +system.l2c.overall_hits::cpu0.inst 959569 # number of overall hits +system.l2c.overall_hits::cpu0.data 353923 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 36433 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 8351 # number of overall hits +system.l2c.overall_hits::cpu1.inst 964750 # number of overall hits +system.l2c.overall_hits::cpu1.data 343792 # number of overall hits +system.l2c.overall_hits::total 2711047 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 70 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 10143 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 7063 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 63 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 10750 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 8134 # number of ReadReq misses -system.l2c.ReadReq_misses::total 36222 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1453 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1281 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2734 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 7 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 2 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 9 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 72022 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 68619 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140641 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 68 # number of demand (read+write) misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 72 # number of ReadReq misses +system.l2c.ReadReq_misses::total 143 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1471 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1262 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2733 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 8 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 5 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 13 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 71586 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 68983 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 140569 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 10198 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 10688 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 20886 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 6850 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 8348 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 15198 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.dtb.walker 70 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 10143 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 79085 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 63 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 10750 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 76753 # number of demand (read+write) misses -system.l2c.demand_misses::total 176863 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 68 # number of overall misses +system.l2c.demand_misses::cpu0.inst 10198 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 78436 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 72 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 10688 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 77331 # number of demand (read+write) misses +system.l2c.demand_misses::total 176796 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 70 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 10143 # number of overall misses -system.l2c.overall_misses::cpu0.data 79085 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 63 # number of overall misses -system.l2c.overall_misses::cpu1.inst 10750 # number of overall misses -system.l2c.overall_misses::cpu1.data 76753 # number of overall misses -system.l2c.overall_misses::total 176863 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 5921750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 68750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 835233999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 610760750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 5497500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 894311500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 720028000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 3071822249 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 436986 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 406987 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 843973 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 141998 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 81000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 222998 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 6026469540 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 5704758320 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 11731227860 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 5921750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 68750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 835233999 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 6637230290 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 5497500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 894311500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 6424786320 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 14803050109 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 5921750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 68750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 835233999 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 6637230290 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 5497500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 894311500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 6424786320 # number of overall miss cycles -system.l2c.overall_miss_latency::total 14803050109 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 36451 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 8251 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 969612 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 275310 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 36425 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 7924 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 975106 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 282327 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2591406 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 704443 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 704443 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1501 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1320 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2821 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 21 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.overall_misses::cpu0.inst 10198 # number of overall misses +system.l2c.overall_misses::cpu0.data 78436 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 72 # number of overall misses +system.l2c.overall_misses::cpu1.inst 10688 # number of overall misses +system.l2c.overall_misses::cpu1.data 77331 # number of overall misses +system.l2c.overall_misses::total 176796 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 6042500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 68500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 6012000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 12123000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 460000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 400000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 860000 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 191000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 62000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 253000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 5970431000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 5726703500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 11697134500 # number of ReadExReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu0.inst 834109000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu1.inst 885703000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 1719812000 # number of ReadCleanReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 591630000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 736687500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 1328317500 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 6042500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 68500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 834109000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 6562061000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 6012000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 885703000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 6463391000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 14757387000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 6042500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 68500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 834109000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 6562061000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 6012000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 885703000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 6463391000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 14757387000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 36325 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 7975 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 36505 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 8351 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 89156 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 703579 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 703579 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1527 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1300 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2827 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 27 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 34 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 55 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 154875 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 141928 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 296803 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 36451 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 8251 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 969612 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 430185 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 36425 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 7924 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 975106 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 424255 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2888209 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 36451 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 8251 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 969612 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 430185 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 36425 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 7924 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 975106 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 424255 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2888209 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001866 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000121 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.010461 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.025655 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.001730 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.011024 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.028811 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.013978 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.968021 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.970455 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.969160 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.333333 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.058824 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.163636 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.465033 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.483478 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.473853 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001866 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000121 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.010461 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.183840 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.001730 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.011024 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.180912 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.061236 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001866 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000121 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.010461 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.183840 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.001730 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.011024 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.180912 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.061236 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 87084.558824 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 68750 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 82345.854185 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 86473.276228 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 87261.904762 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 83191.767442 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 88520.776985 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 84805.428993 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 300.747419 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 317.710383 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 308.695318 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 20285.428571 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 40500 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 24777.555556 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 83675.398351 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83136.716070 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 83412.574285 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 87084.558824 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 68750 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 82345.854185 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 83925.273946 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 87261.904762 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 83191.767442 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 83707.298998 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 83697.834533 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 87084.558824 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 68750 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 82345.854185 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 83925.273946 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 87261.904762 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 83191.767442 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 83707.298998 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 83697.834533 # average overall miss latency +system.l2c.SCUpgradeReq_accesses::total 61 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 155473 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 141275 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 296748 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 969767 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 975438 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 1945205 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 276886 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 279848 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 556734 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 36325 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 7975 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 969767 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 432359 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 36505 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 8351 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 975438 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 421123 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2887843 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 36325 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 7975 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 969767 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 432359 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 36505 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 8351 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 975438 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 421123 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2887843 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001927 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000125 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.001972 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.001604 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.963327 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.970769 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.966749 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.296296 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.147059 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.213115 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.460440 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.488289 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.473698 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.010516 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.010957 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.010737 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.024739 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.029830 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.027298 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001927 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000125 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.010516 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.181414 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.001972 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.010957 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.183630 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.061221 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001927 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000125 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.010516 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.181414 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.001972 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.010957 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.183630 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.061221 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 86321.428571 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 68500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 83500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 84776.223776 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 312.712441 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 316.957211 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 314.672521 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 23875 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 12400 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 19461.538462 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 83402.215517 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83016.156154 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 83212.760281 # average ReadExReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 81791.429692 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 82868.918413 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 82342.813368 # average ReadCleanReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 86369.343066 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 88247.184954 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 87400.809317 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 86321.428571 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 68500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 81791.429692 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 83661.341731 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 83500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 82868.918413 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 83580.853733 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 83471.271974 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 86321.428571 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 68500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 81791.429692 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 83661.341731 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 83500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 82868.918413 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 83580.853733 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 83471.271974 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2262,240 +2296,251 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 95497 # number of writebacks -system.l2c.writebacks::total 95497 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 4 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.data 75 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 6 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.data 61 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 146 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 75 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 6 # number of demand (read+write) MSHR hits +system.l2c.writebacks::writebacks 95583 # number of writebacks +system.l2c.writebacks::total 95583 # number of writebacks +system.l2c.ReadCleanReq_mshr_hits::cpu0.inst 6 # number of ReadCleanReq MSHR hits +system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 7 # number of ReadCleanReq MSHR hits +system.l2c.ReadCleanReq_mshr_hits::total 13 # number of ReadCleanReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu0.data 76 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.data 61 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 137 # number of ReadSharedReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 6 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 76 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu1.data 61 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 146 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 75 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 6 # number of overall MSHR hits +system.l2c.demand_mshr_hits::total 150 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 6 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 76 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.data 61 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 146 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 68 # number of ReadReq MSHR misses +system.l2c.overall_mshr_hits::total 150 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 70 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 10139 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 6988 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 63 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 10744 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 8073 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 36076 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 1453 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1281 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 2734 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 7 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 2 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 9 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 72022 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 68619 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 140641 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 68 # number of demand (read+write) MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 72 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 143 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 1471 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1262 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2733 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 8 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 5 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 13 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 71586 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 68983 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 140569 # number of ReadExReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 10192 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 10681 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::total 20873 # number of ReadCleanReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 6774 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 8287 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 15061 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 70 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 10139 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 79010 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 63 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 10744 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 76692 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 176717 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 68 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 10192 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 78360 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 72 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 10681 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 77270 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 176646 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 70 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 10139 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 79010 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 63 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 10744 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 76692 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 176717 # number of overall MSHR misses -system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 666 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 16558 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 14569 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 31793 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 16166 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 11418 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_misses::cpu0.inst 10192 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 78360 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 72 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 10681 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 77270 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 176646 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 670 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 16542 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 14585 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 31797 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 16149 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 11435 # number of WriteReq MSHR uncacheable system.l2c.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 666 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 32724 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 25987 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 59377 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 5068250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 56250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 708062999 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 518326750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4705500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 759670250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 614985750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 2610875749 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 25946451 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 22749281 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 48695732 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 173506 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 86501 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 260007 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5129956460 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4854039180 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 9983995640 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 5068250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 56250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 708062999 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 5648283210 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 4705500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 759670250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 5469024930 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 12594871389 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 5068250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 56250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 708062999 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 5648283210 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 4705500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 759670250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 5469024930 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 12594871389 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 41164749 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2875017500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2529305000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 5445487249 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2162093500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1988256000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 4150349500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 41164749 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5037111000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 4517561000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 9595836749 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.001866 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000121 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.010457 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.025382 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.001730 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011018 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.028595 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.013921 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.968021 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.970455 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.969160 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.333333 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.058824 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.163636 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.465033 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.483478 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.473853 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001866 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000121 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.010457 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.183665 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.001730 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011018 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.180769 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.061186 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001866 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000121 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.010457 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.183665 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.001730 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011018 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.180769 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.061186 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 74533.088235 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 56250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 69835.585265 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 74173.833715 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 74690.476190 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70706.464073 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76178.093645 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 72371.541995 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17857.158293 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17759.001561 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17811.167520 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24786.571429 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 43250.500000 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 28889.666667 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 71227.631279 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 70738.996196 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 70989.225333 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 74533.088235 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 56250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69835.585265 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 71488.206683 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74690.476190 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70706.464073 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71311.543968 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 71271.419213 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 74533.088235 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 56250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69835.585265 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 71488.206683 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74690.476190 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70706.464073 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71311.543968 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 71271.419213 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 61808.932432 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 173633.138060 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173608.689684 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 171279.440411 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 133743.257454 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 174133.473463 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 150462.206352 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 61808.932432 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 153927.117712 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 173839.265787 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 161608.648955 # average overall mshr uncacheable latency +system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 670 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 32691 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 26020 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 59381 # number of overall MSHR uncacheable misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 5342500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 58500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 5292000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 10693000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 30584000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 26180500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 56764500 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 264500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 105000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 369500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5254571000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 5036873500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 10291444500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 731590500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 778604000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 1510194500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 518333500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 649828500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 1168162000 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 5342500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 58500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 731590500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 5772904500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 5292000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 778604000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 5686702000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 12980494000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 5342500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 58500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 731590500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 5772904500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 5292000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 778604000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 5686702000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 12980494000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 42529000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2936807000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2590020500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 5569356500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2216276000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2037082000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 4253358000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 42529000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5153083000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 4627102500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 9822714500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.001927 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000125 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.001972 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.001604 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.963327 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.970769 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.966749 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.296296 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.147059 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.213115 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.460440 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.488289 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.473698 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.010510 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.010950 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.010730 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.024465 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.029613 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.027052 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001927 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000125 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.010510 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.181238 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.001972 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010950 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.183486 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.061169 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001927 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000125 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.010510 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.181238 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.001972 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010950 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.183486 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.061169 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 76321.428571 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 58500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 73500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 74776.223776 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20791.298436 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20745.245642 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20770.032931 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 33062.500000 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 21000 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 28423.076923 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 73402.215517 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73016.156154 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 73212.760281 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 71780.857535 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72896.170771 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 72351.578594 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 76518.083850 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 78415.409678 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 77562.047673 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76321.428571 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 58500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71780.857535 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 73671.573507 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 73500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72896.170771 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73595.211596 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 73483.090475 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76321.428571 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 58500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71780.857535 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 73671.573507 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 73500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72896.170771 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73595.211596 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 73483.090475 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63476.119403 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177536.392214 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 177581.110730 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 175153.520772 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 137239.209858 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178144.468736 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 154196.563225 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63476.119403 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 157630.020495 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 177828.689470 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 165418.475607 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 68118 # Transaction distribution -system.membus.trans_dist::ReadResp 68117 # Transaction distribution +system.membus.trans_dist::ReadReq 31797 # Transaction distribution +system.membus.trans_dist::ReadResp 68122 # Transaction distribution system.membus.trans_dist::WriteReq 27584 # Transaction distribution system.membus.trans_dist::WriteResp 27584 # Transaction distribution -system.membus.trans_dist::Writeback 131657 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 36194 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 36194 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4626 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 9 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4635 # Transaction distribution -system.membus.trans_dist::ReadExReq 138750 # Transaction distribution -system.membus.trans_dist::ReadExResp 138750 # Transaction distribution +system.membus.trans_dist::Writeback 131744 # Transaction distribution +system.membus.trans_dist::CleanEvict 9021 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4618 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 13 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4631 # Transaction distribution +system.membus.trans_dist::ReadExReq 138685 # Transaction distribution +system.membus.trans_dist::ReadExResp 138685 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 36326 # Transaction distribution +system.membus.trans_dist::InvalidateReq 36195 # Transaction distribution +system.membus.trans_dist::InvalidateResp 36195 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 20 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 22 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 465313 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 572881 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108814 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108814 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 681695 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 474277 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 581847 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108830 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108830 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 690677 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 640 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 704 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17344028 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 17507933 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4631616 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 4631616 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22139549 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17345628 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 17509597 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2315264 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2315264 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19824861 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 523 # Total snoops (count) -system.membus.snoop_fanout::samples 406994 # Request fanout histogram +system.membus.snoop_fanout::samples 416234 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 406994 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 416234 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 406994 # Request fanout histogram -system.membus.reqLayer0.occupancy 95655500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 416234 # Request fanout histogram +system.membus.reqLayer0.occupancy 95824000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 16812 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 17812 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1658000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1684000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1067096296 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 923050293 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1022750121 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1019598366 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 37540981 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64439557 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2528,50 +2573,53 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 2657014 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2656928 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 154492 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2656868 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 704443 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36230 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2822 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 55 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2876 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 296803 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296803 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3891000 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2536661 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 42360 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 169075 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 6639096 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 124504512 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 99962077 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 64700 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 291504 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 224822793 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 70210 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3724954 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.042649 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.202064 # Request fanout histogram +system.toL2Bus.trans_dist::Writeback 835335 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2054815 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2828 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 61 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2888 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 296748 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296748 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1945479 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 556983 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 36195 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5795514 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2675972 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 42691 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 169160 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8683337 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 124535936 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 99845469 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 65304 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 291320 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 224738029 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 211435 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 5959204 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.050368 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.218703 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 3566090 95.74% 95.74% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 158864 4.26% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 5659051 94.96% 94.96% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 300153 5.04% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3724954 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2562504434 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 5959204 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3608244499 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 246000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2923288858 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2920237464 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1353663761 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1326853963 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 26203715 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 26388950 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 96601513 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 96751648 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 3039 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt index 99e4aebe7..d3ad4a453 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt @@ -1,166 +1,166 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.477179 # Number of seconds simulated -sim_ticks 47477179149500 # Number of ticks simulated -final_tick 47477179149500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.482330 # Number of seconds simulated +sim_ticks 47482329862000 # Number of ticks simulated +final_tick 47482329862000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 181000 # Simulator instruction rate (inst/s) -host_op_rate 212908 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9614368962 # Simulator tick rate (ticks/s) -host_mem_usage 772236 # Number of bytes of host memory used -host_seconds 4938.15 # Real time elapsed on the host -sim_insts 893806699 # Number of instructions simulated -sim_ops 1051369194 # Number of ops (including micro ops) simulated +host_inst_rate 176341 # Simulator instruction rate (inst/s) +host_op_rate 207374 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9393535208 # Simulator tick rate (ticks/s) +host_mem_usage 769764 # Number of bytes of host memory used +host_seconds 5054.79 # Real time elapsed on the host +sim_insts 891365561 # Number of instructions simulated +sim_ops 1048233259 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 125376 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 108736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 7965248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 14333320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 15086080 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 149568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 136256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3627008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 11510096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 14847104 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 436288 # Number of bytes read from this memory -system.physmem.bytes_read::total 68325080 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 7965248 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3627008 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 11592256 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 80335616 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 124416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 101184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 8041216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 40378184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 15310528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 143616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 132928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3236032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 17140560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 13345792 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 446144 # Number of bytes read from this memory +system.physmem.bytes_read::total 98400600 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 8041216 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3236032 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 11277248 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 78262528 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 80356200 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1959 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1699 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 124457 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 223971 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 235720 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2337 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2129 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 56672 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 179858 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 231986 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6817 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1067605 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1255244 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 78283112 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1944 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1581 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 125644 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 630922 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 239227 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2244 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2077 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 50563 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 267834 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 208528 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6971 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1537535 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1222852 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1257818 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2641 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2290 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 167770 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 301899 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 317754 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 3150 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2870 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 76395 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 242434 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 312721 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9189 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1439114 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 167770 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 76395 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 244165 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1692089 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1225426 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2620 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2131 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 169352 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 850383 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 322447 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 3025 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2800 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 68152 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 360988 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 281069 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9396 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2072363 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 169352 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 68152 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 237504 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1648245 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1692523 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1692089 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2641 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2290 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 167770 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 302333 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 317754 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 3150 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2870 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 76395 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 242434 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 312721 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9189 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3131637 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1067605 # Number of read requests accepted -system.physmem.writeReqs 1929186 # Number of write requests accepted -system.physmem.readBursts 1067605 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1929186 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 68309056 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 17664 # Total number of bytes read from write queue -system.physmem.bytesWritten 120257344 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 68325080 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 123323752 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 276 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 50133 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 117648 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 62386 # Per bank write bursts -system.physmem.perBankRdBursts::1 65796 # Per bank write bursts -system.physmem.perBankRdBursts::2 60427 # Per bank write bursts -system.physmem.perBankRdBursts::3 63507 # Per bank write bursts -system.physmem.perBankRdBursts::4 66319 # Per bank write bursts -system.physmem.perBankRdBursts::5 73621 # Per bank write bursts -system.physmem.perBankRdBursts::6 69221 # Per bank write bursts -system.physmem.perBankRdBursts::7 63591 # Per bank write bursts -system.physmem.perBankRdBursts::8 61143 # Per bank write bursts -system.physmem.perBankRdBursts::9 115825 # Per bank write bursts -system.physmem.perBankRdBursts::10 59973 # Per bank write bursts -system.physmem.perBankRdBursts::11 66407 # Per bank write bursts -system.physmem.perBankRdBursts::12 58867 # Per bank write bursts -system.physmem.perBankRdBursts::13 61123 # Per bank write bursts -system.physmem.perBankRdBursts::14 58743 # Per bank write bursts -system.physmem.perBankRdBursts::15 60380 # Per bank write bursts -system.physmem.perBankWrBursts::0 115877 # Per bank write bursts -system.physmem.perBankWrBursts::1 122877 # Per bank write bursts -system.physmem.perBankWrBursts::2 115996 # Per bank write bursts -system.physmem.perBankWrBursts::3 119851 # Per bank write bursts -system.physmem.perBankWrBursts::4 119313 # Per bank write bursts -system.physmem.perBankWrBursts::5 126432 # Per bank write bursts -system.physmem.perBankWrBursts::6 119028 # Per bank write bursts -system.physmem.perBankWrBursts::7 120185 # Per bank write bursts -system.physmem.perBankWrBursts::8 118113 # Per bank write bursts -system.physmem.perBankWrBursts::9 119452 # Per bank write bursts -system.physmem.perBankWrBursts::10 113141 # Per bank write bursts -system.physmem.perBankWrBursts::11 117109 # Per bank write bursts -system.physmem.perBankWrBursts::12 112676 # Per bank write bursts -system.physmem.perBankWrBursts::13 113553 # Per bank write bursts -system.physmem.perBankWrBursts::14 112771 # Per bank write bursts -system.physmem.perBankWrBursts::15 112647 # Per bank write bursts +system.physmem.bw_write::total 1648679 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1648245 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2620 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2131 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 169352 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 850817 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 322447 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 3025 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2800 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 68152 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 360988 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 281069 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9396 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3721041 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1537535 # Number of read requests accepted +system.physmem.writeReqs 1225426 # Number of write requests accepted +system.physmem.readBursts 1537535 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1225426 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 98362112 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 40128 # Total number of bytes read from write queue +system.physmem.bytesWritten 78282112 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 98400600 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 78283112 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 627 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2247 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 220170 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 94941 # Per bank write bursts +system.physmem.perBankRdBursts::1 98803 # Per bank write bursts +system.physmem.perBankRdBursts::2 90365 # Per bank write bursts +system.physmem.perBankRdBursts::3 103122 # Per bank write bursts +system.physmem.perBankRdBursts::4 90513 # Per bank write bursts +system.physmem.perBankRdBursts::5 102407 # Per bank write bursts +system.physmem.perBankRdBursts::6 86370 # Per bank write bursts +system.physmem.perBankRdBursts::7 97727 # Per bank write bursts +system.physmem.perBankRdBursts::8 90531 # Per bank write bursts +system.physmem.perBankRdBursts::9 141203 # Per bank write bursts +system.physmem.perBankRdBursts::10 86748 # Per bank write bursts +system.physmem.perBankRdBursts::11 95428 # Per bank write bursts +system.physmem.perBankRdBursts::12 92596 # Per bank write bursts +system.physmem.perBankRdBursts::13 93840 # Per bank write bursts +system.physmem.perBankRdBursts::14 85305 # Per bank write bursts +system.physmem.perBankRdBursts::15 87009 # Per bank write bursts +system.physmem.perBankWrBursts::0 77173 # Per bank write bursts +system.physmem.perBankWrBursts::1 80360 # Per bank write bursts +system.physmem.perBankWrBursts::2 74652 # Per bank write bursts +system.physmem.perBankWrBursts::3 83758 # Per bank write bursts +system.physmem.perBankWrBursts::4 75004 # Per bank write bursts +system.physmem.perBankWrBursts::5 81344 # Per bank write bursts +system.physmem.perBankWrBursts::6 71841 # Per bank write bursts +system.physmem.perBankWrBursts::7 79366 # Per bank write bursts +system.physmem.perBankWrBursts::8 74851 # Per bank write bursts +system.physmem.perBankWrBursts::9 75375 # Per bank write bursts +system.physmem.perBankWrBursts::10 73319 # Per bank write bursts +system.physmem.perBankWrBursts::11 78054 # Per bank write bursts +system.physmem.perBankWrBursts::12 76445 # Per bank write bursts +system.physmem.perBankWrBursts::13 77751 # Per bank write bursts +system.physmem.perBankWrBursts::14 70793 # Per bank write bursts +system.physmem.perBankWrBursts::15 73072 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 226 # Number of times write queue was full causing retry -system.physmem.totGap 47477177227000 # Total gap between requests +system.physmem.numWrRetry 43 # Number of times write queue was full causing retry +system.physmem.totGap 47482327991500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1067575 # Read request sizes (log2) +system.physmem.readPktSize::6 1537505 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1926612 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 704225 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 128672 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 50762 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 38076 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 32557 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 29624 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 27261 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 24554 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 21025 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 5650 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1457 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 974 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 763 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 566 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 319 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 265 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 210 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 190 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 70 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1222852 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 944383 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 373776 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 49487 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 34651 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 29546 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 27146 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 25089 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 22356 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 19759 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4466 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1975 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1145 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 863 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 650 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 440 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 379 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 337 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 283 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 110 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 61 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -188,153 +188,164 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 45205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 65288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 93465 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 105702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 113971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 112162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 108444 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 104050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 100974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 97727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 97663 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 116214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 104741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 100206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 114790 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 102548 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 96204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 91928 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 7498 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 6040 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 6647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 7551 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 7971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 7109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 6845 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 7426 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 5746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 5672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 5351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 5487 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 4631 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 3871 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 3873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 3174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 2570 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1389 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 919 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1025 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 778 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 627 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 635 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 556 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 443 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 391 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 256 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 704 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1080190 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 174.567156 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 106.861850 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 244.135229 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 694007 64.25% 64.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 206792 19.14% 83.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 51978 4.81% 88.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 24974 2.31% 90.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 18580 1.72% 92.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11712 1.08% 93.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8387 0.78% 94.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 7821 0.72% 94.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 55939 5.18% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1080190 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 83578 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 12.770071 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 136.461901 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 83575 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 83578 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 83578 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.482244 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.955849 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 20.755182 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-31 75860 90.77% 90.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-63 5202 6.22% 96.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-95 1276 1.53% 98.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-127 755 0.90% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-159 241 0.29% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-191 100 0.12% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-223 48 0.06% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-255 8 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-287 9 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-319 10 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-351 17 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-383 25 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-415 5 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::416-447 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::448-479 5 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-511 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-543 5 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-575 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::640-671 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::672-703 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::992-1023 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1056-1087 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 83578 # Writes before turning the bus around for reads -system.physmem.totQLat 40962619238 # Total ticks spent queuing -system.physmem.totMemAccLat 60975037988 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5336645000 # Total ticks spent in databus transfers -system.physmem.avgQLat 38378.62 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 17449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 20135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 44686 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 57274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 64486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 68059 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 69963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 74225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 75616 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 79113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 78742 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 81088 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 80039 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 81169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 88387 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 80912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 76308 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 72380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1076 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 779 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 575 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 472 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 442 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 426 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 393 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 419 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 384 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 378 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 122 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 940608 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 187.797442 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 115.260175 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 246.189901 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 561167 59.66% 59.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 186793 19.86% 79.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 62478 6.64% 86.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 31194 3.32% 89.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 21090 2.24% 91.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 13303 1.41% 93.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 10059 1.07% 94.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 10062 1.07% 95.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 44462 4.73% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 940608 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 69828 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.009810 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 322.555489 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 69825 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::24576-28671 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::77824-81919 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 69828 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 69828 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.516727 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.040521 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 6.611414 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 66194 94.80% 94.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 1213 1.74% 96.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 484 0.69% 97.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 227 0.33% 97.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 283 0.41% 97.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 499 0.71% 98.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 107 0.15% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 41 0.06% 98.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 40 0.06% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 28 0.04% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 48 0.07% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 19 0.03% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 437 0.63% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 36 0.05% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 59 0.08% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 38 0.05% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 18 0.03% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 2 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 4 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 30 0.04% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 4 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 69828 # Writes before turning the bus around for reads +system.physmem.totQLat 47438420321 # Total ticks spent queuing +system.physmem.totMemAccLat 76255445321 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 7684540000 # Total ticks spent in databus transfers +system.physmem.avgQLat 30866.14 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 57128.62 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.44 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.53 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.44 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.60 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 49616.14 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.07 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.65 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.07 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.65 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage -system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.20 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.74 # Average write queue length when enqueuing -system.physmem.readRowHits 799066 # Number of row buffer hits during reads -system.physmem.writeRowHits 1067089 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.87 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 56.79 # Row buffer hit rate for writes -system.physmem.avgGap 15842672.12 # Average gap between requests -system.physmem.pageHitRate 63.34 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4225820760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2305755375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4093954800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 6217942320 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3100978164960 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1196990920755 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27436312080750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31751124639720 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.766110 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45642284556030 # Time in different power states -system.physmem_0.memoryStateTime::REF 1585367160000 # Time in different power states +system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.49 # Average write queue length when enqueuing +system.physmem.readRowHits 1237162 # Number of row buffer hits during reads +system.physmem.writeRowHits 582295 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.50 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 47.61 # Row buffer hit rate for writes +system.physmem.avgGap 17185305.18 # Average gap between requests +system.physmem.pageHitRate 65.92 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3664415160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1999432875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 5961079800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4040267040 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3101314831680 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1200459376170 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27436362274500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31753801677225 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.749891 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45642197013620 # Time in different power states +system.physmem_0.memoryStateTime::REF 1585539280000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 249523460470 # Time in different power states +system.physmem_0.memoryStateTime::ACT 254592941380 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3940415640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2150028375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4231125600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5958113760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3100978164960 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1192295919105 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27440430503250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31749984270690 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.742090 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45649112064952 # Time in different power states -system.physmem_1.memoryStateTime::REF 1585367160000 # Time in different power states +system.physmem_1.actEnergy 3446581320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1880575125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 6026748000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3885796800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3101314831680 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1189099091205 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27446327436750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31751981060880 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.711548 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45658799171891 # Time in different power states +system.physmem_1.memoryStateTime::REF 1585539280000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 242698243548 # Time in different power states +system.physmem_1.memoryStateTime::ACT 237989586859 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -368,15 +379,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 146228375 # Number of BP lookups -system.cpu0.branchPred.condPredicted 102974776 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 6711039 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 109409110 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 78811291 # Number of BTB hits +system.cpu0.branchPred.lookups 132987745 # Number of BP lookups +system.cpu0.branchPred.condPredicted 94268605 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 6098049 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 100013530 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 72636793 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 72.033573 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 17518133 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 1190785 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 72.626967 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 15695407 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 1093856 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -407,62 +418,66 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 302414 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 302414 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9161 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 80364 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 302414 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 302414 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 302414 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 89525 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 18873.046300 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 17079.714221 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 14739.219535 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 88579 98.94% 98.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 783 0.87% 99.82% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 49 0.05% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 43 0.05% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 44 0.05% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 15 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 7 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 89525 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 788586204 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 788586204 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 788586204 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 80364 89.77% 89.77% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 9161 10.23% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 89525 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 302414 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 275636 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 275636 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8285 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 76005 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 275636 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 275636 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 275636 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 84290 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 20584.826195 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 18820.617576 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 14196.942212 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-32767 79742 94.60% 94.60% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-65535 3631 4.31% 98.91% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-98303 417 0.49% 99.41% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-131071 355 0.42% 99.83% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-163839 30 0.04% 99.86% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::163840-196607 13 0.02% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-229375 32 0.04% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::229376-262143 8 0.01% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-294911 18 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::294912-327679 24 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-360447 12 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::360448-393215 5 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 84290 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 669754704 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 669754704 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 669754704 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 76005 90.17% 90.17% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 8285 9.83% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 84290 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 275636 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 302414 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 89525 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 275636 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 84290 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 89525 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 391939 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 84290 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 359926 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 94852147 # DTB read hits -system.cpu0.dtb.read_misses 252189 # DTB read misses -system.cpu0.dtb.write_hits 83443537 # DTB write hits -system.cpu0.dtb.write_misses 50225 # DTB write misses +system.cpu0.dtb.read_hits 84907220 # DTB read hits +system.cpu0.dtb.read_misses 227423 # DTB read misses +system.cpu0.dtb.write_hits 75575788 # DTB write hits +system.cpu0.dtb.write_misses 48213 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 43363 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1048 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 36113 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 2068 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 9574 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 41950 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1046 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 35105 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1851 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 8962 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 10663 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 95104336 # DTB read accesses -system.cpu0.dtb.write_accesses 83493762 # DTB write accesses +system.cpu0.dtb.perms_faults 10953 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 85134643 # DTB read accesses +system.cpu0.dtb.write_accesses 75624001 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 178295684 # DTB hits -system.cpu0.dtb.misses 302414 # DTB misses -system.cpu0.dtb.accesses 178598098 # DTB accesses +system.cpu0.dtb.hits 160483008 # DTB hits +system.cpu0.dtb.misses 275636 # DTB misses +system.cpu0.dtb.accesses 160758644 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -492,187 +507,193 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 66598 # Table walker walks requested -system.cpu0.itb.walker.walksLong 66598 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 516 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 54284 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 66598 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 66598 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 66598 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 54800 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 21262.637080 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 19017.155066 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 16721.874177 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 53728 98.04% 98.04% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 946 1.73% 99.77% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 48 0.09% 99.86% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 54 0.10% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 12 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 9 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 54800 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 787865704 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 787865704 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 787865704 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 54284 99.06% 99.06% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 516 0.94% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 54800 # Table walker page sizes translated +system.cpu0.itb.walker.walks 64906 # Table walker walks requested +system.cpu0.itb.walker.walksLong 64906 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 453 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 52493 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 64906 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 64906 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 64906 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 52946 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 23323.187776 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 21129.664435 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 16367.746814 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 48035 90.72% 90.72% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 3919 7.40% 98.13% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-98303 305 0.58% 98.70% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-131071 573 1.08% 99.78% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 22 0.04% 99.83% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-196607 23 0.04% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-229375 32 0.06% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::229376-262143 10 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 11 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::294912-327679 7 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-360447 3 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::360448-393215 3 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 52946 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 669040204 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 669040204 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 669040204 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 52493 99.14% 99.14% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 453 0.86% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 52946 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 66598 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 66598 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 64906 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 64906 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 54800 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 54800 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 121398 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 261387859 # ITB inst hits -system.cpu0.itb.inst_misses 66598 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 52946 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 52946 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 117852 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 238223958 # ITB inst hits +system.cpu0.itb.inst_misses 64906 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 43363 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1048 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 25865 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 41950 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1046 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 24846 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 223375 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 205008 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 261454457 # ITB inst accesses -system.cpu0.itb.hits 261387859 # DTB hits -system.cpu0.itb.misses 66598 # DTB misses -system.cpu0.itb.accesses 261454457 # DTB accesses -system.cpu0.numCycles 1029830596 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 238288864 # ITB inst accesses +system.cpu0.itb.hits 238223958 # DTB hits +system.cpu0.itb.misses 64906 # DTB misses +system.cpu0.itb.accesses 238288864 # DTB accesses +system.cpu0.numCycles 971262699 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 487755400 # Number of instructions committed -system.cpu0.committedOps 573075495 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 47715438 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 4391 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 93925247519 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.111367 # CPI: cycles per instruction -system.cpu0.ipc 0.473627 # IPC: instructions per cycle +system.cpu0.committedInsts 437915417 # Number of instructions committed +system.cpu0.committedOps 515248827 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 45685554 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 4508 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 93994129820 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.217923 # CPI: cycles per instruction +system.cpu0.ipc 0.450872 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 13314 # number of quiesce instructions executed -system.cpu0.tickCycles 777849504 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 251981092 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 5902107 # number of replacements -system.cpu0.dcache.tags.tagsinuse 475.000126 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 169363182 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5902609 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 28.692936 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 5093256500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.000126 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.927735 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.927735 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 502 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 153 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.980469 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 359562725 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 359562725 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 86974547 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 86974547 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 77401946 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 77401946 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 298185 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 298185 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 275916 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 275916 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1961524 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1961524 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1923644 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1923644 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 164376493 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 164376493 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 164674678 # number of overall hits -system.cpu0.dcache.overall_hits::total 164674678 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3650210 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3650210 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 2435892 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2435892 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 670224 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 670224 # number of SoftPFReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 817849 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 817849 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 165967 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 165967 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 202383 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 202383 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 6086102 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 6086102 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 6756326 # number of overall misses -system.cpu0.dcache.overall_misses::total 6756326 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 55969500387 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 55969500387 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 47032436273 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 47032436273 # number of WriteReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 33507618312 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 33507618312 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2441854002 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2441854002 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4283229947 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4283229947 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1855000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1855000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 103001936660 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 103001936660 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 103001936660 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 103001936660 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 90624757 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 90624757 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 79837838 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 79837838 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 968409 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 968409 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1093765 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 1093765 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2127491 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2127491 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2126027 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2126027 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 170462595 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 170462595 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 171431004 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 171431004 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.040278 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.040278 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.030510 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.030510 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.692088 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.692088 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.747737 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.747737 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.078011 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.078011 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.095193 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.095193 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.035703 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.035703 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.039411 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.039411 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15333.227509 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15333.227509 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19308.095873 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 19308.095873 # average WriteReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 40970.421572 # average WriteInvalidateReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 40970.421572 # average WriteInvalidateReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14712.888719 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14712.888719 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21163.980903 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21163.980903 # average StoreCondReq miss latency +system.cpu0.kern.inst.quiesce 13434 # number of quiesce instructions executed +system.cpu0.tickCycles 710739035 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 260523664 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 5570429 # number of replacements +system.cpu0.dcache.tags.tagsinuse 501.849943 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 152007137 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5570934 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.285754 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 4974167000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 501.849943 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.980176 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.980176 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 505 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 13 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 361 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 131 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.986328 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 323765599 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 323765599 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 77611950 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 77611950 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 69963904 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 69963904 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 263445 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 263445 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 169638 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 169638 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1758419 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1758419 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1721710 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1721710 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 147575854 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 147575854 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 147839299 # number of overall hits +system.cpu0.dcache.overall_hits::total 147839299 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3380647 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3380647 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 2384184 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2384184 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 670394 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 670394 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 781336 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 781336 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 154783 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 154783 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 189820 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 189820 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 5764831 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 5764831 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 6435225 # number of overall misses +system.cpu0.dcache.overall_misses::total 6435225 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 51653726500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 51653726500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 46144722000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 46144722000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 52344211500 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 52344211500 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2307846500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2307846500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3989603000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 3989603000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3214000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3214000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 97798448500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 97798448500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 97798448500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 97798448500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 80992597 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 80992597 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 72348088 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 72348088 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 933839 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 933839 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 950974 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 950974 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1913202 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 1913202 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1911530 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 1911530 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 153340685 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 153340685 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 154274524 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 154274524 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.041740 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.041740 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.032954 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.032954 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.717890 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.717890 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.821617 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.821617 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.080903 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.080903 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.099303 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.099303 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.037595 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.037595 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.041713 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.041713 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15279.242849 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15279.242849 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19354.513746 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 19354.513746 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 66993.216107 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 66993.216107 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14910.206547 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14910.206547 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21017.822147 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21017.822147 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16924.122642 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 16924.122642 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15245.258541 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 15245.258541 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16964.668782 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 16964.668782 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15197.362718 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 15197.362718 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -681,161 +702,161 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 3966592 # number of writebacks -system.cpu0.dcache.writebacks::total 3966592 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 443574 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 443574 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1010368 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1010368 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 102 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 102 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 43626 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 43626 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 27 # number of StoreCondReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::total 27 # number of StoreCondReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1453942 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1453942 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1453942 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1453942 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3206636 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3206636 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1425524 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1425524 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 664815 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 664815 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 817747 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 817747 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 122341 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 122341 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 202356 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 202356 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 4632160 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 4632160 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5296975 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5296975 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31604 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31604 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 30977 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 30977 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 62581 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 62581 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 42580313466 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 42580313466 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 25667045166 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 25667045166 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14837829930 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14837829930 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 32271814438 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 32271814438 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1568491891 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1568491891 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3969414040 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3969414040 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1696000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1696000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 68247358632 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 68247358632 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 83085188562 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 83085188562 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5612600750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5612600750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5285393252 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5285393252 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10897994002 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10897994002 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035384 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035384 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017855 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017855 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.686502 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.686502 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.747644 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.747644 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.057505 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.057505 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.095180 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.095180 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027174 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.027174 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030899 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.030899 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13278.811024 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13278.811024 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18005.340609 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18005.340609 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22318.735182 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22318.735182 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 39464.301842 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 39464.301842 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12820.656125 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12820.656125 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19615.993793 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19615.993793 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 3773399 # number of writebacks +system.cpu0.dcache.writebacks::total 3773399 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 430069 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 430069 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 999795 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 999795 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 103 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 103 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 40774 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 40774 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 43 # number of StoreCondReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::total 43 # number of StoreCondReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1429864 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1429864 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1429864 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1429864 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2950578 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 2950578 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1384389 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1384389 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 664773 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 664773 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 781233 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 781233 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 114009 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 114009 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 189777 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 189777 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4334967 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4334967 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 4999740 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 4999740 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32882 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32882 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 32815 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 32815 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 65697 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 65697 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 40501320500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 40501320500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 25594559000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 25594559000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 15267286500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 15267286500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 51557242500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 51557242500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1530630500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1530630500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3798446000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3798446000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2841500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2841500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 66095879500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 66095879500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 81363166000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 81363166000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5911844500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5911844500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5682739500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5682739500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11594584000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11594584000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036430 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036430 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019135 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019135 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.711871 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.711871 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.821508 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.821508 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059591 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059591 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.099280 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.099280 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028270 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028270 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032408 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032408 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13726.571709 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13726.571709 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18487.982063 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18487.982063 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22966.165142 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22966.165142 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 65994.706445 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 65994.706445 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13425.523424 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13425.523424 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20015.312709 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20015.312709 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14733.376790 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14733.376790 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15685.403190 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15685.403190 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177591.467852 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 177591.467852 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170623.147884 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 170623.147884 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 174142.215720 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 174142.215720 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15247.147095 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15247.147095 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16273.479421 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16273.479421 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 179789.687367 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 179789.687367 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 173175.057139 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173175.057139 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 176485.745163 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 176485.745163 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 10289736 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.930282 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 250868144 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 10290248 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 24.379213 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 24018555250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.930282 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999864 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999864 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 9510825 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.926606 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 228501569 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 9511337 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 24.024127 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 29799763000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.926606 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999857 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999857 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 266 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 233 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 431 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 532607059 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 532607059 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 250868144 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 250868144 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 250868144 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 250868144 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 250868144 # number of overall hits -system.cpu0.icache.overall_hits::total 250868144 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 10290257 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 10290257 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 10290257 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 10290257 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 10290257 # number of overall misses -system.cpu0.icache.overall_misses::total 10290257 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 101454150461 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 101454150461 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 101454150461 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 101454150461 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 101454150461 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 101454150461 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 261158401 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 261158401 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 261158401 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 261158401 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 261158401 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 261158401 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.039402 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.039402 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.039402 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.039402 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.039402 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.039402 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9859.243599 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9859.243599 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9859.243599 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9859.243599 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9859.243599 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9859.243599 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 485537176 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 485537176 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 228501569 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 228501569 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 228501569 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 228501569 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 228501569 # number of overall hits +system.cpu0.icache.overall_hits::total 228501569 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 9511346 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 9511346 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 9511346 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 9511346 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 9511346 # number of overall misses +system.cpu0.icache.overall_misses::total 9511346 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 94734195000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 94734195000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 94734195000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 94734195000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 94734195000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 94734195000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 238012915 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 238012915 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 238012915 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 238012915 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 238012915 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 238012915 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.039961 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.039961 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.039961 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.039961 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.039961 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.039961 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9960.124992 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9960.124992 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9960.124992 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9960.124992 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9960.124992 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9960.124992 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -844,462 +865,490 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 10290257 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 10290257 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 10290257 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 10290257 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 10290257 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 10290257 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52307 # number of ReadReq MSHR uncacheable -system.cpu0.icache.ReadReq_mshr_uncacheable::total 52307 # number of ReadReq MSHR uncacheable -system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52307 # number of overall MSHR uncacheable misses -system.cpu0.icache.overall_mshr_uncacheable_misses::total 52307 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 91134485035 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 91134485035 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 91134485035 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 91134485035 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 91134485035 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 91134485035 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4833897250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4833897250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4833897250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 4833897250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.039402 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.039402 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.039402 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.039402 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.039402 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.039402 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8856.385709 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8856.385709 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8856.385709 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 8856.385709 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8856.385709 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 8856.385709 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92413.964670 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92413.964670 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92413.964670 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92413.964670 # average overall mshr uncacheable latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9511346 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 9511346 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 9511346 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 9511346 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 9511346 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 9511346 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52292 # number of ReadReq MSHR uncacheable +system.cpu0.icache.ReadReq_mshr_uncacheable::total 52292 # number of ReadReq MSHR uncacheable +system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52292 # number of overall MSHR uncacheable misses +system.cpu0.icache.overall_mshr_uncacheable_misses::total 52292 # number of overall MSHR uncacheable misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 89978522000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 89978522000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 89978522000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 89978522000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 89978522000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 89978522000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4777780500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4777780500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4777780500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 4777780500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.039961 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.039961 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.039961 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.039961 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.039961 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.039961 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9460.124992 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9460.124992 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9460.124992 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 9460.124992 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9460.124992 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9460.124992 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 91367.331523 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 91367.331523 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 91367.331523 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 91367.331523 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 8031555 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 8035489 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 3395 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 7512189 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 7515615 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 2942 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 1023103 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 2858654 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16072.506631 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 16359356 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2874620 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 5.690963 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 5820437500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 7531.283903 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 82.699151 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 79.479413 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4176.151665 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3206.986567 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 995.905932 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.459673 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.005048 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004851 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.254892 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.195739 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.060785 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.980988 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1379 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 78 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14509 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 349 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 790 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 240 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 24 # Occupied blocks per task id +system.cpu0.l2cache.prefetcher.pfSpanPage 975521 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 2798117 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16231.650842 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 26314432 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2814109 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 9.350893 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 27335773000 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 6405.405319 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 66.558250 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 59.359829 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5460.175756 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3311.396146 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 928.755541 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.390955 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004062 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003623 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.333263 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.202112 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.056687 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.990701 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1465 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 86 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14441 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 296 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 685 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 484 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 6 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 25 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 40 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 671 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4595 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6778 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2297 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.084167 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004761 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.885559 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 347615506 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 347615506 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 522089 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 157285 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 9486915 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 2945564 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 13111853 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 3966591 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 3966591 # number of Writeback hits -system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 220070 # number of WriteInvalidateReq hits -system.cpu0.l2cache.WriteInvalidateReq_hits::total 220070 # number of WriteInvalidateReq hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 104135 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 104135 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 36121 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 36121 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 927424 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 927424 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 522089 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 157285 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 9486915 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 3872988 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 14039277 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 522089 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 157285 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 9486915 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 3872988 # number of overall hits -system.cpu0.l2cache.overall_hits::total 14039277 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 12017 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8240 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 803341 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 1047943 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 1871541 # number of ReadReq misses -system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 596217 # number of WriteInvalidateReq misses -system.cpu0.l2cache.WriteInvalidateReq_misses::total 596217 # number of WriteInvalidateReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 136954 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 136954 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 166233 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 166233 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 268888 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 268888 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 12017 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8240 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 803341 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 1316831 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 2140429 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 12017 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8240 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 803341 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 1316831 # number of overall misses -system.cpu0.l2cache.overall_misses::total 2140429 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 431373212 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 321871478 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 24275854446 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 35706676401 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 60735775537 # number of ReadReq miss cycles -system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data 217330162 # number of WriteInvalidateReq miss cycles -system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total 217330162 # number of WriteInvalidateReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2999502703 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 2999502703 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3447611393 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3447611393 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1659499 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1659499 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 13657276886 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 13657276886 # number of ReadExReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 431373212 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 321871478 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 24275854446 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 49363953287 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 74393052423 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 431373212 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 321871478 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 24275854446 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 49363953287 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 74393052423 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 534106 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 165525 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 10290256 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 3993507 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 14983394 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 3966591 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 3966591 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 816287 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.l2cache.WriteInvalidateReq_accesses::total 816287 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 241089 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 241089 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 202354 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 202354 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1196312 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 1196312 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 534106 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 165525 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 10290256 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 5189819 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 16179706 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 534106 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 165525 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 10290256 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 5189819 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 16179706 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.022499 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.049781 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.078068 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.262412 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.124908 # miss rate for ReadReq accesses -system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.730401 # miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.730401 # miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.568064 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.568064 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.821496 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.821496 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 15 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 821 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4037 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5036 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4531 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.089417 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005249 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.881409 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 507029075 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 507029075 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 480958 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 155860 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 636818 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 3773399 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 3773399 # number of Writeback hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 109301 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 109301 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 35296 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 35296 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 877723 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 877723 # number of ReadExReq hits +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 8733791 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadCleanReq_hits::total 8733791 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2708727 # number of ReadSharedReq hits +system.cpu0.l2cache.ReadSharedReq_hits::total 2708727 # number of ReadSharedReq hits +system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 190451 # number of InvalidateReq hits +system.cpu0.l2cache.InvalidateReq_hits::total 190451 # number of InvalidateReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 480958 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 155860 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 8733791 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 3586450 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 12957059 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 480958 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 155860 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 8733791 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 3586450 # number of overall hits +system.cpu0.l2cache.overall_hits::total 12957059 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 12195 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8813 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 21008 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 130468 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 130468 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 154478 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 154478 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 3 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 278567 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 278567 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 777554 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 777554 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1020411 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 1020411 # number of ReadSharedReq misses +system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 589182 # number of InvalidateReq misses +system.cpu0.l2cache.InvalidateReq_misses::total 589182 # number of InvalidateReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 12195 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8813 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 777554 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 1298978 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 2097540 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 12195 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8813 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 777554 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 1298978 # number of overall misses +system.cpu0.l2cache.overall_misses::total 2097540 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 429581500 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 328472000 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 758053500 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2811659500 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 2811659500 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3201796000 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3201796000 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2748498 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2748498 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 13465224999 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 13465224999 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 23641079500 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::total 23641079500 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 33953780489 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::total 33953780489 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 49014503000 # number of InvalidateReq miss cycles +system.cpu0.l2cache.InvalidateReq_miss_latency::total 49014503000 # number of InvalidateReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 429581500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 328472000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 23641079500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 47419005488 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 71818138488 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 429581500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 328472000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 23641079500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 47419005488 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 71818138488 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 493153 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 164673 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 657826 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 3773399 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 3773399 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 239769 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 239769 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 189774 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 189774 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 3 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1156290 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 1156290 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 9511345 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::total 9511345 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3729138 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::total 3729138 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 779633 # number of InvalidateReq accesses(hits+misses) +system.cpu0.l2cache.InvalidateReq_accesses::total 779633 # number of InvalidateReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 493153 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 164673 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 9511345 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 4885428 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 15054599 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 493153 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 164673 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 9511345 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 4885428 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 15054599 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.024729 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.053518 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.031935 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.544140 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.544140 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.814010 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.814010 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.224764 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.224764 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.022499 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.049781 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.078068 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.253734 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.132291 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.022499 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.049781 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.078068 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.253734 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.132291 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 35896.913706 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 39062.072573 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 30218.617556 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 34073.109321 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32452.281589 # average ReadReq miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.data 364.515205 # average WriteInvalidateReq miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total 364.515205 # average WriteInvalidateReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21901.534114 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21901.534114 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20739.632883 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20739.632883 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 829749.500000 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 829749.500000 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50791.693516 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50791.693516 # average ReadExReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 35896.913706 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 39062.072573 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 30218.617556 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 37486.931343 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 34756.141139 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 35896.913706 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 39062.072573 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 30218.617556 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 37486.931343 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 34756.141139 # average overall miss latency -system.cpu0.l2cache.blocked_cycles::no_mshrs 127 # number of cycles access was blocked +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.240914 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.240914 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.081750 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.081750 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.273632 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.273632 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.755717 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.755717 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.024729 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.053518 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.081750 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.265888 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.139329 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.024729 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.053518 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.081750 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.265888 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.139329 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 35226.035260 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 37271.303756 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 36084.039414 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21550.567955 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21550.567955 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20726.550059 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20726.550059 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 916166 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 916166 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 48337.473567 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 48337.473567 # average ReadExReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 30404.421429 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 30404.421429 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 33274.612376 # average ReadSharedReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 33274.612376 # average ReadSharedReq miss latency +system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 83190.767878 # average InvalidateReq miss latency +system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 83190.767878 # average InvalidateReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 35226.035260 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 37271.303756 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 30404.421429 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 36504.856501 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 34239.222369 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 35226.035260 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 37271.303756 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 30404.421429 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 36504.856501 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 34239.222369 # average overall miss latency +system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 127 # average number of cycles each access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 1439553 # number of writebacks -system.cpu0.l2cache.writebacks::total 1439553 # number of writebacks +system.cpu0.l2cache.writebacks::writebacks 1441697 # number of writebacks +system.cpu0.l2cache.writebacks::total 1441697 # number of writebacks system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 3 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 11 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 1023 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::total 1037 # number of ReadReq MSHR hits -system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::cpu0.data 27 # number of WriteInvalidateReq MSHR hits -system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::total 27 # number of WriteInvalidateReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 8712 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 8712 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 8436 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 8436 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 8 # number of ReadCleanReq MSHR hits +system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 8 # number of ReadCleanReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 865 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 865 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 68 # number of InvalidateReq MSHR hits +system.cpu0.l2cache.InvalidateReq_mshr_hits::total 68 # number of InvalidateReq MSHR hits system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 3 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 11 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 9735 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 9749 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 8 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 9301 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 9312 # number of demand (read+write) MSHR hits system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 3 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 11 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 9735 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 9749 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 12017 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8237 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 803330 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 1046920 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 1870504 # number of ReadReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 757617 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 757617 # number of HardPFReq MSHR misses -system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.data 596190 # number of WriteInvalidateReq MSHR misses -system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total 596190 # number of WriteInvalidateReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 136954 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 136954 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 166233 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 166233 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 2 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 260176 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 260176 # number of ReadExReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 12017 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8237 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 803330 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1307096 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 2130680 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 12017 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8237 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 803330 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1307096 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 757617 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 2888297 # number of overall MSHR misses -system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 52307 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31604 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 83911 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 30977 # number of WriteReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 30977 # number of WriteReq MSHR uncacheable -system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 52307 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 62581 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 114888 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 352675786 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 267790036 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 19027435054 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 28762264327 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 48410165203 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 36487468285 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 36487468285 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 26018290315 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 26018290315 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2786437286 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2786437286 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2450969244 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2450969244 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1425499 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1425499 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 10771329997 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 10771329997 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 352675786 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 267790036 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 19027435054 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 39533594324 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 59181495200 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 352675786 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 267790036 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 19027435054 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 39533594324 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 36487468285 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 95668963485 # number of overall MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4391070750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5359743750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 9750814500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5053047499 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5053047499 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 4391070750 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10412791249 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 14803861999 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.022499 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.049763 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.078067 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.262156 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.124838 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 8 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 9301 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 9312 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 12195 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8810 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 21005 # number of ReadReq MSHR misses +system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 114790 # number of CleanEvict MSHR misses +system.cpu0.l2cache.CleanEvict_mshr_misses::total 114790 # number of CleanEvict MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 731294 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 731294 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 130468 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 130468 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 154478 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 154478 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 3 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 270131 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 270131 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 777546 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 777546 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1019546 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1019546 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 589114 # number of InvalidateReq MSHR misses +system.cpu0.l2cache.InvalidateReq_mshr_misses::total 589114 # number of InvalidateReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 12195 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8810 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 777546 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1289677 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 2088228 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 12195 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8810 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 777546 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1289677 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 731294 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 2819522 # number of overall MSHR misses +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 52292 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 32882 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 85174 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 32815 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 32815 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 52292 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 65697 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 117989 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 356411500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 275560000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 631971500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 35755952523 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 35755952523 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2648670495 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2648670495 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2356042000 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2356042000 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2382498 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2382498 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 10796229999 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 10796229999 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 18975468000 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 18975468000 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 27752056489 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 27752056489 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 45478624000 # number of InvalidateReq MSHR miss cycles +system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 45478624000 # number of InvalidateReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 356411500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 275560000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 18975468000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 38548286488 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 58155725988 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 356411500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 275560000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 18975468000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 38548286488 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 35755952523 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 93911678511 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4359444500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5648614500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 10008059000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5436600500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5436600500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 4359444500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11085215000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15444659500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.024729 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.053500 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.031931 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.730368 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.730368 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.568064 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.568064 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.821496 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.821496 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.544140 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.544140 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.814010 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.814010 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.217482 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.217482 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.022499 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.049763 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.078067 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.251858 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.131688 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.022499 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.049763 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.078067 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.251858 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.233619 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.233619 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.081749 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.081749 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.273400 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.273400 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.755630 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.755630 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.024729 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.053500 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.081749 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.263984 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.138710 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.024729 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.053500 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.081749 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.263984 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.178514 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 29348.072397 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 32510.627170 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23685.702083 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 27473.220807 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25880.813515 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48160.836260 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 48160.836260 # average HardPFReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 43640.937143 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 43640.937143 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20345.789725 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20345.789725 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14744.179820 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14744.179820 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 712749.500000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 712749.500000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41400.167567 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41400.167567 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 29348.072397 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 32510.627170 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23685.702083 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 30245.364016 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27775.872116 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 29348.072397 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 32510.627170 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23685.702083 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 30245.364016 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48160.836260 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 33122.966054 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83948.051886 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 169590.676813 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 116204.246166 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 163122.558640 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 163122.558640 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83948.051886 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 166389.019814 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 128854.728074 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.187286 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 29226.035260 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 31278.093076 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 30086.717448 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48894.087088 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 48894.087088 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20301.303730 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20301.303730 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15251.634537 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15251.634537 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 794166 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 794166 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39966.645809 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39966.645809 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 24404.302768 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 24404.302768 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 27220.014094 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 27220.014094 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 77198.341917 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 77198.341917 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 29226.035260 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 31278.093076 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24404.302768 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29889.876681 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27849.318172 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 29226.035260 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 31278.093076 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24404.302768 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29889.876681 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48894.087088 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 33307.659423 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83367.331523 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 171784.395718 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 117501.338437 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165674.249581 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 165674.249581 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83367.331523 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 168732.438315 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 130899.147378 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 17664917 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 15307376 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 38492 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 30977 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 3966591 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 1103078 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1166462 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 816287 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 481802 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 368927 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 516230 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 30 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 64 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1338230 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1206066 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 20685127 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17177406 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 364539 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1170846 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 39397918 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 661924032 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 645723507 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1324200 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4272848 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1313244587 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 4794163 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 26128529 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 1.203121 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.402322 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 870203 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 14200168 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 38095 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 32815 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 7469298 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 14383795 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1113522 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 480939 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 348630 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 494804 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 46 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 104 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1552927 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1165328 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9511346 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 6196752 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 886361 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 779633 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 28635865 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18059535 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 358708 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1078688 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 48132796 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 612072768 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 561022439 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1317384 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3945224 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1178357815 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 11561310 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 42854991 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 1.281176 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.449573 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 20821287 79.69% 79.69% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 5307242 20.31% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 30805196 71.88% 71.88% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 12049795 28.12% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 26128529 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 15626998682 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 42854991 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 19582200977 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 207003480 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 188679986 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 15540735463 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 14347273859 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 8534595583 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 7985002182 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 199309237 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 194043982 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 637104704 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 585561447 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 125576312 # Number of BP lookups -system.cpu1.branchPred.condPredicted 90437850 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 5588126 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 96414800 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 70448335 # Number of BTB hits +system.cpu1.branchPred.lookups 137760504 # Number of BP lookups +system.cpu1.branchPred.condPredicted 98367064 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 6188278 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 103396299 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 75843064 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 73.067968 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 14240452 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 921306 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 73.351817 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 15930905 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 1003913 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1329,67 +1378,62 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 267188 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 267188 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10577 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 85745 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 267188 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 267188 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 267188 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 96322 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 19417.832759 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 17582.202051 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 14852.958051 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 91721 95.22% 95.22% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 3398 3.53% 98.75% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-98303 602 0.62% 99.38% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-131071 416 0.43% 99.81% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-163839 24 0.02% 99.83% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::163840-196607 24 0.02% 99.86% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-229375 36 0.04% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::229376-262143 19 0.02% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-294911 31 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::294912-327679 34 0.04% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-360447 8 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::360448-393215 3 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-425983 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 96322 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 1244507444 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1244507444 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 1244507444 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 85745 89.02% 89.02% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 10577 10.98% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 96322 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 267188 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 290439 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 290439 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10797 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 87034 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 290439 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 290439 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 290439 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 97831 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 20885.603745 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 19076.396548 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 15781.781984 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 96557 98.70% 98.70% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1078 1.10% 99.80% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 36 0.04% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 66 0.07% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 60 0.06% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 20 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 6 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 5 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 97831 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -1532721648 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -1532721648 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -1532721648 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 87034 88.96% 88.96% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 10797 11.04% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 97831 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 290439 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 267188 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 96322 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 290439 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 97831 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 96322 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 363510 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 97831 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 388270 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 79480191 # DTB read hits -system.cpu1.dtb.read_misses 220503 # DTB read misses -system.cpu1.dtb.write_hits 69950509 # DTB write hits -system.cpu1.dtb.write_misses 46685 # DTB write misses +system.cpu1.dtb.read_hits 89204123 # DTB read hits +system.cpu1.dtb.read_misses 242859 # DTB read misses +system.cpu1.dtb.write_hits 77378465 # DTB write hits +system.cpu1.dtb.write_misses 47580 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 43363 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1048 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 40279 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1007 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 7671 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 41950 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1046 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 40087 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1034 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 8257 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 12807 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 79700694 # DTB read accesses -system.cpu1.dtb.write_accesses 69997194 # DTB write accesses +system.cpu1.dtb.perms_faults 11467 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 89446982 # DTB read accesses +system.cpu1.dtb.write_accesses 77426045 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 149430700 # DTB hits -system.cpu1.dtb.misses 267188 # DTB misses -system.cpu1.dtb.accesses 149697888 # DTB accesses +system.cpu1.dtb.hits 166582588 # DTB hits +system.cpu1.dtb.misses 290439 # DTB misses +system.cpu1.dtb.accesses 166873027 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1419,187 +1463,192 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 64917 # Table walker walks requested -system.cpu1.itb.walker.walksLong 64917 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 645 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 55496 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 64917 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 64917 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 64917 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 56141 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 22418.994977 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 19682.840516 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 19289.014659 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 54677 97.39% 97.39% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 1297 2.31% 99.70% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 47 0.08% 99.79% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 81 0.14% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 18 0.03% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 16 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 1 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 3 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 56141 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1243919944 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1243919944 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1243919944 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 55496 98.85% 98.85% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 645 1.15% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 56141 # Table walker page sizes translated +system.cpu1.itb.walker.walks 66791 # Table walker walks requested +system.cpu1.itb.walker.walksLong 66791 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 712 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 57147 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 66791 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 66791 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 66791 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 57859 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 23479.562384 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 21074.499694 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 18067.183609 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 53326 92.17% 92.17% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 3146 5.44% 97.60% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 488 0.84% 98.45% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 735 1.27% 99.72% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 30 0.05% 99.77% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 27 0.05% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 52 0.09% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 18 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 8 0.01% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 9 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 10 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 8 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 57859 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -1533304148 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1533304148 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1533304148 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 57147 98.77% 98.77% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 712 1.23% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 57859 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 64917 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 64917 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 66791 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 66791 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 56141 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 56141 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 121058 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 225481249 # ITB inst hits -system.cpu1.itb.inst_misses 64917 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 57859 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 57859 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 124650 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 246625416 # ITB inst hits +system.cpu1.itb.inst_misses 66791 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 43363 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1048 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 28543 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 41950 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1046 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 29073 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 202570 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 217204 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 225546166 # ITB inst accesses -system.cpu1.itb.hits 225481249 # DTB hits -system.cpu1.itb.misses 64917 # DTB misses -system.cpu1.itb.accesses 225546166 # DTB accesses -system.cpu1.numCycles 849119079 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 246692207 # ITB inst accesses +system.cpu1.itb.hits 246625416 # DTB hits +system.cpu1.itb.misses 66791 # DTB misses +system.cpu1.itb.accesses 246692207 # DTB accesses +system.cpu1.numCycles 916577474 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 406051299 # Number of instructions committed -system.cpu1.committedOps 478293699 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 46606937 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 5644 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 94106060514 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.091162 # CPI: cycles per instruction -system.cpu1.ipc 0.478203 # IPC: instructions per cycle +system.cpu1.committedInsts 453450144 # Number of instructions committed +system.cpu1.committedOps 532984432 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 47678042 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 5221 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 94048897478 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.021341 # CPI: cycles per instruction +system.cpu1.ipc 0.494721 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 5757 # number of quiesce instructions executed -system.cpu1.tickCycles 666946808 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 182172271 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.replacements 5052284 # number of replacements -system.cpu1.dcache.tags.tagsinuse 457.990994 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 141727438 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5052796 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 28.049309 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8380007678500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 457.990994 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.894514 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.894514 # Average percentage of cache occupancy +system.cpu1.kern.inst.quiesce 5293 # number of quiesce instructions executed +system.cpu1.tickCycles 728135326 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 188442148 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.replacements 5347951 # number of replacements +system.cpu1.dcache.tags.tagsinuse 430.817141 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 158458993 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5348463 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 29.627015 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8387659413500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 430.817141 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.841440 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.841440 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 359 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 377 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 301466109 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 301466109 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 72704936 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 72704936 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 65165576 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 65165576 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 206723 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 206723 # number of SoftPFReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 46881 # number of WriteInvalidateReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::total 46881 # number of WriteInvalidateReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1586345 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1586345 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1544117 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1544117 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 137870512 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 137870512 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 138077235 # number of overall hits -system.cpu1.dcache.overall_hits::total 138077235 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 3207186 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 3207186 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 2249159 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 2249159 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 660232 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 660232 # number of SoftPFReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 426407 # number of WriteInvalidateReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::total 426407 # number of WriteInvalidateReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 160976 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 160976 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 201965 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 201965 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 5456345 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 5456345 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 6116577 # number of overall misses -system.cpu1.dcache.overall_misses::total 6116577 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 49733165026 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 49733165026 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 39916128019 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 39916128019 # number of WriteReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 12105984043 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 12105984043 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2535632453 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2535632453 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4276755567 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4276755567 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1256500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1256500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 89649293045 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 89649293045 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 89649293045 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 89649293045 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 75912122 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 75912122 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 67414735 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 67414735 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 866955 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 866955 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 473288 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::total 473288 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1747321 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1747321 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1746082 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1746082 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 143326857 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 143326857 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 144193812 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 144193812 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.042249 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.042249 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.033363 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.033363 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.761553 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.761553 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.900946 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.900946 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.092127 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.092127 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.115668 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.115668 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.038069 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.038069 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.042419 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.042419 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15506.791632 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15506.791632 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17747.134826 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 17747.134826 # average WriteReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 28390.678490 # average WriteInvalidateReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 28390.678490 # average WriteInvalidateReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15751.617962 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15751.617962 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21175.726324 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21175.726324 # average StoreCondReq miss latency +system.cpu1.dcache.tags.tag_accesses 335833986 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 335833986 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 81837847 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 81837847 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 72225758 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 72225758 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 239509 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 239509 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 145455 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 145455 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1785819 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1785819 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1759762 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1759762 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 154063605 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 154063605 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 154303114 # number of overall hits +system.cpu1.dcache.overall_hits::total 154303114 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 3469404 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 3469404 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 2254005 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 2254005 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 641263 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 641263 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 468533 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 468533 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 172541 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 172541 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 196757 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 196757 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 5723409 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 5723409 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 6364672 # number of overall misses +system.cpu1.dcache.overall_misses::total 6364672 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 51425230000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 51425230000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 38096829500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 38096829500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 16555952500 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 16555952500 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2623224000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2623224000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4131954500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4131954500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2147500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2147500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 89522059500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 89522059500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 89522059500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 89522059500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 85307251 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 85307251 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 74479763 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 74479763 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 880772 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 880772 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 613988 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 613988 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1958360 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1958360 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1956519 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1956519 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 159787014 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 159787014 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 160667786 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 160667786 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.040670 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.040670 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030263 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.030263 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.728069 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.728069 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.763098 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.763098 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.088105 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.088105 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100565 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100565 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035819 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.035819 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.039614 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.039614 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14822.496890 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14822.496890 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16901.838949 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 16901.838949 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 35335.723418 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 35335.723418 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15203.482071 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15203.482071 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21000.292239 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21000.292239 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16430.283101 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 16430.283101 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14656.775030 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14656.775030 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15641.387764 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 15641.387764 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14065.463153 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14065.463153 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1608,161 +1657,161 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 3294639 # number of writebacks -system.cpu1.dcache.writebacks::total 3294639 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 376716 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 376716 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 934861 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 934861 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 50 # number of WriteInvalidateReq MSHR hits -system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 50 # number of WriteInvalidateReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 39920 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 39920 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 26 # number of StoreCondReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::total 26 # number of StoreCondReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1311577 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1311577 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1311577 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1311577 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2830470 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 2830470 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1314298 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1314298 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 659943 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 659943 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 426357 # number of WriteInvalidateReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 426357 # number of WriteInvalidateReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 121056 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 121056 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 201939 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 201939 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4144768 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4144768 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 4804711 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 4804711 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 7026 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 7026 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7515 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 7515 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 14541 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 14541 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 38398702439 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 38398702439 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 21764603493 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 21764603493 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13372610673 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13372610673 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 11459992206 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 11459992206 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1620200910 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1620200910 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3963729421 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3963729421 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1148000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1148000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 60163305932 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 60163305932 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 73535916605 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 73535916605 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 828088750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 828088750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 987688750 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 987688750 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1815777500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1815777500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037286 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037286 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019496 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.019496 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.761219 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.761219 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.900841 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.900841 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.069281 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.069281 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.115653 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.115653 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028918 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.028918 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033321 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.033321 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13566.193049 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13566.193049 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16559.869598 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16559.869598 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20263.281333 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20263.281333 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 26878.864909 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 26878.864909 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13383.895966 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13383.895966 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19628.350249 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19628.350249 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 3440440 # number of writebacks +system.cpu1.dcache.writebacks::total 3440440 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 392659 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 392659 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 925831 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 925831 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 46 # number of WriteLineReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::total 46 # number of WriteLineReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 41204 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 41204 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 43 # number of StoreCondReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::total 43 # number of StoreCondReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1318490 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1318490 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1318490 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1318490 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3076745 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 3076745 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1328174 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1328174 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 640972 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 640972 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 468487 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 468487 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 131337 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 131337 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 196714 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 196714 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4404919 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4404919 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5045891 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5045891 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5366 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 5366 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 5280 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 5280 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10646 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 10646 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 41480566500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 41480566500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 21714665000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 21714665000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12811841000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 12811841000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 16084660000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 16084660000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1751023000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1751023000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3933903500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3933903500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1830000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1830000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 63195231500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 63195231500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 76007072500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 76007072500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 593786000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 593786000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 651165500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 651165500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1244951500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1244951500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036067 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036067 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017833 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017833 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.727739 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.727739 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.763023 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.763023 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.067065 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.067065 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100543 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100543 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027567 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027567 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031406 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.031406 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13481.964381 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13481.964381 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16349.262220 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16349.262220 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19988.144568 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 19988.144568 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 34333.204550 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 34333.204550 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13332.290215 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13332.290215 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19998.086054 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19998.086054 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14515.482153 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14515.482153 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15304.961444 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15304.961444 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117860.624822 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 117860.624822 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 131428.975383 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 131428.975383 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 124872.945465 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 124872.945465 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14346.513863 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14346.513863 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15063.161788 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15063.161788 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 110657.100261 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 110657.100261 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 123326.799242 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 123326.799242 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 116940.775878 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 116940.775878 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 8512500 # number of replacements -system.cpu1.icache.tags.tagsinuse 507.044267 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 216759728 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 8513012 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 25.462166 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8369990866500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.044267 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990321 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.990321 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 9156821 # number of replacements +system.cpu1.icache.tags.tagsinuse 506.982135 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 237244674 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 9157333 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 25.907617 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8375787773000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.982135 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990199 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.990199 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 217 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 336 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 459058494 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 459058494 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 216759728 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 216759728 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 216759728 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 216759728 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 216759728 # number of overall hits -system.cpu1.icache.overall_hits::total 216759728 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 8513013 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 8513013 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 8513013 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 8513013 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 8513013 # number of overall misses -system.cpu1.icache.overall_misses::total 8513013 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 85304905568 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 85304905568 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 85304905568 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 85304905568 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 85304905568 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 85304905568 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 225272741 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 225272741 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 225272741 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 225272741 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 225272741 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 225272741 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.037790 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.037790 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.037790 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.037790 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.037790 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.037790 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10020.530401 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 10020.530401 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10020.530401 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10020.530401 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10020.530401 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10020.530401 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 501961349 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 501961349 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 237244674 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 237244674 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 237244674 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 237244674 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 237244674 # number of overall hits +system.cpu1.icache.overall_hits::total 237244674 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 9157334 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 9157334 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 9157334 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 9157334 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 9157334 # number of overall misses +system.cpu1.icache.overall_misses::total 9157334 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 90409615500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 90409615500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 90409615500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 90409615500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 90409615500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 90409615500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 246402008 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 246402008 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 246402008 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 246402008 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 246402008 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 246402008 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.037164 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.037164 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.037164 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.037164 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.037164 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.037164 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9872.918854 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 9872.918854 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9872.918854 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9872.918854 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9872.918854 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9872.918854 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1771,241 +1820,257 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8513013 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 8513013 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 8513013 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 8513013 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 8513013 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 8513013 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 90 # number of ReadReq MSHR uncacheable -system.cpu1.icache.ReadReq_mshr_uncacheable::total 90 # number of ReadReq MSHR uncacheable -system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 90 # number of overall MSHR uncacheable misses -system.cpu1.icache.overall_mshr_uncacheable_misses::total 90 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 76768195856 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 76768195856 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 76768195856 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 76768195856 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 76768195856 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 76768195856 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8107000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8107000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8107000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 8107000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.037790 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.037790 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.037790 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.037790 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.037790 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.037790 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9017.746814 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9017.746814 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9017.746814 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 9017.746814 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9017.746814 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 9017.746814 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90077.777778 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 90077.777778 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90077.777778 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 90077.777778 # average overall mshr uncacheable latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9157334 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 9157334 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 9157334 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 9157334 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 9157334 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 9157334 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable +system.cpu1.icache.ReadReq_mshr_uncacheable::total 93 # number of ReadReq MSHR uncacheable +system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses +system.cpu1.icache.overall_mshr_uncacheable_misses::total 93 # number of overall MSHR uncacheable misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 85830949000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 85830949000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 85830949000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 85830949000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 85830949000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 85830949000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8848000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8848000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8848000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 8848000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.037164 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.037164 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.037164 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.037164 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.037164 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.037164 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9372.918908 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9372.918908 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9372.918908 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 9372.918908 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9372.918908 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 9372.918908 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 95139.784946 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 95139.784946 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 95139.784946 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 95139.784946 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 7158191 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 7159863 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 1351 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 7355033 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 7356454 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 1193 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 847001 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 2383886 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13587.340153 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 13938188 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2400056 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 5.807443 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 10048790087250 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 4939.758457 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 75.017087 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 74.049784 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4551.314512 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3187.549823 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 759.650489 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.301499 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004579 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004520 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.277790 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.194553 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.046365 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.829305 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1323 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 67 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14780 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 42 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 286 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 433 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 562 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 40 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 21 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1093 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4947 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2638 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5915 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.080750 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004089 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.902100 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 292928618 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 292928618 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 489959 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 155192 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 7753793 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 2612837 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 11011781 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 3294638 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 3294638 # number of Writeback hits -system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 173190 # number of WriteInvalidateReq hits -system.cpu1.l2cache.WriteInvalidateReq_hits::total 173190 # number of WriteInvalidateReq hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 70896 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 70896 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 35338 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 35338 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 862674 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 862674 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 489959 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 155192 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 7753793 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3475511 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 11874455 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 489959 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 155192 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 7753793 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3475511 # number of overall hits -system.cpu1.l2cache.overall_hits::total 11874455 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 11727 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8782 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 759220 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 998421 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 1778150 # number of ReadReq misses -system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 251764 # number of WriteInvalidateReq misses -system.cpu1.l2cache.WriteInvalidateReq_misses::total 251764 # number of WriteInvalidateReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 136318 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 136318 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 166600 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 166600 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 246181 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 246181 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 11727 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8782 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 759220 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 1244602 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 2024331 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 11727 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8782 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 759220 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 1244602 # number of overall misses -system.cpu1.l2cache.overall_misses::total 2024331 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 449146209 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 373707270 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 22071218543 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 32673719778 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 55567791800 # number of ReadReq miss cycles -system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data 216255594 # number of WriteInvalidateReq miss cycles -system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 216255594 # number of WriteInvalidateReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2967566092 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 2967566092 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3447328545 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3447328545 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1119500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1119500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 10839077173 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 10839077173 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 449146209 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 373707270 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 22071218543 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 43512796951 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 66406868973 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 449146209 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 373707270 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 22071218543 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 43512796951 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 66406868973 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 501686 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 163974 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 8513013 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 3611258 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 12789931 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 3294638 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 3294638 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 424954 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.l2cache.WriteInvalidateReq_accesses::total 424954 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 207214 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 207214 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 201938 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 201938 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1108855 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 1108855 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 501686 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 163974 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 8513013 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 4720113 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 13898786 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 501686 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 163974 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 8513013 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 4720113 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 13898786 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.023375 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.053557 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.089183 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.276475 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.139027 # miss rate for ReadReq accesses -system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.592450 # miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.592450 # miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.657861 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.657861 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.825006 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.825006 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.prefetcher.pfSpanPage 921370 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 2420449 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13525.501015 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 25921683 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 2436577 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 10.638565 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 9890893366500 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 5242.566110 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 80.941753 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 86.247702 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3561.549924 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3753.026790 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 801.168735 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.319981 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004940 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005264 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.217380 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.229067 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.048899 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.825531 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1192 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 58 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14878 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 317 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 534 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 335 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 3 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 39 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1163 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5423 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4799 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3398 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.072754 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003540 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.908081 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 488189494 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 488189494 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 527706 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 160378 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 688084 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 3440434 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 3440434 # number of Writeback hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 69060 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 69060 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 37815 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 37815 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 888572 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 888572 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 8367748 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 8367748 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2856681 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 2856681 # number of ReadSharedReq hits +system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 194722 # number of InvalidateReq hits +system.cpu1.l2cache.InvalidateReq_hits::total 194722 # number of InvalidateReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 527706 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 160378 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 8367748 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 3745253 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 12801085 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 527706 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 160378 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 8367748 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 3745253 # number of overall hits +system.cpu1.l2cache.overall_hits::total 12801085 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 11992 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8532 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 20524 # number of ReadReq misses +system.cpu1.l2cache.Writeback_misses::writebacks 3 # number of Writeback misses +system.cpu1.l2cache.Writeback_misses::total 3 # number of Writeback misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 136249 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 136249 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 158895 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 158895 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 4 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 235953 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 235953 # number of ReadExReq misses +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 789586 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadCleanReq_misses::total 789586 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 992043 # number of ReadSharedReq misses +system.cpu1.l2cache.ReadSharedReq_misses::total 992043 # number of ReadSharedReq misses +system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 272649 # number of InvalidateReq misses +system.cpu1.l2cache.InvalidateReq_misses::total 272649 # number of InvalidateReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 11992 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8532 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 789586 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 1227996 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 2038106 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 11992 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8532 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 789586 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 1227996 # number of overall misses +system.cpu1.l2cache.overall_misses::total 2038106 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 446382000 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 354037500 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 800419500 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2966896500 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 2966896500 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3304625499 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3304625499 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1763998 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1763998 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 9908657497 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 9908657497 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 22229315000 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::total 22229315000 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 31556071491 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::total 31556071491 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 14034162000 # number of InvalidateReq miss cycles +system.cpu1.l2cache.InvalidateReq_miss_latency::total 14034162000 # number of InvalidateReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 446382000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 354037500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 22229315000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 41464728988 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 64494463488 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 446382000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 354037500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 22229315000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 41464728988 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 64494463488 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 539698 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 168910 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 708608 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 3440437 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 3440437 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 205309 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 205309 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 196710 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 196710 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 4 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1124525 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 1124525 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 9157334 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::total 9157334 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3848724 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::total 3848724 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 467371 # number of InvalidateReq accesses(hits+misses) +system.cpu1.l2cache.InvalidateReq_accesses::total 467371 # number of InvalidateReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 539698 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 168910 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 9157334 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 4973249 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 14839191 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 539698 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 168910 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 9157334 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 4973249 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 14839191 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.022220 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.050512 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.028964 # miss rate for ReadReq accesses +system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000001 # miss rate for Writeback accesses +system.cpu1.l2cache.Writeback_miss_rate::total 0.000001 # miss rate for Writeback accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.663629 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.663629 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.807763 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.807763 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.222014 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.222014 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.023375 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.053557 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.089183 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.263681 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.145648 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.023375 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.053557 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.089183 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.263681 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.145648 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 38300.179841 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 42553.777044 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 29070.912967 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 32725.393174 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 31250.339848 # average ReadReq miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data 858.961543 # average WriteInvalidateReq miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 858.961543 # average WriteInvalidateReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21769.436846 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21769.436846 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20692.248169 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20692.248169 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 1119500 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 1119500 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 44028.894078 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 44028.894078 # average ReadExReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 38300.179841 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 42553.777044 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 29070.912967 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34961.214068 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 32804.353129 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 38300.179841 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 42553.777044 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 29070.912967 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34961.214068 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 32804.353129 # average overall miss latency +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.209825 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.209825 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.086224 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.086224 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.257759 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.257759 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.583367 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.583367 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.022220 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.050512 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.086224 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.246920 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.137346 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.022220 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.050512 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.086224 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.246920 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.137346 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 37223.315544 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 41495.253165 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 38999.196063 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21775.546976 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21775.546976 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20797.542396 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20797.542396 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 440999.500000 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 440999.500000 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 41994.200103 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 41994.200103 # average ReadExReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 28153.127082 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 28153.127082 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 31809.177113 # average ReadSharedReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 31809.177113 # average ReadSharedReq miss latency +system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 51473.366856 # average InvalidateReq miss latency +system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 51473.366856 # average InvalidateReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 37223.315544 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 41495.253165 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 28153.127082 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 33766.175939 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 31644.312655 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 37223.315544 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 41495.253165 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 28153.127082 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33766.175939 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 31644.312655 # average overall miss latency system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2014,214 +2079,236 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 1051021 # number of writebacks -system.cpu1.l2cache.writebacks::total 1051021 # number of writebacks -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 2 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 699 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::total 701 # number of ReadReq MSHR hits -system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.data 6 # number of WriteInvalidateReq MSHR hits -system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total 6 # number of WriteInvalidateReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 8312 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 8312 # number of ReadExReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 2 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 9011 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 9013 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 2 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 9011 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 9013 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 11727 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8782 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 759218 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 997722 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 1777449 # number of ReadReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 732693 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 732693 # number of HardPFReq MSHR misses -system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.data 251758 # number of WriteInvalidateReq MSHR misses -system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total 251758 # number of WriteInvalidateReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 136318 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 136318 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 166600 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 166600 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 1 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 237869 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 237869 # number of ReadExReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 11727 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8782 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 759218 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1235591 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 2015318 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 11727 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8782 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 759218 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1235591 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 732693 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 2748011 # number of overall MSHR misses -system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 90 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 7026 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 7116 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 7515 # number of WriteReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 7515 # number of WriteReq MSHR uncacheable -system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 90 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 14541 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 14631 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 372203283 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 315988754 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 17115860957 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 26083443690 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 43887496684 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 35590505004 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 35590505004 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 8154289208 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 8154289208 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2662634544 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2662634544 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2448254099 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2448254099 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 937500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 937500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8085398810 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8085398810 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 372203283 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 315988754 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 17115860957 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 34168842500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 51972895494 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 372203283 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 315988754 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 17115860957 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 34168842500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 35590505004 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 87563400498 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7349000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 771832750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 779181750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 931317500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 931317500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7349000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1703150250 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1710499250 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.023375 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.053557 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.089183 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.276281 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.138973 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.writebacks::writebacks 1031306 # number of writebacks +system.cpu1.l2cache.writebacks::total 1031306 # number of writebacks +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 2 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 7033 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 7033 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 1 # number of ReadCleanReq MSHR hits +system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits +system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 605 # number of ReadSharedReq MSHR hits +system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 605 # number of ReadSharedReq MSHR hits +system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 17 # number of InvalidateReq MSHR hits +system.cpu1.l2cache.InvalidateReq_mshr_hits::total 17 # number of InvalidateReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 2 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 7638 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 7641 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 2 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 7638 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 7641 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 11992 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8530 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 20522 # number of ReadReq MSHR misses +system.cpu1.l2cache.Writeback_mshr_misses::writebacks 3 # number of Writeback MSHR misses +system.cpu1.l2cache.Writeback_mshr_misses::total 3 # number of Writeback MSHR misses +system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 115811 # number of CleanEvict MSHR misses +system.cpu1.l2cache.CleanEvict_mshr_misses::total 115811 # number of CleanEvict MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 714965 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 714965 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 136249 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 136249 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 158895 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 158895 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 4 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 228920 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 228920 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 789585 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 789585 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 991438 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 991438 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 272632 # number of InvalidateReq MSHR misses +system.cpu1.l2cache.InvalidateReq_mshr_misses::total 272632 # number of InvalidateReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 11992 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8530 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 789585 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1220358 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 2030465 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 11992 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8530 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 789585 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1220358 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 714965 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 2745430 # number of overall MSHR misses +system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 5366 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 5459 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 5280 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 5280 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 10646 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 10739 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 374430000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 302816000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 677246000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 30632454632 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 30632454632 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2763352994 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2763352994 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2438062999 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2438062999 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1505998 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1505998 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 7634474497 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 7634474497 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 17491788500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 17491788500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 25566861991 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 25566861991 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 12398047000 # number of InvalidateReq MSHR miss cycles +system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 12398047000 # number of InvalidateReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 374430000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 302816000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 17491788500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 33201336488 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 51370370988 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 374430000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 302816000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 17491788500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 33201336488 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 30632454632 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 82002825620 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8104000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 550842500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 558946500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 611561500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 611561500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8104000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1162404000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1170508000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.022220 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.050500 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.028961 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for Writeback accesses +system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000001 # mshr miss rate for Writeback accesses +system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.592436 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.592436 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.657861 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.657861 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.825006 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.825006 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.663629 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.663629 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.807763 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.807763 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.214518 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.214518 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.023375 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.053557 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.089183 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.261771 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.145000 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.023375 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.053557 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.089183 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.261771 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.203570 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.203570 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.086224 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.086224 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.257602 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.257602 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.583331 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.583331 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022220 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.050500 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.086224 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.245384 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.136831 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022220 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.050500 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.086224 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.245384 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.197716 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 31739.002558 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35981.411296 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22544.066338 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 26142.997438 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 24691.283229 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48574.921562 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 48574.921562 # average HardPFReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32389.394609 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 32389.394609 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19532.523541 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19532.523541 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14695.402755 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14695.402755 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 937500 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 937500 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33990.973225 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33990.973225 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 31739.002558 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35981.411296 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22544.066338 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27653.845407 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25788.930330 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 31739.002558 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35981.411296 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22544.066338 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27653.845407 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48574.921562 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 31864.283112 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 81655.555556 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 109853.793054 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 109497.154300 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 123927.811045 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 123927.811045 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 81655.555556 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 117127.449969 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 116909.250906 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.185012 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 31223.315544 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35500.117233 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 33000.974564 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 42844.691183 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 42844.691183 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20281.638720 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20281.638720 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15343.862293 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15343.862293 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 376499.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 376499.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33349.967224 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33349.967224 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 22153.141840 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 22153.141840 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 25787.655901 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 25787.655901 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 45475.391737 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 45475.391737 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 31223.315544 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35500.117233 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22153.141840 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27206.226770 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25299.806196 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 31223.315544 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35500.117233 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22153.141840 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27206.226770 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 42844.691183 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29868.845908 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 87139.784946 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 102654.211703 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 102389.906576 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 115826.041667 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 115826.041667 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 87139.784946 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 109186.924667 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 108995.995903 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 15573132 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 13012901 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 38492 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 7515 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 3294638 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 1065592 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1119456 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 424954 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 452600 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 368137 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 473527 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 37 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 64 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1269149 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1115295 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17026205 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 14595450 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 357835 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1096931 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 33076421 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 544838528 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 546511254 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1311792 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4013488 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1096675062 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 5302361 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 23181233 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 1.250406 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.433247 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 927149 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 13939785 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 38095 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 5280 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 7136333 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 14143122 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 1073027 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 445884 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 351130 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 465721 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 65 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 104 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1873672 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1132302 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 9157334 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 6348630 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 574099 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 467371 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 27470555 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17217135 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 368278 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1176846 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 46232814 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 586075264 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 544882505 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1351280 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4317584 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1136626633 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 12009621 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 42070384 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 1.298426 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.457567 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 17376502 74.96% 74.96% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 5804731 25.04% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 29515487 70.16% 70.16% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 12554897 29.84% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 23181233 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 12806281931 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 42070384 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 18619089977 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 180531485 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 181245984 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 12781520856 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 13738184900 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7568960857 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7905383000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 194234943 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 199375485 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 595690418 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 637173449 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40349 # Transaction distribution -system.iobus.trans_dist::ReadResp 40349 # Transaction distribution -system.iobus.trans_dist::WriteReq 136610 # Transaction distribution -system.iobus.trans_dist::WriteResp 29882 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47640 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 40322 # Transaction distribution +system.iobus.trans_dist::ReadResp 40322 # Transaction distribution +system.iobus.trans_dist::WriteReq 136608 # Transaction distribution +system.iobus.trans_dist::WriteResp 136608 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47696 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -2231,18 +2318,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122574 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231264 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231264 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122578 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231202 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231202 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353918 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47660 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353860 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47716 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2252,18 +2339,18 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155681 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339072 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7339072 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155708 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338824 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338824 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496839 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36172000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496618 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36211000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2283,7 +2370,7 @@ system.iobus.reqLayer16.occupancy 12000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) @@ -2291,778 +2378,754 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 607512131 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 569805082 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92695000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92701000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 148588668 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147898000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 170500 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115637 # number of replacements -system.iocache.tags.tagsinuse 11.310069 # Cycle average of tags in use +system.iocache.tags.replacements 115582 # number of replacements +system.iocache.tags.tagsinuse 11.293791 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115653 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115598 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9129457632000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 7.399895 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 3.910174 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.462493 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.244386 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.706879 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9174209621000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.830929 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.462862 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.239433 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.466429 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.705862 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1041045 # Number of tag accesses -system.iocache.tags.data_accesses 1041045 # Number of data accesses +system.iocache.tags.tag_accesses 1040766 # Number of tag accesses +system.iocache.tags.data_accesses 1040766 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8904 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8941 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8873 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8910 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8904 # number of demand (read+write) misses -system.iocache.demand_misses::total 8944 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8873 # number of demand (read+write) misses +system.iocache.demand_misses::total 8913 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8904 # number of overall misses -system.iocache.overall_misses::total 8944 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5195500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1622865167 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1628060667 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8873 # number of overall misses +system.iocache.overall_misses::total 8913 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5195000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1631093968 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1636288968 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19842621296 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 19842621296 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5564500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1622865167 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1628429667 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5564500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1622865167 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1628429667 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12624582114 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12624582114 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5564000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1631093968 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1636657968 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5564000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1631093968 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1636657968 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8904 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8941 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8873 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8910 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8904 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8944 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8873 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8913 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8904 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8944 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8873 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8913 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140418.918919 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 182262.485063 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 182089.326362 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 183826.661558 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 183646.348822 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 185917.671989 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 185917.671989 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 182262.485063 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 182069.506597 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 182262.485063 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 182069.506597 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 110288 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118287.442040 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118287.442040 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139100 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 183826.661558 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 183625.936048 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139100 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 183826.661558 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 183625.936048 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 31363 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 16227 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3550 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.796574 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.834648 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106703 # number of writebacks -system.iocache.writebacks::total 106703 # number of writebacks +system.iocache.writebacks::writebacks 106694 # number of writebacks +system.iocache.writebacks::total 106694 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8904 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8941 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8873 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8910 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106728 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 106728 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8904 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8944 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8873 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8913 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8904 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8944 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3270500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1158690425 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1161960925 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 213000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 213000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14292687374 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14292687374 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3483500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1158690425 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1162173925 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3483500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1158690425 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1162173925 # number of overall MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8873 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8913 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3345000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1187443968 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1190788968 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7288182114 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7288182114 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3564000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1187443968 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1191007968 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3564000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1187443968 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1191007968 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 88391.891892 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 130131.449349 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 129958.721060 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 71000 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 71000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133916.941890 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133916.941890 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 130131.449349 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 129938.945103 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 130131.449349 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 129938.945103 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133826.661558 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 133646.348822 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68287.442040 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68287.442040 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 133826.661558 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 133625.936048 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 133826.661558 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 133625.936048 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1500558 # number of replacements -system.l2c.tags.tagsinuse 64423.791175 # Cycle average of tags in use -system.l2c.tags.total_refs 5010724 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1561220 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.209493 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 8774171000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 18406.054563 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 163.983954 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 204.641755 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4710.197783 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 8659.570147 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 11639.948556 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 186.392680 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 219.831325 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3870.715230 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 6776.772016 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 9585.683167 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.280854 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002502 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.003123 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.071872 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.132135 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.177612 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002844 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.003354 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.059062 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.103405 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.146266 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.983029 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 9890 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 240 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 50532 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 96 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 403 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 9383 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 240 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1652 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5116 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 43541 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.150909 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003662 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.771057 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 65146304 # Number of tag accesses -system.l2c.tags.data_accesses 65146304 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 6273 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4042 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 730934 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 606426 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 316069 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 6330 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 4616 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 702346 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 568034 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 305702 # number of ReadReq hits -system.l2c.ReadReq_hits::total 3250772 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 2490573 # number of Writeback hits -system.l2c.Writeback_hits::total 2490573 # number of Writeback hits -system.l2c.WriteInvalidateReq_hits::cpu0.data 135019 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::cpu1.data 128371 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::total 263390 # number of WriteInvalidateReq hits -system.l2c.UpgradeReq_hits::cpu0.data 28214 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 29967 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 58181 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 6140 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 6184 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 12324 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 50287 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 53122 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 103409 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 6273 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4042 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 730934 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 656713 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 316069 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 6330 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4616 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 702346 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 621156 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 305702 # number of demand (read+write) hits -system.l2c.demand_hits::total 3354181 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 6273 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4042 # number of overall hits -system.l2c.overall_hits::cpu0.inst 730934 # number of overall hits -system.l2c.overall_hits::cpu0.data 656713 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 316069 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 6330 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 4616 # number of overall hits -system.l2c.overall_hits::cpu1.inst 702346 # number of overall hits -system.l2c.overall_hits::cpu1.data 621156 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 305702 # number of overall hits -system.l2c.overall_hits::total 3354181 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 1959 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1699 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 72396 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 144803 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 235787 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 2337 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 2129 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 56871 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 125845 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 232153 # number of ReadReq misses -system.l2c.ReadReq_misses::total 875979 # number of ReadReq misses -system.l2c.WriteInvalidateReq_misses::cpu0.data 452629 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::cpu1.data 114950 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::total 567579 # number of WriteInvalidateReq misses -system.l2c.UpgradeReq_misses::cpu0.data 49085 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 42979 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 92064 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 9286 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 8933 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 18219 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 81593 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 56532 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 138125 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 1959 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1699 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 72396 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 226396 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 235787 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 2337 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 2129 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 56871 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 182377 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 232153 # number of demand (read+write) misses -system.l2c.demand_misses::total 1014104 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 1959 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1699 # number of overall misses -system.l2c.overall_misses::cpu0.inst 72396 # number of overall misses -system.l2c.overall_misses::cpu0.data 226396 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 235787 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 2337 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 2129 # number of overall misses -system.l2c.overall_misses::cpu1.inst 56871 # number of overall misses -system.l2c.overall_misses::cpu1.data 182377 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 232153 # number of overall misses -system.l2c.overall_misses::total 1014104 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 183693028 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 155473534 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 6124405792 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 13529784764 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 31415388170 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 209221515 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 197082496 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 4800216916 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 11513015623 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 30700473496 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 98828755334 # number of ReadReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::cpu0.data 50831909 # number of WriteInvalidateReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 41081201 # number of WriteInvalidateReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::total 91913110 # number of WriteInvalidateReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 314052545 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 253554995 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 567607540 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 59571609 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 53385310 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 112956919 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 7326457212 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 4778922810 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 12105380022 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 183693028 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 155473534 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 6124405792 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 20856241976 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 31415388170 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 209221515 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 197082496 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 4800216916 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 16291938433 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 30700473496 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 110934135356 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 183693028 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 155473534 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 6124405792 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 20856241976 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 31415388170 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 209221515 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 197082496 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 4800216916 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 16291938433 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 30700473496 # number of overall miss cycles -system.l2c.overall_miss_latency::total 110934135356 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 8232 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 5741 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 803330 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 751229 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 551856 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 8667 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 6745 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 759217 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 693879 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 537855 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 4126751 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 2490573 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 2490573 # number of Writeback accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu0.data 587648 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu1.data 243321 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::total 830969 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 77299 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 72946 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 150245 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 15426 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 15117 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 30543 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 131880 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 109654 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 241534 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 8232 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 5741 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 803330 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 883109 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 551856 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 8667 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 6745 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 759217 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 803533 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 537855 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 4368285 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 8232 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 5741 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 803330 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 883109 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 551856 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 8667 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 6745 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 759217 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 803533 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 537855 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 4368285 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.237974 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.295941 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.090120 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.192755 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.427262 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.269643 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.315641 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.074907 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.181364 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.431627 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.212268 # miss rate for ReadReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.770238 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.472421 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::total 0.683033 # miss rate for WriteInvalidateReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.635002 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.589189 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.612759 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.601971 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.590924 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.596503 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.618691 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.515549 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.571866 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.237974 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.295941 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.090120 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.256362 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.427262 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.269643 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.315641 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.074907 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.226969 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.431627 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.232152 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.237974 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.295941 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.090120 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.256362 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.427262 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.269643 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.315641 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.074907 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.226969 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.431627 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.232152 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 93768.773864 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 91508.848735 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 84595.914028 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 93435.804258 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 133236.302977 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 89525.680359 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 92570.453734 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 84405.354504 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 91485.681775 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 132242.415545 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 112820.918463 # average ReadReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data 112.303695 # average WriteInvalidateReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data 357.383219 # average WriteInvalidateReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::total 161.938884 # average WriteInvalidateReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6398.136804 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5899.508946 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 6165.358229 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6415.206655 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5976.190529 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 6199.951644 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 89792.717660 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 84534.826470 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 87640.760340 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 93768.773864 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 91508.848735 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 84595.914028 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 92122.837753 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 133236.302977 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89525.680359 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 92570.453734 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 84405.354504 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 89331.102239 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 132242.415545 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 109391.280733 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 93768.773864 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 91508.848735 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 84595.914028 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 92122.837753 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 133236.302977 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89525.680359 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 92570.453734 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 84405.354504 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 89331.102239 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 132242.415545 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 109391.280733 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 1791 # number of cycles access was blocked +system.l2c.tags.replacements 1460315 # number of replacements +system.l2c.tags.tagsinuse 63815.106569 # Cycle average of tags in use +system.l2c.tags.total_refs 6243583 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1520944 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 4.105071 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 17020.262251 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 105.114677 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 114.825043 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4617.432955 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 6910.402402 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 7514.168760 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 272.316465 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 336.862323 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3976.770964 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 9922.626808 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 13024.323921 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.259709 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001604 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.001752 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.070456 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.105444 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.114657 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004155 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.005140 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.060681 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.151407 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.198735 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.973741 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 9634 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 233 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 50762 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 214 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 450 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 8970 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 232 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2000 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4985 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 43502 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.147003 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.003555 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.774567 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 74931302 # Number of tag accesses +system.l2c.tags.data_accesses 74931302 # Number of data accesses +system.l2c.Writeback_hits::writebacks 2473005 # number of Writeback hits +system.l2c.Writeback_hits::total 2473005 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 29717 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 30251 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 59968 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 5861 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 6611 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 12472 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 174264 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 168948 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 343212 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6955 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 5054 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 704009 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 596815 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 296922 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6236 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4142 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 738933 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 577563 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 321187 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 3257816 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 6955 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 5054 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 704009 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 771079 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 296922 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 6236 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 4142 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 738933 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 746511 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 321187 # number of demand (read+write) hits +system.l2c.demand_hits::total 3601028 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 6955 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 5054 # number of overall hits +system.l2c.overall_hits::cpu0.inst 704009 # number of overall hits +system.l2c.overall_hits::cpu0.data 771079 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 296922 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 6236 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 4142 # number of overall hits +system.l2c.overall_hits::cpu1.inst 738933 # number of overall hits +system.l2c.overall_hits::cpu1.data 746511 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 321187 # number of overall hits +system.l2c.overall_hits::total 3601028 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 43094 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 44585 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 87679 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 8745 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 9538 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 18283 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 499472 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 152688 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 652160 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1944 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1581 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.inst 73537 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 135426 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 239395 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2244 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2077 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 50651 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 119141 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 208595 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 834591 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.dtb.walker 1944 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 1581 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 73537 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 634898 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 239395 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 2244 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 2077 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 50651 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 271829 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 208595 # number of demand (read+write) misses +system.l2c.demand_misses::total 1486751 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 1944 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 1581 # number of overall misses +system.l2c.overall_misses::cpu0.inst 73537 # number of overall misses +system.l2c.overall_misses::cpu0.data 634898 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 239395 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 2244 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 2077 # number of overall misses +system.l2c.overall_misses::cpu1.inst 50651 # number of overall misses +system.l2c.overall_misses::cpu1.data 271829 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 208595 # number of overall misses +system.l2c.overall_misses::total 1486751 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0.data 260324500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 277994500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 538319000 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 55253500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 54480000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 109733500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 46824185500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 13176547500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 60000733000 # number of ReadExReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 176295500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 146583500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.inst 6133823500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 12343951000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 30575603157 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 201877500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 184505000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.inst 4199208000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 10504090000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 25273313307 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 89739250464 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 176295500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 146583500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 6133823500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 59168136500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 30575603157 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 201877500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 184505000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 4199208000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 23680637500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 25273313307 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 149739983464 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 176295500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 146583500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 6133823500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 59168136500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 30575603157 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 201877500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 184505000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 4199208000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 23680637500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 25273313307 # number of overall miss cycles +system.l2c.overall_miss_latency::total 149739983464 # number of overall miss cycles +system.l2c.Writeback_accesses::writebacks 2473005 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 2473005 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 72811 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 74836 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 147647 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 14606 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 16149 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 30755 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 673736 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 321636 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 995372 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 8899 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6635 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.inst 777546 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 732241 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 536317 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8480 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 6219 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.inst 789584 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 696704 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 529782 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 4092407 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 8899 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 6635 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 777546 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1405977 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 536317 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 8480 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 6219 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 789584 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 1018340 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 529782 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 5087779 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 8899 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 6635 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 777546 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1405977 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 536317 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 8480 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 6219 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 789584 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 1018340 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 529782 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 5087779 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.591861 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.595769 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.593842 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.598727 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.590625 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.594472 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.741347 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.474723 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.655192 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.218452 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.238282 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.094576 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.184947 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.446368 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.264623 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.333977 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.064149 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.171007 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.393737 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.203936 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.218452 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.238282 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.094576 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.451571 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.446368 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.264623 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.333977 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.064149 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.266933 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.393737 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.292220 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.218452 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.238282 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.094576 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.451571 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.446368 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.264623 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.333977 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.064149 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.266933 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.393737 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.292220 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6040.852555 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6235.157564 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 6139.657158 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6318.296169 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5711.889285 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 6001.941694 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 93747.368221 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 86297.204102 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 92003.086666 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 90686.985597 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 92715.686275 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 83411.391544 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 91149.048189 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 127720.308097 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 89963.235294 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 88832.450650 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 82904.740282 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 88165.199218 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 121159.727256 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 107524.824092 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 90686.985597 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 92715.686275 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 83411.391544 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 93193.137323 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 127720.308097 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89963.235294 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 88832.450650 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 82904.740282 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 87115.935018 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 121159.727256 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 100716.248695 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 90686.985597 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 92715.686275 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 83411.391544 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 93193.137323 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 127720.308097 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89963.235294 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 88832.450650 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 82904.740282 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 87115.935018 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 121159.727256 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 100716.248695 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 107 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 28 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 3 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 63.964286 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 35.666667 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 1148541 # number of writebacks -system.l2c.writebacks::total 1148541 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 220 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.data 34 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 280 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.data 31 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 565 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 220 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 34 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 280 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 31 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 565 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 220 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 34 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 280 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 31 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 565 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1959 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1699 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 72176 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 144769 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 235787 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 2337 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 2129 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 56591 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 125814 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 232153 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 875414 # number of ReadReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::cpu0.data 452629 # number of WriteInvalidateReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data 114950 # number of WriteInvalidateReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::total 567579 # number of WriteInvalidateReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 49085 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 42979 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 92064 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 9286 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 8933 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 18219 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 81593 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 56532 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 138125 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 1959 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 1699 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 72176 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 226362 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 235787 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 2337 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 2129 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 56591 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 182346 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 232153 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 1013539 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 1959 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 1699 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 72176 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 226362 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 235787 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 2337 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 2129 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 56591 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 182346 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 232153 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 1013539 # number of overall MSHR misses -system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 52307 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31604 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 90 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 7024 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 91025 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 30977 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 7515 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 38492 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 52307 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 62581 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 90 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 14539 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 129517 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 158938472 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 134003964 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 5203434958 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 11714509236 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 28520645338 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 179744471 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 170218000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 4069447334 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 9933395627 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 27845565280 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 87929902680 # number of ReadReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data 15184820591 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 3681276299 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::total 18866096890 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 873684340 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 765163234 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 1638847574 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 165173761 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 159092905 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 324266666 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6306752788 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4071633688 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 10378386476 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 158938472 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 134003964 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 5203434958 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 18021262024 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 28520645338 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 179744471 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 170218000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 4069447334 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 14005029315 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 27845565280 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 98308289156 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 158938472 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 134003964 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 5203434958 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 18021262024 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 28520645338 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 179744471 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 170218000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 4069447334 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 14005029315 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 27845565280 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 98308289156 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 3188012750 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4742528250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5282500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 634028250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 8569851750 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4479331501 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 791938501 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 5271270002 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 3188012750 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9221859751 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5282500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1425966751 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 13841121752 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.237974 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.295941 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.089846 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.192710 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.427262 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.269643 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.315641 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.074539 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.181320 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.431627 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.212132 # mshr miss rate for ReadReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.770238 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.472421 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.683033 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.635002 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.589189 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.612759 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.601971 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.590924 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.596503 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.618691 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.515549 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.571866 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.237974 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.295941 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.089846 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.256324 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.427262 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.269643 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.315641 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.074539 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.226930 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.431627 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.232022 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.237974 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.295941 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.089846 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.256324 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.427262 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.269643 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.315641 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.074539 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.226930 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.431627 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.232022 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 81132.451251 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 78872.256622 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 72093.700926 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 80918.630618 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 120959.363061 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76912.482242 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 79952.090183 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71909.797212 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 78953.022931 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119944.886691 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 100443.793085 # average ReadReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 33548.050591 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32025.022175 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 33239.596409 # average WriteInvalidateReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17799.416115 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17803.188394 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17801.177159 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17787.396188 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17809.571812 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17798.269170 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 77295.267829 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72023.520979 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 75137.639645 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 81132.451251 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78872.256622 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72093.700926 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 79612.576422 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 120959.363061 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76912.482242 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 79952.090183 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71909.797212 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 76804.697197 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119944.886691 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 96995.072864 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 81132.451251 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78872.256622 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72093.700926 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 79612.576422 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 120959.363061 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76912.482242 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 79952.090183 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71909.797212 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 76804.697197 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119944.886691 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 96995.072864 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60948.109240 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 150061.012846 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 58694.444444 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 90265.980923 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 94148.330129 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 144601.849792 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 105381.038057 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 136944.559961 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60948.109240 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 147358.779038 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 58694.444444 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 98078.736571 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 106867.220149 # average overall mshr uncacheable latency +system.l2c.writebacks::writebacks 1116158 # number of writebacks +system.l2c.writebacks::total 1116158 # number of writebacks +system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 174 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu0.data 19 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 157 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.data 10 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 360 # number of ReadSharedReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 174 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 19 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 157 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 10 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 360 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 174 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 19 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 157 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 10 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 360 # number of overall MSHR hits +system.l2c.CleanEvict_mshr_misses::writebacks 53748 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 53748 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 43094 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 44585 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 87679 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 8745 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 9538 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 18283 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 499472 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 152688 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 652160 # number of ReadExReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1944 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1581 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 73363 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 135407 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 239395 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 2244 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 2077 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 50494 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 119131 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 208595 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 834231 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 1944 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 1581 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 73363 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 634879 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 239395 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 2244 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 2077 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 50494 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 271819 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 208595 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 1486391 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 1944 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 1581 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 73363 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 634879 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 239395 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 2244 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 2077 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 50494 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 271819 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 208595 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 1486391 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 52292 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 32882 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 5364 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 90631 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 32815 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 5280 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 38095 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 52292 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 65697 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 10644 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 128726 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 895608505 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 925545505 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 1821154010 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 181952000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 198394500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 380346500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 41829465500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 11649667500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 53479133000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 156855500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 130773500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 5387567000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 10988450500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 28181653157 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 179437500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 163735000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 3683448000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 9312099500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 23187363307 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 81371382964 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 156855500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 130773500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 5387567000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 52817916000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 28181653157 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 179437500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 163735000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 3683448000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 20961767000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 23187363307 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 134850515964 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 156855500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 130773500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 5387567000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 52817916000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 28181653157 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 179437500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 163735000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 3683448000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 20961767000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 23187363307 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 134850515964 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 3261312500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5056717000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6149000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 454250000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 8778428500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4878683500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 521791000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 5400474500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 3261312500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9935400500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6149000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 976041000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 14178903000 # number of overall MSHR uncacheable cycles +system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.591861 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.595769 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.593842 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.598727 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.590625 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.594472 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.741347 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.474723 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.655192 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.218452 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.238282 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.094352 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.184921 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.446368 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.264623 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.333977 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.063950 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.170992 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.393737 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.203848 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.218452 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.238282 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.094352 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.451557 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.446368 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.264623 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.333977 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.063950 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.266924 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.393737 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.292149 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.218452 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.238282 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.094352 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.451557 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.446368 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.264623 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.333977 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.063950 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.266924 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.393737 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.292149 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20782.672878 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20759.123136 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20770.697773 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20806.403659 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20800.429860 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20803.287207 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 83747.368221 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 76297.204102 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 82003.086666 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 80686.985597 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 82715.686275 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 73437.114077 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 81151.273568 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117720.308097 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 79963.235294 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 78832.450650 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 72948.231473 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 78166.887712 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111159.727256 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 97540.588835 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 80686.985597 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 82715.686275 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73437.114077 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 83193.673125 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117720.308097 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79963.235294 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 78832.450650 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72948.231473 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 77116.636438 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111159.727256 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 90723.447575 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 80686.985597 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 82715.686275 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73437.114077 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 83193.673125 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117720.308097 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79963.235294 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 78832.450650 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72948.231473 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 77116.636438 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111159.727256 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 90723.447575 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62367.331523 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 153783.741865 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 66118.279570 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 84684.936614 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 96859.005197 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 148672.360201 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 98824.053030 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141763.341646 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62367.331523 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 151230.657412 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 66118.279570 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 91698.703495 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 110147.934372 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 975380 # Transaction distribution -system.membus.trans_dist::ReadResp 975380 # Transaction distribution -system.membus.trans_dist::WriteReq 38492 # Transaction distribution -system.membus.trans_dist::WriteResp 38492 # Transaction distribution -system.membus.trans_dist::Writeback 1255244 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 671368 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 671368 # Transaction distribution -system.membus.trans_dist::UpgradeReq 435292 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 320448 # Transaction distribution -system.membus.trans_dist::UpgradeResp 117663 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 19 # Transaction distribution -system.membus.trans_dist::ReadExReq 151367 # Transaction distribution -system.membus.trans_dist::ReadExResp 133687 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122574 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 90631 # Transaction distribution +system.membus.trans_dist::ReadResp 933772 # Transaction distribution +system.membus.trans_dist::WriteReq 38095 # Transaction distribution +system.membus.trans_dist::WriteResp 38095 # Transaction distribution +system.membus.trans_dist::Writeback 1222852 # Transaction distribution +system.membus.trans_dist::CleanEvict 259291 # Transaction distribution +system.membus.trans_dist::UpgradeReq 429274 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 300804 # Transaction distribution +system.membus.trans_dist::UpgradeResp 113465 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 5 # Transaction distribution +system.membus.trans_dist::ReadExReq 664837 # Transaction distribution +system.membus.trans_dist::ReadExResp 644660 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 843141 # Transaction distribution +system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution +system.membus.trans_dist::InvalidateResp 106728 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122578 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26446 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5296349 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5445421 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335920 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 335920 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5781341 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155681 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24884 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5299387 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5446901 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342793 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 342793 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5789694 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155708 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52892 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 177552960 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 177762857 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14095872 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14095872 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 191858729 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 658635 # Total snoops (count) -system.membus.snoop_fanout::samples 3847839 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49768 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 169409152 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 169615952 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7274560 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7274560 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 176890512 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 639479 # Total snoops (count) +system.membus.snoop_fanout::samples 3957833 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3847839 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3957833 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3847839 # Request fanout histogram -system.membus.reqLayer0.occupancy 109654500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3957833 # Request fanout histogram +system.membus.reqLayer0.occupancy 109447997 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 33484 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 33984 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 21898998 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 20601500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 11397821385 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 8645644788 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 6506682845 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 8381282870 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 152058832 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 229327995 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -3106,45 +3169,46 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 5105910 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 5098639 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38492 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38492 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 2490573 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 937823 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 830969 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 486096 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 332772 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 818868 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 64 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 64 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 302211 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 302211 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8322623 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6766752 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 15089375 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 277489443 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 218349254 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 495838697 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1695482 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 9694113 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.011945 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.108639 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 90633 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 5042509 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38095 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38095 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 3695900 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1651242 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 481742 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 313276 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 795018 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 104 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 104 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1145784 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1145784 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 4959107 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 106728 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8783138 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7404481 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 16187619 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 270950615 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 216626041 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 487576656 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 3318184 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 13892424 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.121763 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.327012 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 9578315 98.81% 98.81% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 115798 1.19% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 12200843 87.82% 87.82% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 1691581 12.18% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 9694113 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 8435746901 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 13892424 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 8859040198 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2506500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2520000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4797228870 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 5187778836 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4287100444 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4493465928 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt index 505d3c407..df26aa07d 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt @@ -1,138 +1,138 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.610037 # Number of seconds simulated -sim_ticks 51610036853000 # Number of ticks simulated -final_tick 51610036853000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.694137 # Number of seconds simulated +sim_ticks 51694136923000 # Number of ticks simulated +final_tick 51694136923000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 188716 # Simulator instruction rate (inst/s) -host_op_rate 221745 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 10246213919 # Simulator tick rate (ticks/s) -host_mem_usage 724572 # Number of bytes of host memory used -host_seconds 5036.99 # Real time elapsed on the host -sim_insts 950561948 # Number of instructions simulated -sim_ops 1116924449 # Number of ops (including micro ops) simulated +host_inst_rate 185117 # Simulator instruction rate (inst/s) +host_op_rate 217521 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10090931944 # Simulator tick rate (ticks/s) +host_mem_usage 725160 # Number of bytes of host memory used +host_seconds 5122.83 # Real time elapsed on the host +sim_insts 948323287 # Number of instructions simulated +sim_ops 1114322939 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 410048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 340288 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 10352448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 67122824 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 411200 # Number of bytes read from this memory -system.physmem.bytes_read::total 78636808 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 10352448 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 10352448 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 95202624 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 407232 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 344384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 10254400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 100902664 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 404352 # Number of bytes read from this memory +system.physmem.bytes_read::total 112313032 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 10254400 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10254400 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 94405184 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 95223204 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 6407 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 5317 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 161757 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1048807 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6425 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1228713 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1487541 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 94425764 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 6363 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 5381 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 160225 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1576617 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6318 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1754904 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1475081 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1490114 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 7945 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 6593 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 200590 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1300577 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7967 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1523673 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 200590 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 200590 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1844653 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 399 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1845052 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1844653 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 7945 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 6593 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 200590 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1300976 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7967 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3368725 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1228713 # Number of read requests accepted -system.physmem.writeReqs 2143008 # Number of write requests accepted -system.physmem.readBursts 1228713 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 2143008 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 78600192 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 37440 # Total number of bytes read from write queue -system.physmem.bytesWritten 133928256 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 78636808 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 137008420 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 585 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 50360 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 39728 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 75722 # Per bank write bursts -system.physmem.perBankRdBursts::1 79954 # Per bank write bursts -system.physmem.perBankRdBursts::2 72878 # Per bank write bursts -system.physmem.perBankRdBursts::3 71278 # Per bank write bursts -system.physmem.perBankRdBursts::4 72651 # Per bank write bursts -system.physmem.perBankRdBursts::5 79829 # Per bank write bursts -system.physmem.perBankRdBursts::6 73600 # Per bank write bursts -system.physmem.perBankRdBursts::7 73320 # Per bank write bursts -system.physmem.perBankRdBursts::8 65239 # Per bank write bursts -system.physmem.perBankRdBursts::9 127420 # Per bank write bursts -system.physmem.perBankRdBursts::10 73665 # Per bank write bursts -system.physmem.perBankRdBursts::11 77478 # Per bank write bursts -system.physmem.perBankRdBursts::12 72459 # Per bank write bursts -system.physmem.perBankRdBursts::13 72712 # Per bank write bursts -system.physmem.perBankRdBursts::14 69098 # Per bank write bursts -system.physmem.perBankRdBursts::15 70825 # Per bank write bursts -system.physmem.perBankWrBursts::0 130775 # Per bank write bursts -system.physmem.perBankWrBursts::1 132563 # Per bank write bursts -system.physmem.perBankWrBursts::2 131683 # Per bank write bursts -system.physmem.perBankWrBursts::3 133448 # Per bank write bursts -system.physmem.perBankWrBursts::4 132375 # Per bank write bursts -system.physmem.perBankWrBursts::5 136941 # Per bank write bursts -system.physmem.perBankWrBursts::6 129100 # Per bank write bursts -system.physmem.perBankWrBursts::7 132855 # Per bank write bursts -system.physmem.perBankWrBursts::8 124239 # Per bank write bursts -system.physmem.perBankWrBursts::9 131924 # Per bank write bursts -system.physmem.perBankWrBursts::10 130753 # Per bank write bursts -system.physmem.perBankWrBursts::11 132768 # Per bank write bursts -system.physmem.perBankWrBursts::12 128150 # Per bank write bursts -system.physmem.perBankWrBursts::13 130180 # Per bank write bursts -system.physmem.perBankWrBursts::14 126529 # Per bank write bursts -system.physmem.perBankWrBursts::15 128346 # Per bank write bursts +system.physmem.num_writes::total 1477654 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 7878 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 6662 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 198367 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1951917 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7822 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2172645 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 198367 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 198367 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1826226 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1826624 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1826226 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 7878 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 6662 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 198367 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1952315 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7822 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3999270 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1754904 # Number of read requests accepted +system.physmem.writeReqs 1477654 # Number of write requests accepted +system.physmem.readBursts 1754904 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1477654 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 112259136 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 54720 # Total number of bytes read from write queue +system.physmem.bytesWritten 94423744 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 112313032 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 94425764 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 855 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2252 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 146151 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 109407 # Per bank write bursts +system.physmem.perBankRdBursts::1 112864 # Per bank write bursts +system.physmem.perBankRdBursts::2 109220 # Per bank write bursts +system.physmem.perBankRdBursts::3 104188 # Per bank write bursts +system.physmem.perBankRdBursts::4 106449 # Per bank write bursts +system.physmem.perBankRdBursts::5 113846 # Per bank write bursts +system.physmem.perBankRdBursts::6 104146 # Per bank write bursts +system.physmem.perBankRdBursts::7 106564 # Per bank write bursts +system.physmem.perBankRdBursts::8 99467 # Per bank write bursts +system.physmem.perBankRdBursts::9 160932 # Per bank write bursts +system.physmem.perBankRdBursts::10 104576 # Per bank write bursts +system.physmem.perBankRdBursts::11 109948 # Per bank write bursts +system.physmem.perBankRdBursts::12 102336 # Per bank write bursts +system.physmem.perBankRdBursts::13 105581 # Per bank write bursts +system.physmem.perBankRdBursts::14 99543 # Per bank write bursts +system.physmem.perBankRdBursts::15 104982 # Per bank write bursts +system.physmem.perBankWrBursts::0 93507 # Per bank write bursts +system.physmem.perBankWrBursts::1 95050 # Per bank write bursts +system.physmem.perBankWrBursts::2 93111 # Per bank write bursts +system.physmem.perBankWrBursts::3 91031 # Per bank write bursts +system.physmem.perBankWrBursts::4 92702 # Per bank write bursts +system.physmem.perBankWrBursts::5 96804 # Per bank write bursts +system.physmem.perBankWrBursts::6 89915 # Per bank write bursts +system.physmem.perBankWrBursts::7 93502 # Per bank write bursts +system.physmem.perBankWrBursts::8 87351 # Per bank write bursts +system.physmem.perBankWrBursts::9 94209 # Per bank write bursts +system.physmem.perBankWrBursts::10 90719 # Per bank write bursts +system.physmem.perBankWrBursts::11 94851 # Per bank write bursts +system.physmem.perBankWrBursts::12 89273 # Per bank write bursts +system.physmem.perBankWrBursts::13 92330 # Per bank write bursts +system.physmem.perBankWrBursts::14 88747 # Per bank write bursts +system.physmem.perBankWrBursts::15 92269 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 140 # Number of times write queue was full causing retry -system.physmem.totGap 51610035211500 # Total gap between requests +system.physmem.numWrRetry 31 # Number of times write queue was full causing retry +system.physmem.totGap 51694135218000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1228698 # Read request sizes (log2) +system.physmem.readPktSize::6 1754889 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 2140435 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1157126 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 64351 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 755 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 308 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 447 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 546 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 482 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 776 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 503 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1798 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 175 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 116 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 113 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 110 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 92 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 89 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 70 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 58 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1475081 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1420187 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 327570 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 933 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 327 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 464 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 482 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 515 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 534 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 776 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 878 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 379 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 167 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 176 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 124 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 118 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 95 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 72 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 46 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -159,168 +159,164 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 52200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 61876 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 103140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 107216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 115340 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 154284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 127380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 116704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 115742 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 109222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 108713 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 142144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 115995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 110189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 122630 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 110947 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 107019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 104847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 5989 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 5575 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 6143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 7595 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 8109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 7187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 6881 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 8026 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 6843 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 6405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 5844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 5760 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 4978 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 3912 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 3857 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 3012 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 2330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1631 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1002 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 404 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 434 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 339 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 312 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 733749 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 289.646732 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 167.469062 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 324.982397 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 301017 41.02% 41.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 179214 24.42% 65.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 65174 8.88% 74.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 36623 4.99% 79.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 25257 3.44% 82.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 17346 2.36% 85.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 13099 1.79% 86.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 11628 1.58% 88.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 84391 11.50% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 733749 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 100720 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 12.193388 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 124.138953 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 100718 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 100720 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 100720 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.776698 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.274786 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 17.101890 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 96977 96.28% 96.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 2012 2.00% 98.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 404 0.40% 98.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 303 0.30% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 157 0.16% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 153 0.15% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 320 0.32% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 134 0.13% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 20 0.02% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 11 0.01% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 66 0.07% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 35 0.03% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 14 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 5 0.00% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 1 0.00% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 7 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 6 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 7 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 11 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 8 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 12 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 21 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 5 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 5 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::400-415 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::416-431 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::432-447 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::464-479 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 5 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 5 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::560-575 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::688-703 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::720-735 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::736-751 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::912-927 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 100720 # Writes before turning the bus around for reads -system.physmem.totQLat 16983547454 # Total ticks spent queuing -system.physmem.totMemAccLat 40010947454 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 6140640000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13828.81 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 15753 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 18367 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 69542 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 87805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 88303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 88136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 87821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 90771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 91285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 93842 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 92895 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 93403 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 89996 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 90062 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 102154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 88485 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 90293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 86850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 661 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 753 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 576 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 442 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 503 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 417 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 362 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 82 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 688077 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 300.376987 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.587339 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 327.638975 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 270609 39.33% 39.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 164654 23.93% 63.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 63521 9.23% 72.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 36566 5.31% 77.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 27027 3.93% 81.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 18739 2.72% 84.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 14736 2.14% 86.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 13602 1.98% 88.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 78623 11.43% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 688077 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 86230 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 20.341007 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 270.950677 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 86227 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::24576-28671 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::73728-77823 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 86230 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 86230 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.109718 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.738195 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 5.845815 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 83739 97.11% 97.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 148 0.17% 97.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 433 0.50% 97.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 182 0.21% 98.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 327 0.38% 98.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 491 0.57% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 146 0.17% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 35 0.04% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 38 0.04% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 19 0.02% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 25 0.03% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 26 0.03% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 445 0.52% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 41 0.05% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 34 0.04% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 31 0.04% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 6 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 3 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 32 0.04% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 8 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 86230 # Writes before turning the bus around for reads +system.physmem.totQLat 26659687931 # Total ticks spent queuing +system.physmem.totMemAccLat 59548106681 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 8770245000 # Total ticks spent in databus transfers +system.physmem.avgQLat 15198.94 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32578.81 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.52 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.60 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.52 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.65 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 33948.94 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.17 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.83 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.17 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.83 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage -system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.54 # Average write queue length when enqueuing -system.physmem.readRowHits 948457 # Number of row buffer hits during reads -system.physmem.writeRowHits 1638549 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.23 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.30 # Row buffer hit rate for writes -system.physmem.avgGap 15306733.63 # Average gap between requests -system.physmem.pageHitRate 77.90 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2845387440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1552542750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4674001800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 6867115200 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3370916218800 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1311782988195 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29815330787250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34513969041435 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.745387 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49599639397461 # Time in different power states -system.physmem_0.memoryStateTime::REF 1723372300000 # Time in different power states +system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.61 # Average write queue length when enqueuing +system.physmem.readRowHits 1434287 # Number of row buffer hits during reads +system.physmem.writeRowHits 1107055 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.77 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.03 # Row buffer hit rate for writes +system.physmem.avgGap 15991711.59 # Average gap between requests +system.physmem.pageHitRate 78.69 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2644873560 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1443135375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6760088400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4831630560 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3376409683920 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1310236671105 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29867151449250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34569477532170 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.731116 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49685803332014 # Time in different power states +system.physmem_0.memoryStateTime::REF 1726180820000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 287019858539 # Time in different power states +system.physmem_0.memoryStateTime::ACT 282152299236 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2701755000 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1474171875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4905342000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 6693120720 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3370916218800 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1303897064130 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29822248264500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34512835937025 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.723432 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49611170347429 # Time in different power states -system.physmem_1.memoryStateTime::REF 1723372300000 # Time in different power states +system.physmem_1.actEnergy 2556988560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1395182250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 6921447000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4728773520 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3376409683920 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1305311169150 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29871472073250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34568795317650 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.717918 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49692977337193 # Time in different power states +system.physmem_1.memoryStateTime::REF 1726180820000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 275493728071 # Time in different power states +system.physmem_1.memoryStateTime::ACT 274978307807 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory @@ -344,15 +340,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 260902420 # Number of BP lookups -system.cpu.branchPred.condPredicted 182959992 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12222887 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 194114900 # Number of BTB lookups -system.cpu.branchPred.BTBHits 136429435 # Number of BTB hits +system.cpu.branchPred.lookups 260235992 # Number of BP lookups +system.cpu.branchPred.condPredicted 182594285 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12181539 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 193306639 # Number of BTB lookups +system.cpu.branchPred.BTBHits 136184729 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 70.282825 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 31730781 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2172348 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 70.450104 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 31573215 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2152291 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -383,61 +379,61 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 588227 # Table walker walks requested -system.cpu.dtb.walker.walksLong 588227 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 22315 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 191623 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 588227 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 588227 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 588227 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 213938 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 24858.035959 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 21008.300307 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 15796.225820 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 211313 98.77% 98.77% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 2233 1.04% 99.82% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 146 0.07% 99.89% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 117 0.05% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 91 0.04% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 23 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 8 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walks 586554 # Table walker walks requested +system.cpu.dtb.walker.walksLong 586554 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 22200 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 191198 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 586554 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 586554 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 586554 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 213398 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 26171.173113 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 22678.472578 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 15672.620914 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 210833 98.80% 98.80% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 2191 1.03% 99.82% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 145 0.07% 99.89% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 108 0.05% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 74 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 36 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 5 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::458752-524287 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 213938 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples -15748296 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 -15748296 100.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total -15748296 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 191624 89.57% 89.57% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 22315 10.43% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 213939 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 588227 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 213398 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples -58656296 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 -58656296 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total -58656296 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 191199 89.60% 89.60% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 22200 10.40% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 213399 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 586554 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 588227 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 213939 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 586554 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 213399 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 213939 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 802166 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 213399 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 799953 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 183548892 # DTB read hits -system.cpu.dtb.read_misses 485969 # DTB read misses -system.cpu.dtb.write_hits 162881584 # DTB write hits -system.cpu.dtb.write_misses 102258 # DTB write misses +system.cpu.dtb.read_hits 183104972 # DTB read hits +system.cpu.dtb.read_misses 484611 # DTB read misses +system.cpu.dtb.write_hits 162443368 # DTB write hits +system.cpu.dtb.write_misses 101943 # DTB write misses system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 47246 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_mva_asid 47231 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 1111 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 79791 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 811 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 15585 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 80156 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 829 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 15457 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 23526 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 184034861 # DTB read accesses -system.cpu.dtb.write_accesses 162983842 # DTB write accesses +system.cpu.dtb.perms_faults 23578 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 183589583 # DTB read accesses +system.cpu.dtb.write_accesses 162545311 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 346430476 # DTB hits -system.cpu.dtb.misses 588227 # DTB misses -system.cpu.dtb.accesses 347018703 # DTB accesses +system.cpu.dtb.hits 345548340 # DTB hits +system.cpu.dtb.misses 586554 # DTB misses +system.cpu.dtb.accesses 346134894 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -467,341 +463,345 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 136538 # Table walker walks requested -system.cpu.itb.walker.walksLong 136538 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1085 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 118818 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 136538 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 136538 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 136538 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 119903 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 27208.529278 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 23313.702861 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 17744.151968 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 116996 97.58% 97.58% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 2625 2.19% 99.76% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 168 0.14% 99.90% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 53 0.04% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 37 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 14 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 6 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 119903 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples -16365796 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 -16365796 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total -16365796 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 118818 99.10% 99.10% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1085 0.90% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 119903 # Table walker page sizes translated +system.cpu.itb.walker.walks 136663 # Table walker walks requested +system.cpu.itb.walker.walksLong 136663 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1080 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 119012 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 136663 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 136663 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 136663 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 120092 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 28563.884355 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 25001.850654 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 17459.523046 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-32767 59524 49.57% 49.57% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::32768-65535 57595 47.96% 97.52% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-98303 1126 0.94% 98.46% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::98304-131071 1581 1.32% 99.78% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-163839 30 0.02% 99.80% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::163840-196607 128 0.11% 99.91% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-229375 37 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::229376-262143 22 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-294911 13 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::294912-327679 15 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-360447 10 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::360448-393215 7 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::425984-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 120092 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples -59528796 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 -59528796 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total -59528796 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 119012 99.10% 99.10% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1080 0.90% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 120092 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 136538 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 136538 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 136663 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 136663 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 119903 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 119903 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 256441 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 454119408 # ITB inst hits -system.cpu.itb.inst_misses 136538 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 120092 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 120092 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 256755 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 453103030 # ITB inst hits +system.cpu.itb.inst_misses 136663 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 47246 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_mva_asid 47231 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 1111 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 57195 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 57609 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 369083 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 364302 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 454255946 # ITB inst accesses -system.cpu.itb.hits 454119408 # DTB hits -system.cpu.itb.misses 136538 # DTB misses -system.cpu.itb.accesses 454255946 # DTB accesses -system.cpu.numCycles 2495798541 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 453239693 # ITB inst accesses +system.cpu.itb.hits 453103030 # DTB hits +system.cpu.itb.misses 136663 # DTB misses +system.cpu.itb.accesses 453239693 # DTB accesses +system.cpu.numCycles 2508251480 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 950561948 # Number of instructions committed -system.cpu.committedOps 1116924449 # Number of ops (including micro ops) committed -system.cpu.discardedOps 97483728 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 7747 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 100725440428 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.625603 # CPI: cycles per instruction -system.cpu.ipc 0.380865 # IPC: instructions per cycle +system.cpu.committedInsts 948323287 # Number of instructions committed +system.cpu.committedOps 1114322939 # Number of ops (including micro ops) committed +system.cpu.discardedOps 97332960 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 7744 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 100881187078 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.644933 # CPI: cycles per instruction +system.cpu.ipc 0.378081 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16607 # number of quiesce instructions executed -system.cpu.tickCycles 1794634441 # Number of cycles that the object actually ticked -system.cpu.idleCycles 701164100 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 11128908 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.957332 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 330012577 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 11129420 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.652271 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 4320792250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.957332 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999917 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999917 # Average percentage of cache occupancy +system.cpu.kern.inst.quiesce 16604 # number of quiesce instructions executed +system.cpu.tickCycles 1790178903 # Number of cycles that the object actually ticked +system.cpu.idleCycles 718072577 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 11134622 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.957818 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 329114421 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 11135134 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.556395 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 4277412500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.957818 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999918 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999918 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 379 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 386 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 54 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1386837426 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1386837426 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 168701491 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 168701491 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 152033429 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 152033429 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 523995 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 523995 # number of SoftPFReq hits -system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 336687 # number of WriteInvalidateReq hits -system.cpu.dcache.WriteInvalidateReq_hits::total 336687 # number of WriteInvalidateReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4025252 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4025252 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 4342024 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 4342024 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 320734920 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 320734920 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 321258915 # number of overall hits -system.cpu.dcache.overall_hits::total 321258915 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 6599201 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 6599201 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4320372 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4320372 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1481368 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1481368 # number of SoftPFReq misses -system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1244671 # number of WriteInvalidateReq misses -system.cpu.dcache.WriteInvalidateReq_misses::total 1244671 # number of WriteInvalidateReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 318506 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 318506 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 10919573 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 10919573 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 12400941 # number of overall misses -system.cpu.dcache.overall_misses::total 12400941 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 107641538217 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 107641538217 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 155110738831 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 155110738831 # number of WriteReq miss cycles -system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 35571203201 # number of WriteInvalidateReq miss cycles -system.cpu.dcache.WriteInvalidateReq_miss_latency::total 35571203201 # number of WriteInvalidateReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4850646421 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 4850646421 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 82000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 82000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 262752277048 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 262752277048 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 262752277048 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 262752277048 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 175300692 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 175300692 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 156353801 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 156353801 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2005363 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2005363 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1581358 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::total 1581358 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4343758 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4343758 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 4342025 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 4342025 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 331654493 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 331654493 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 333659856 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 333659856 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037645 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.037645 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027632 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.027632 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.738703 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.738703 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.787090 # miss rate for WriteInvalidateReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.787090 # miss rate for WriteInvalidateReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.073325 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.073325 # miss rate for LoadLockedReq accesses +system.cpu.dcache.tags.tag_accesses 1383337751 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1383337751 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 168246441 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 168246441 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 151606594 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 151606594 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 524249 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 524249 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 336460 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 336460 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4018923 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4018923 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 4332342 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 4332342 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 319853035 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 319853035 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 320377284 # number of overall hits +system.cpu.dcache.overall_hits::total 320377284 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 6626426 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 6626426 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 4317891 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4317891 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1480828 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1480828 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1245336 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1245336 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 315150 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 315150 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 10944317 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 10944317 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 12425145 # number of overall misses +system.cpu.dcache.overall_misses::total 12425145 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 107226750500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 107226750500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 152543350000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 152543350000 # number of WriteReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 58512566000 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 58512566000 # number of WriteLineReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4781324500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 4781324500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 115500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 115500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 259770100500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 259770100500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 259770100500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 259770100500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 174872867 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 174872867 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 155924485 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 155924485 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2005077 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2005077 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::cpu.data 1581796 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 1581796 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4334073 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 4334073 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 4332344 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 4332344 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 330797352 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 330797352 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 332802429 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 332802429 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037893 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.037893 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027692 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.027692 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.738539 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.738539 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.787292 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.787292 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.072715 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.072715 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032925 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032925 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037166 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037166 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16311.298628 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16311.298628 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35902.172042 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35902.172042 # average WriteReq miss latency -system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 28578.799700 # average WriteInvalidateReq miss latency -system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 28578.799700 # average WriteInvalidateReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15229.372197 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15229.372197 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24062.504738 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24062.504738 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21188.091859 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21188.091859 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 4 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.033085 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.033085 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037335 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037335 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16181.686855 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16181.686855 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35328.207683 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35328.207683 # average WriteReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 46985.364592 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 46985.364592 # average WriteLineReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15171.583373 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15171.583373 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 57750 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 57750 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23735.615525 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23735.615525 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20906.806359 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20906.806359 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 8539693 # number of writebacks -system.cpu.dcache.writebacks::total 8539693 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 803144 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 803144 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1904565 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1904565 # number of WriteReq MSHR hits -system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.data 147 # number of WriteInvalidateReq MSHR hits -system.cpu.dcache.WriteInvalidateReq_mshr_hits::total 147 # number of WriteInvalidateReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 69655 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 69655 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2707709 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2707709 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2707709 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2707709 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5796057 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5796057 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2415807 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2415807 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1473891 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1473891 # number of SoftPFReq MSHR misses -system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data 1244524 # number of WriteInvalidateReq MSHR misses -system.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1244524 # number of WriteInvalidateReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 248851 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 248851 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 8211864 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 8211864 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9685755 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9685755 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33696 # number of ReadReq MSHR uncacheable -system.cpu.dcache.ReadReq_mshr_uncacheable::total 33696 # number of ReadReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33705 # number of WriteReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::total 33705 # number of WriteReq MSHR uncacheable -system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67401 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 67401 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 85294782786 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 85294782786 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 79878018296 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 79878018296 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 23078167080 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 23078167080 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 33700697799 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 33700697799 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3279664007 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3279664007 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 80500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 80500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 165172801082 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 165172801082 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 188250968162 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 188250968162 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5750649000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5750649000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5615353750 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5615353750 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11366002750 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 11366002750 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.033064 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.033064 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015451 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015451 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.734975 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.734975 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.786997 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.786997 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057289 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057289 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.writebacks::writebacks 8552025 # number of writebacks +system.cpu.dcache.writebacks::total 8552025 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 818755 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 818755 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1904630 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1904630 # number of WriteReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 150 # number of WriteLineReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::total 150 # number of WriteLineReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 70014 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 70014 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2723385 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2723385 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2723385 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2723385 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5807671 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5807671 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2413261 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2413261 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1473332 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1473332 # number of SoftPFReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1245186 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 1245186 # number of WriteLineReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 245136 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 245136 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 8220932 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 8220932 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9694264 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9694264 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33699 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadReq_mshr_uncacheable::total 33699 # number of ReadReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33707 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 33707 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67406 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 67406 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 87900213000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 87900213000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 80008628500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 80008628500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 23654166000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 23654166000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 57263274500 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 57263274500 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3335164500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3335164500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 113500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 113500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 167908841500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 167908841500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191563007500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 191563007500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5830486500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5830486500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5692032500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5692032500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11522519000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 11522519000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.033211 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.033211 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015477 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015477 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.734801 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.734801 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787198 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787198 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.056560 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.056560 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024760 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.024760 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029029 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.029029 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14716.001376 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14716.001376 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33064.735012 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33064.735012 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15657.987653 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15657.987653 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 27079.186740 # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 27079.186740 # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13179.227759 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13179.227759 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 80500 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 80500 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20113.923110 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20113.923110 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19435.858966 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19435.858966 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 170662.660256 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 170662.660256 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 166602.989171 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 166602.989171 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 168632.553671 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 168632.553671 # average overall mshr uncacheable latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024852 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.024852 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029129 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.029129 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15135.191542 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15135.191542 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33153.740312 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33153.740312 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16054.878330 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16054.878330 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 45987.727536 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 45987.727536 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13605.363961 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13605.363961 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 56750 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 56750 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20424.550586 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20424.550586 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19760.448808 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19760.448808 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173016.602867 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173016.602867 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 168867.965111 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 168867.965111 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 170942.037801 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 170942.037801 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 24596775 # number of replacements -system.cpu.icache.tags.tagsinuse 511.926998 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 429140951 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 24597287 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 17.446678 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 22329177250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.926998 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999857 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999857 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 24460747 # number of replacements +system.cpu.icache.tags.tagsinuse 511.918526 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 428265010 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 24461259 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 17.507889 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 26893649500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.918526 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999841 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999841 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 103 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 284 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 118 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 478335544 # Number of tag accesses -system.cpu.icache.tags.data_accesses 478335544 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 429140951 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 429140951 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 429140951 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 429140951 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 429140951 # number of overall hits -system.cpu.icache.overall_hits::total 429140951 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 24597297 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 24597297 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 24597297 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 24597297 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 24597297 # number of overall misses -system.cpu.icache.overall_misses::total 24597297 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 327843901768 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 327843901768 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 327843901768 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 327843901768 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 327843901768 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 327843901768 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 453738248 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 453738248 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 453738248 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 453738248 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 453738248 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 453738248 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.054210 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.054210 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.054210 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.054210 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.054210 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.054210 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13328.452381 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13328.452381 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13328.452381 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13328.452381 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13328.452381 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13328.452381 # average overall miss latency +system.cpu.icache.tags.tag_accesses 477187547 # Number of tag accesses +system.cpu.icache.tags.data_accesses 477187547 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 428265010 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 428265010 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 428265010 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 428265010 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 428265010 # number of overall hits +system.cpu.icache.overall_hits::total 428265010 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 24461269 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 24461269 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 24461269 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 24461269 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 24461269 # number of overall misses +system.cpu.icache.overall_misses::total 24461269 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 325762917500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 325762917500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 325762917500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 325762917500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 325762917500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 325762917500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 452726279 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 452726279 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 452726279 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 452726279 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 452726279 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 452726279 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.054031 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.054031 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.054031 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.054031 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.054031 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.054031 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13317.498675 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13317.498675 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13317.498675 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13317.498675 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13317.498675 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13317.498675 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -810,212 +810,225 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24597297 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 24597297 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 24597297 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 24597297 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 24597297 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 24597297 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 52294 # number of ReadReq MSHR uncacheable -system.cpu.icache.ReadReq_mshr_uncacheable::total 52294 # number of ReadReq MSHR uncacheable -system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 52294 # number of overall MSHR uncacheable misses -system.cpu.icache.overall_mshr_uncacheable_misses::total 52294 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 290898201664 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 290898201664 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 290898201664 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 290898201664 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 290898201664 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 290898201664 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 4024065500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 4024065500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 4024065500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 4024065500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.054210 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.054210 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.054210 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.054210 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.054210 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.054210 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11826.429614 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11826.429614 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11826.429614 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11826.429614 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11826.429614 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11826.429614 # average overall mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 76950.806976 # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 76950.806976 # average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 76950.806976 # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 76950.806976 # average overall mshr uncacheable latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24461269 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 24461269 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 24461269 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 24461269 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 24461269 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 24461269 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 52295 # number of ReadReq MSHR uncacheable +system.cpu.icache.ReadReq_mshr_uncacheable::total 52295 # number of ReadReq MSHR uncacheable +system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 52295 # number of overall MSHR uncacheable misses +system.cpu.icache.overall_mshr_uncacheable_misses::total 52295 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 301301649500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 301301649500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 301301649500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 301301649500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 301301649500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 301301649500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 4042938500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 4042938500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 4042938500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 4042938500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.054031 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.054031 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.054031 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.054031 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.054031 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.054031 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12317.498716 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12317.498716 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12317.498716 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12317.498716 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12317.498716 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12317.498716 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 77310.230424 # average ReadReq mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 77310.230424 # average ReadReq mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 77310.230424 # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 77310.230424 # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1624472 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65307.335302 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 40176051 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1687699 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 23.805223 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 6393601000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 36145.263997 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 333.648075 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 422.733439 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 8142.717924 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 20262.971868 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.551533 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.005091 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006450 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124248 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.309188 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996511 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 253 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 62974 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 253 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 498 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2440 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5584 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54389 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003860 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.960907 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 369553553 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 369553553 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 980236 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 284775 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 24487803 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 7183333 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 32936147 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 8539693 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 8539693 # number of Writeback hits -system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data 698094 # number of WriteInvalidateReq hits -system.cpu.l2cache.WriteInvalidateReq_hits::total 698094 # number of WriteInvalidateReq hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 10791 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 10791 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1651497 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1651497 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 980236 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 284775 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 24487803 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 8834830 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 34587644 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 980236 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 284775 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 24487803 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 8834830 # number of overall hits -system.cpu.l2cache.overall_hits::total 34587644 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6407 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5317 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 109491 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 335212 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 456427 # number of ReadReq misses -system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data 546430 # number of WriteInvalidateReq misses -system.cpu.l2cache.WriteInvalidateReq_misses::total 546430 # number of WriteInvalidateReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 38901 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 38901 # number of UpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 714872 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 714872 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 6407 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 5317 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 109491 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1050084 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1171299 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 6407 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 5317 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 109491 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1050084 # number of overall misses -system.cpu.l2cache.overall_misses::total 1171299 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 560042000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 465198251 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 8958985804 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 28447834598 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 38432060653 # number of ReadReq miss cycles -system.cpu.l2cache.WriteInvalidateReq_miss_latency::cpu.data 6247800 # number of WriteInvalidateReq miss cycles -system.cpu.l2cache.WriteInvalidateReq_miss_latency::total 6247800 # number of WriteInvalidateReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 584783300 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 584783300 # number of UpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 79500 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::total 79500 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 58773696620 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 58773696620 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 560042000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 465198251 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 8958985804 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 87221531218 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 97205757273 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 560042000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 465198251 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 8958985804 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 87221531218 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 97205757273 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 986643 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 290092 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 24597294 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7518545 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 33392574 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 8539693 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 8539693 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data 1244524 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.l2cache.WriteInvalidateReq_accesses::total 1244524 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 49692 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 49692 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2366369 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2366369 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 986643 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 290092 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 24597294 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9884914 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 35758943 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 986643 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 290092 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 24597294 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9884914 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 35758943 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.006494 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.018329 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.004451 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.044585 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.013669 # miss rate for ReadReq accesses -system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data 0.439067 # miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.439067 # miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.782842 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.782842 # miss rate for UpgradeReq accesses +system.cpu.l2cache.tags.replacements 1604829 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65266.156442 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 67107084 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1667914 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 40.234139 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 24502559000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 35881.888844 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 344.047128 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 429.269400 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 8228.433015 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 20382.518055 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.547514 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.005250 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006550 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.125556 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.311013 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.995883 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 276 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 62809 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 275 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 504 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2442 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5503 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54305 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004211 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.958389 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 585371330 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 585371330 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 972902 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 283103 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1256005 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 8552025 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 8552025 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 10723 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 10723 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1658365 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1658365 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24353307 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 24353307 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7197008 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 7197008 # number of ReadSharedReq hits +system.cpu.l2cache.InvalidateReq_hits::cpu.data 701735 # number of InvalidateReq hits +system.cpu.l2cache.InvalidateReq_hits::total 701735 # number of InvalidateReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 972902 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 283103 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 24353307 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 8855373 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 34464685 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 972902 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 283103 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 24353307 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 8855373 # number of overall hits +system.cpu.l2cache.overall_hits::total 34464685 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6363 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5381 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 11744 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 38680 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 38680 # number of UpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 705767 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 705767 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 107959 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 107959 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 328857 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 328857 # number of ReadSharedReq misses +system.cpu.l2cache.InvalidateReq_misses::cpu.data 543451 # number of InvalidateReq misses +system.cpu.l2cache.InvalidateReq_misses::total 543451 # number of InvalidateReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 6363 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 5381 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 107959 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1034624 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1154327 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 6363 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 5381 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 107959 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1034624 # number of overall misses +system.cpu.l2cache.overall_misses::total 1154327 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 554201500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 467153500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1021355000 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 576538000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 576538000 # number of UpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 110500 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::total 110500 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 57650400000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 57650400000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 8792604500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 8792604500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 27746254000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 27746254000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 47759810000 # number of InvalidateReq miss cycles +system.cpu.l2cache.InvalidateReq_miss_latency::total 47759810000 # number of InvalidateReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 554201500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 467153500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 8792604500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 85396654000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 95210613500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 554201500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 467153500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 8792604500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 85396654000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 95210613500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 979265 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 288484 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1267749 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 8552025 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 8552025 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 49403 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 49403 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2364132 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2364132 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 24461266 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 24461266 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7525865 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 7525865 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1245186 # number of InvalidateReq accesses(hits+misses) +system.cpu.l2cache.InvalidateReq_accesses::total 1245186 # number of InvalidateReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 979265 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 288484 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 24461266 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9889997 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 35619012 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 979265 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 288484 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 24461266 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9889997 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 35619012 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.006498 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.018653 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.009264 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.782948 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.782948 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.302097 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.302097 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.006494 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.018329 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004451 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.106231 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.032755 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.006494 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.018329 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004451 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.106231 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.032755 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 87410.956766 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 87492.618206 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81823.947210 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 84865.203507 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 84201.987729 # average ReadReq miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::cpu.data 11.433852 # average WriteInvalidateReq miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::total 11.433852 # average WriteInvalidateReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15032.603275 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15032.603275 # average UpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500 # average SCUpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82215.692627 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82215.692627 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 87410.956766 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 87492.618206 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81823.947210 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83061.480051 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 82989.703972 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 87410.956766 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 87492.618206 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81823.947210 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83061.480051 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 82989.703972 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.298531 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.298531 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.004413 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.004413 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043697 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043697 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.436442 # miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::total 0.436442 # miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.006498 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.018653 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004413 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.104613 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.032408 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.006498 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.018653 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004413 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.104613 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.032408 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 87097.516895 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 86815.368891 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 86968.239101 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14905.325750 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14905.325750 # average UpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 55250 # average SCUpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 55250 # average SCUpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81684.748649 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81684.748649 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81443.923156 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81443.923156 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84371.790778 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84371.790778 # average ReadSharedReq miss latency +system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 87882.458584 # average InvalidateReq miss latency +system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 87882.458584 # average InvalidateReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 87097.516895 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 86815.368891 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81443.923156 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82538.829565 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 82481.492246 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 87097.516895 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 86815.368891 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81443.923156 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82538.829565 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 82481.492246 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1024,185 +1037,200 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1380910 # number of writebacks -system.cpu.l2cache.writebacks::total 1380910 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 21 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 23 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits +system.cpu.l2cache.writebacks::writebacks 1368450 # number of writebacks +system.cpu.l2cache.writebacks::total 1368450 # number of writebacks +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 3 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 21 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 21 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 23 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 24 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 23 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 6407 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5317 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 109489 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 335191 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 456404 # number of ReadReq MSHR misses -system.cpu.l2cache.WriteInvalidateReq_mshr_misses::cpu.data 546430 # number of WriteInvalidateReq MSHR misses -system.cpu.l2cache.WriteInvalidateReq_mshr_misses::total 546430 # number of WriteInvalidateReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 38901 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 38901 # number of UpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 714872 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 714872 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 6407 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5317 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 109489 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1050063 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1171276 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 6407 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5317 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 109489 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1050063 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1171276 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 52294 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33696 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.ReadReq_mshr_uncacheable::total 85990 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33705 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33705 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 52294 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67401 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::total 119695 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 479479000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 398285251 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 7586646696 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 24249187152 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 32713598099 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data 18411194701 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total 18411194701 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 691147894 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 691147894 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 67500 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 67500 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 49837354880 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 49837354880 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 479479000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 398285251 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7586646696 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 74086542032 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 82550952979 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 479479000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 398285251 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7586646696 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 74086542032 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 82550952979 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 3108920000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5278320250 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 8387240250 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5176274500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5176274500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3108920000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10454594750 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 13563514750 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006494 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.018329 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.004451 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.044582 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013668 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.439067 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.439067 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.782842 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.782842 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.overall_mshr_hits::total 24 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 6363 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5381 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 11744 # number of ReadReq MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1115 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 1115 # number of CleanEvict MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 38680 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 38680 # number of UpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 705767 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 705767 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 107956 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 107956 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 328836 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 328836 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 543451 # number of InvalidateReq MSHR misses +system.cpu.l2cache.InvalidateReq_mshr_misses::total 543451 # number of InvalidateReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 6363 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5381 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 107956 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1034603 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1154303 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 6363 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5381 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 107956 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1034603 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1154303 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 52295 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33699 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::total 85994 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33707 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33707 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 52295 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67406 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 119701 # number of overall MSHR uncacheable misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 490571500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 413343500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 903915000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 803162500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 803162500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 90500 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 90500 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 50592730000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 50592730000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 7712869000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 7712869000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 24456668500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 24456668500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 42325300000 # number of InvalidateReq MSHR miss cycles +system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 42325300000 # number of InvalidateReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 490571500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 413343500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7712869000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 75049398500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 83666182500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 490571500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 413343500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7712869000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 75049398500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 83666182500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 3232365500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5409182000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 8641547500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5303781000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5303781000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3232365500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10712963000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 13945328500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006498 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.018653 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.009264 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.782948 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.782948 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.302097 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.302097 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006494 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.018329 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004451 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.106229 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.032755 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006494 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.018329 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004451 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.106229 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.032755 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 74836.741064 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 74907.889976 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69291.405493 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72344.386192 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71676.843540 # average ReadReq mshr miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 33693.601561 # average WriteInvalidateReq mshr miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 33693.601561 # average WriteInvalidateReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17766.841315 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17766.841315 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 67500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 67500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69715.074699 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69715.074699 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 74836.741064 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 74907.889976 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69291.405493 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70554.378196 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70479.505240 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 74836.741064 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 74907.889976 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69291.405493 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70554.378196 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70479.505240 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 59450.797415 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 156645.306565 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 97537.390976 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 153575.864115 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 153575.864115 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 59450.797415 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 155110.380410 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 113317.304399 # average overall mshr uncacheable latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.298531 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.298531 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004413 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004413 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.043694 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043694 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.436442 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.436442 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006498 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.018653 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004413 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.104611 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.032407 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006498 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.018653 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004413 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.104611 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.032407 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 77097.516895 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 76815.368891 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 76968.239101 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20764.283868 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20764.283868 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 45250 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 45250 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71684.748649 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71684.748649 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71444.560747 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71444.560747 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74373.452116 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74373.452116 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 77882.458584 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 77882.458584 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 77097.516895 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 76815.368891 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71444.560747 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72539.320396 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72481.993463 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 77097.516895 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 76815.368891 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71444.560747 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72539.320396 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72481.993463 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 61810.220862 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160514.614677 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 100490.121404 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 157349.541638 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157349.541638 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 61810.220862 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 158931.890336 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 116501.353372 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 33924038 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 33915953 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 33705 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 33705 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 8539693 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1351286 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1244524 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 49695 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 49696 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2366369 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2366369 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 49299178 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 31033537 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 698041 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2292039 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 83322795 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1577573568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1259064522 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2320736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7893144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2846851970 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 553019 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 46264787 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.039533 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.194859 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadReq 1796538 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 33784448 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33707 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33707 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 10027137 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 27284097 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 49406 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 49408 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2364132 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2364132 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 24461269 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7534742 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1351850 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1245186 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 73484098 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 33638682 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 696808 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2281485 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 110101073 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1568867840 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1180529566 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2307872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7834120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2759539398 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2279468 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 74907361 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.047344 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.212374 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 44435816 96.05% 96.05% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 1828971 3.95% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 71360927 95.27% 95.27% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 3546434 4.73% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 46264787 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 32875768488 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 74907361 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 45104615497 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 1167000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 37011580552 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 36773946781 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 15738706286 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 15533347490 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 408640707 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 408345956 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1306185489 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1302236467 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40309 # Transaction distribution -system.iobus.trans_dist::ReadResp 40309 # Transaction distribution +system.iobus.trans_dist::ReadReq 40325 # Transaction distribution +system.iobus.trans_dist::ReadResp 40325 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution -system.iobus.trans_dist::WriteResp 29907 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution +system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -1219,11 +1247,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230976 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230976 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231008 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231008 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353760 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353792 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1240,11 +1268,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334336 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334336 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334464 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334464 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7492384 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) @@ -1273,211 +1301,213 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 606954435 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 568973549 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 148397760 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147768000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 174500 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115470 # number of replacements -system.iocache.tags.tagsinuse 10.439534 # Cycle average of tags in use +system.iocache.tags.replacements 115486 # number of replacements +system.iocache.tags.tagsinuse 10.447136 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115486 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115502 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13142420796000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.524742 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.914791 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.220296 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.432174 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.652471 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13147036427000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.519010 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.928125 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.219938 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.433008 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.652946 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039749 # Number of tag accesses -system.iocache.tags.data_accesses 1039749 # Number of data accesses +system.iocache.tags.tag_accesses 1039893 # Number of tag accesses +system.iocache.tags.data_accesses 1039893 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8824 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8861 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8840 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8877 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8824 # number of demand (read+write) misses -system.iocache.demand_misses::total 8864 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8840 # number of demand (read+write) misses +system.iocache.demand_misses::total 8880 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8824 # number of overall misses -system.iocache.overall_misses::total 8864 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5072000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1602204582 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1607276582 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::realview.ethernet 352500 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 352500 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19806517093 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 19806517093 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5424500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1602204582 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1607629082 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5424500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1602204582 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1607629082 # number of overall miss cycles +system.iocache.overall_misses::realview.ide 8840 # number of overall misses +system.iocache.overall_misses::total 8880 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5069000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1592056146 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1597125146 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12612249403 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12612249403 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5420000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1592056146 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1597476146 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5420000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1592056146 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1597476146 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8824 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8861 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8840 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8877 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8824 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8864 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8840 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8880 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8824 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8864 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8840 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8880 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 181573.502040 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 181387.719445 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117500 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 117500 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 185690.740015 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 185690.740015 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 181573.502040 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 181366.096796 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 181573.502040 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 181366.096796 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 109809 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137000 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 180096.849095 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 179917.218204 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118242.794223 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118242.794223 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135500 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 180096.849095 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 179895.962387 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135500 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 180096.849095 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 179895.962387 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 29944 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 16154 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3370 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.797635 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.885460 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8824 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8861 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8840 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8877 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8824 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8864 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8840 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8880 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8824 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8864 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3142000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1142260060 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1145402060 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 193500 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 193500 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14259947135 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14259947135 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3335500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1142260060 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1145595560 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3335500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1142260060 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1145595560 # number of overall MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8840 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8880 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1150056146 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1153275146 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7279049403 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7279049403 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3420000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1150056146 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1153476146 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3420000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1150056146 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1153476146 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 84918.918919 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 129449.236174 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 129263.295339 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 64500 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 64500 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133690.346649 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133690.346649 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 129449.236174 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 129241.376354 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 129449.236174 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 129241.376354 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87000 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 130096.849095 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 129917.218204 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68242.794223 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68242.794223 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 130096.849095 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 129895.962387 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 130096.849095 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 129895.962387 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 551255 # Transaction distribution -system.membus.trans_dist::ReadResp 551255 # Transaction distribution -system.membus.trans_dist::WriteReq 33705 # Transaction distribution -system.membus.trans_dist::WriteResp 33705 # Transaction distribution -system.membus.trans_dist::Writeback 1487541 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 652894 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 652894 # Transaction distribution -system.membus.trans_dist::UpgradeReq 39734 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 39735 # Transaction distribution -system.membus.trans_dist::ReadExReq 714242 # Transaction distribution -system.membus.trans_dist::ReadExResp 714242 # Transaction distribution +system.membus.trans_dist::ReadReq 85994 # Transaction distribution +system.membus.trans_dist::ReadResp 543407 # Transaction distribution +system.membus.trans_dist::WriteReq 33707 # Transaction distribution +system.membus.trans_dist::WriteResp 33707 # Transaction distribution +system.membus.trans_dist::Writeback 1475081 # Transaction distribution +system.membus.trans_dist::CleanEvict 242486 # Transaction distribution +system.membus.trans_dist::UpgradeReq 39492 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 39494 # Transaction distribution +system.membus.trans_dist::ReadExReq 1248409 # Transaction distribution +system.membus.trans_dist::ReadExResp 1248409 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 457413 # Transaction distribution +system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution +system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6912 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5003208 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5132856 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335248 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 335248 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5468104 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6922 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5186779 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5316437 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341268 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 341268 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5657705 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13824 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 201583148 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 201753546 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14062080 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14062080 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 215815626 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3099 # Total snoops (count) -system.membus.snoop_fanout::samples 3479513 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13844 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 199510060 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 199680478 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7228736 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7228736 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 206909214 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3224 # Total snoops (count) +system.membus.snoop_fanout::samples 3692024 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3479513 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3692024 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3479513 # Request fanout histogram -system.membus.reqLayer0.occupancy 102597500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3692024 # Request fanout histogram +system.membus.reqLayer0.occupancy 102515000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 19828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5574500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5516000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 12409067173 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 9935800091 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 7217145927 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 9380119144 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 151545740 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 228946369 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -1488,11 +1518,11 @@ system.realview.ethernet.descDMAReads 0 # Nu system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) +system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s) system.realview.ethernet.totPackets 3 # Total Packets system.realview.ethernet.totBytes 966 # Total Bytes system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s) system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt index c76990264..2b80b1dcb 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt @@ -1,141 +1,141 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.320469 # Number of seconds simulated -sim_ticks 51320468905000 # Number of ticks simulated -final_tick 51320468905000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.323721 # Number of seconds simulated +sim_ticks 51323721423000 # Number of ticks simulated +final_tick 51323721423000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 81731 # Simulator instruction rate (inst/s) -host_op_rate 96032 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4902851121 # Simulator tick rate (ticks/s) -host_mem_usage 723872 # Number of bytes of host memory used -host_seconds 10467.47 # Real time elapsed on the host -sim_insts 855512158 # Number of instructions simulated -sim_ops 1005211605 # Number of ops (including micro ops) simulated +host_inst_rate 78661 # Simulator instruction rate (inst/s) +host_op_rate 92428 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4731079623 # Simulator tick rate (ticks/s) +host_mem_usage 729012 # Number of bytes of host memory used +host_seconds 10848.21 # Real time elapsed on the host +sim_insts 853325819 # Number of instructions simulated +sim_ops 1002674190 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 202624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 193280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5755680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 42629000 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 415488 # Number of bytes read from this memory -system.physmem.bytes_read::total 49196072 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5755680 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5755680 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 69369152 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 203200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 189632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5727200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 73778504 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 419776 # Number of bytes read from this memory +system.physmem.bytes_read::total 80318312 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5727200 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5727200 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 68723904 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 69389732 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 3166 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 3020 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 105885 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 666091 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6492 # Number of read requests responded to by this memory -system.physmem.num_reads::total 784654 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1083893 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 68744484 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 3175 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2963 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 105440 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1152802 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6559 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1270939 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1073811 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1086466 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 3948 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 3766 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 112152 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 830643 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8096 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 958605 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 112152 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 112152 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1351686 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1076384 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 3959 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 3695 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 111590 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1437513 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8179 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1564935 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 111590 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 111590 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1339028 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1352087 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1351686 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 3948 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 3766 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 112152 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 831044 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8096 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2310692 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 784654 # Number of read requests accepted -system.physmem.writeReqs 1688539 # Number of write requests accepted -system.physmem.readBursts 784654 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1688539 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 50184064 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 33792 # Total number of bytes read from write queue -system.physmem.bytesWritten 104909952 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 49196072 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 107922404 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 528 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 49293 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 35218 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 46664 # Per bank write bursts -system.physmem.perBankRdBursts::1 51485 # Per bank write bursts -system.physmem.perBankRdBursts::2 48018 # Per bank write bursts -system.physmem.perBankRdBursts::3 46409 # Per bank write bursts -system.physmem.perBankRdBursts::4 44064 # Per bank write bursts -system.physmem.perBankRdBursts::5 51949 # Per bank write bursts -system.physmem.perBankRdBursts::6 45895 # Per bank write bursts -system.physmem.perBankRdBursts::7 48923 # Per bank write bursts -system.physmem.perBankRdBursts::8 45299 # Per bank write bursts -system.physmem.perBankRdBursts::9 70789 # Per bank write bursts -system.physmem.perBankRdBursts::10 48156 # Per bank write bursts -system.physmem.perBankRdBursts::11 46739 # Per bank write bursts -system.physmem.perBankRdBursts::12 48771 # Per bank write bursts -system.physmem.perBankRdBursts::13 48997 # Per bank write bursts -system.physmem.perBankRdBursts::14 45133 # Per bank write bursts -system.physmem.perBankRdBursts::15 46835 # Per bank write bursts -system.physmem.perBankWrBursts::0 99610 # Per bank write bursts -system.physmem.perBankWrBursts::1 104326 # Per bank write bursts -system.physmem.perBankWrBursts::2 103481 # Per bank write bursts -system.physmem.perBankWrBursts::3 102430 # Per bank write bursts -system.physmem.perBankWrBursts::4 101747 # Per bank write bursts -system.physmem.perBankWrBursts::5 104971 # Per bank write bursts -system.physmem.perBankWrBursts::6 100056 # Per bank write bursts -system.physmem.perBankWrBursts::7 103888 # Per bank write bursts -system.physmem.perBankWrBursts::8 99840 # Per bank write bursts -system.physmem.perBankWrBursts::9 106110 # Per bank write bursts -system.physmem.perBankWrBursts::10 102643 # Per bank write bursts -system.physmem.perBankWrBursts::11 100858 # Per bank write bursts -system.physmem.perBankWrBursts::12 103355 # Per bank write bursts -system.physmem.perBankWrBursts::13 103593 # Per bank write bursts -system.physmem.perBankWrBursts::14 100350 # Per bank write bursts -system.physmem.perBankWrBursts::15 101960 # Per bank write bursts +system.physmem.bw_write::total 1339429 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1339028 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 3959 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 3695 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 111590 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1437914 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8179 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2904365 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1270939 # Number of read requests accepted +system.physmem.writeReqs 1076384 # Number of write requests accepted +system.physmem.readBursts 1270939 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1076384 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 81299584 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 40512 # Total number of bytes read from write queue +system.physmem.bytesWritten 68742976 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 80318312 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 68744484 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 633 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 142017 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 76590 # Per bank write bursts +system.physmem.perBankRdBursts::1 80112 # Per bank write bursts +system.physmem.perBankRdBursts::2 82312 # Per bank write bursts +system.physmem.perBankRdBursts::3 76894 # Per bank write bursts +system.physmem.perBankRdBursts::4 75148 # Per bank write bursts +system.physmem.perBankRdBursts::5 84486 # Per bank write bursts +system.physmem.perBankRdBursts::6 75307 # Per bank write bursts +system.physmem.perBankRdBursts::7 76047 # Per bank write bursts +system.physmem.perBankRdBursts::8 76921 # Per bank write bursts +system.physmem.perBankRdBursts::9 104197 # Per bank write bursts +system.physmem.perBankRdBursts::10 75653 # Per bank write bursts +system.physmem.perBankRdBursts::11 81028 # Per bank write bursts +system.physmem.perBankRdBursts::12 74845 # Per bank write bursts +system.physmem.perBankRdBursts::13 77383 # Per bank write bursts +system.physmem.perBankRdBursts::14 76622 # Per bank write bursts +system.physmem.perBankRdBursts::15 76761 # Per bank write bursts +system.physmem.perBankWrBursts::0 64108 # Per bank write bursts +system.physmem.perBankWrBursts::1 67910 # Per bank write bursts +system.physmem.perBankWrBursts::2 69982 # Per bank write bursts +system.physmem.perBankWrBursts::3 67432 # Per bank write bursts +system.physmem.perBankWrBursts::4 65959 # Per bank write bursts +system.physmem.perBankWrBursts::5 70786 # Per bank write bursts +system.physmem.perBankWrBursts::6 64733 # Per bank write bursts +system.physmem.perBankWrBursts::7 66187 # Per bank write bursts +system.physmem.perBankWrBursts::8 67287 # Per bank write bursts +system.physmem.perBankWrBursts::9 71812 # Per bank write bursts +system.physmem.perBankWrBursts::10 65064 # Per bank write bursts +system.physmem.perBankWrBursts::11 69201 # Per bank write bursts +system.physmem.perBankWrBursts::12 65082 # Per bank write bursts +system.physmem.perBankWrBursts::13 66370 # Per bank write bursts +system.physmem.perBankWrBursts::14 66024 # Per bank write bursts +system.physmem.perBankWrBursts::15 66172 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 560 # Number of times write queue was full causing retry -system.physmem.totGap 51320467654000 # Total gap between requests +system.physmem.numWrRetry 12 # Number of times write queue was full causing retry +system.physmem.totGap 51323720227500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 21272 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 763369 # Read request sizes (log2) +system.physmem.readPktSize::6 1249654 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1685966 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 521104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 214865 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 29991 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 12339 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 553 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 577 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 468 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 726 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 459 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1858 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 231 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 131 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 121 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 109 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 81 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 65 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1073811 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 646219 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 339232 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 151287 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 128129 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 684 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 489 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 502 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 533 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 812 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 936 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 392 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 192 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 135 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 119 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 118 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 100 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 87 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 63 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -159,160 +159,164 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 25954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 62903 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 63057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 90168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 80361 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 95410 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 92759 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 101527 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 92557 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 106064 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 84728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 110064 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 83833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 78687 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 89131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 74275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 70833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 66282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 8883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 7376 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 8392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 9232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 9334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 8685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 9103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 9266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 8544 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 8245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 7856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 7810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 7132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 5765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 6644 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 5091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 4890 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 3473 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 3916 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 2921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 3295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 2570 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 3011 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 2474 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 3139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 2181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 2765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 1862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 4424 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 820 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 1539 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 512637 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 302.540847 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 171.812512 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 339.509823 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 207576 40.49% 40.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 124268 24.24% 64.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 44401 8.66% 73.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 23774 4.64% 78.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 16232 3.17% 81.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 10193 1.99% 83.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8192 1.60% 84.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 7548 1.47% 86.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 70453 13.74% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 512637 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 56080 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 13.981651 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 75.084718 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 56073 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 5 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 56080 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 56080 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 29.229993 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 22.064414 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 40.823681 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-31 46001 82.03% 82.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-63 3837 6.84% 88.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-95 4190 7.47% 96.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-127 975 1.74% 98.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-159 304 0.54% 98.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-191 127 0.23% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-223 99 0.18% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-255 80 0.14% 99.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-287 114 0.20% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-319 122 0.22% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-351 75 0.13% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-383 40 0.07% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-415 26 0.05% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::416-447 17 0.03% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::448-479 12 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-511 8 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-543 13 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-575 10 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::576-607 5 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::608-639 3 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::640-671 4 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::672-703 5 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::704-735 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::736-767 3 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::768-799 4 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::896-927 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::992-1023 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1056-1087 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1184-1215 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 56080 # Writes before turning the bus around for reads -system.physmem.totQLat 15388206863 # Total ticks spent queuing -system.physmem.totMemAccLat 30090569363 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 3920630000 # Total ticks spent in databus transfers -system.physmem.avgQLat 19624.66 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 11927 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 14439 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 31518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 44897 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 53343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 63481 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 63532 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 67021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 67803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 70464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 69167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 70329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 66867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 85010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 86471 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 65847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 69713 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 62929 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1006 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 572 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 637 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 503 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 415 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 439 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 475 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 414 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 362 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 294 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 42 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 481355 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 311.708207 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 178.914901 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 339.146013 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 186832 38.81% 38.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 113175 23.51% 62.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 45398 9.43% 71.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 23450 4.87% 76.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 18101 3.76% 80.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 11671 2.42% 82.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 10460 2.17% 84.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 8315 1.73% 86.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 63953 13.29% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 481355 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 61522 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 20.647411 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 265.936082 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 61519 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-12287 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::63488-65535 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 61522 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 61522 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.458942 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.948779 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 6.823778 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 58490 95.07% 95.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 664 1.08% 96.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 448 0.73% 96.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 190 0.31% 97.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 308 0.50% 97.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 527 0.86% 98.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 143 0.23% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 33 0.05% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 36 0.06% 98.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 18 0.03% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 32 0.05% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 22 0.04% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 426 0.69% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 45 0.07% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 33 0.05% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 35 0.06% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 13 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 2 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 5 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 31 0.05% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 6 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-243 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 61522 # Writes before turning the bus around for reads +system.physmem.totQLat 31530968444 # Total ticks spent queuing +system.physmem.totMemAccLat 55349205944 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6351530000 # Total ticks spent in databus transfers +system.physmem.avgQLat 24821.55 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38374.66 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 0.98 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.04 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 0.96 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.10 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 43571.55 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.58 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.34 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.56 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.34 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.46 # Average write queue length when enqueuing -system.physmem.readRowHits 598254 # Number of row buffer hits during reads -system.physmem.writeRowHits 1312451 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.30 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.06 # Row buffer hit rate for writes -system.physmem.avgGap 20750692.59 # Average gap between requests -system.physmem.pageHitRate 78.84 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1947569400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1062661875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2990566800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5316898320 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3352003380960 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1226375853165 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29716511616000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34306208546520 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.470318 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49436040472112 # Time in different power states -system.physmem_0.memoryStateTime::REF 1713703160000 # Time in different power states +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing +system.physmem.avgWrQLen 22.31 # Average write queue length when enqueuing +system.physmem.readRowHits 1047361 # Number of row buffer hits during reads +system.physmem.writeRowHits 815697 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.45 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.94 # Row buffer hit rate for writes +system.physmem.avgGap 21864788.20 # Average gap between requests +system.physmem.pageHitRate 79.47 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1828287720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 997577625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4889757600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3480388560 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3352215959040 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1226219398425 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29718601656750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34308233025720 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.467372 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49439480717043 # Time in different power states +system.physmem_0.memoryStateTime::REF 1713811840000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 170725136888 # Time in different power states +system.physmem_0.memoryStateTime::ACT 170428636707 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1927966320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1051965750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3125569200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5305234320 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3352003380960 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1229368112910 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29713886826750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34306669056210 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.479291 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49431639282027 # Time in different power states -system.physmem_1.memoryStateTime::REF 1713703160000 # Time in different power states +system.physmem_1.actEnergy 1810756080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 988011750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 5018598000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3479837760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3352215959040 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1228704019020 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29716422156750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34308639338400 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.475289 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49435820968594 # Time in different power states +system.physmem_1.memoryStateTime::REF 1713811840000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 175126075973 # Time in different power states +system.physmem_1.memoryStateTime::ACT 174088371406 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 400 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory @@ -336,15 +340,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 226088242 # Number of BP lookups -system.cpu.branchPred.condPredicted 151212051 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12236747 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 159576730 # Number of BTB lookups -system.cpu.branchPred.BTBHits 104394184 # Number of BTB hits +system.cpu.branchPred.lookups 225557622 # Number of BP lookups +system.cpu.branchPred.condPredicted 150824960 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12221670 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 159273353 # Number of BTB lookups +system.cpu.branchPred.BTBHits 104130221 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 65.419428 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 31024336 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 344701 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 65.378307 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 30957399 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 344598 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -375,45 +379,45 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.dtb.walker.walks 200795 # Table walker walks requested -system.cpu.checker.dtb.walker.walksLong 200795 # Table walker walks initiated with long descriptors -system.cpu.checker.dtb.walker.walkWaitTime::samples 200795 # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walkWaitTime::0 200795 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walkWaitTime::total 200795 # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walksPending::samples 1638530500 # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walksPending::0 1638530500 100.00% 100.00% # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walksPending::total 1638530500 # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walkPageSizes::4K 155523 90.97% 90.97% # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkPageSizes::2M 15432 9.03% 100.00% # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkPageSizes::total 170955 # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 200795 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walks 199616 # Table walker walks requested +system.cpu.checker.dtb.walker.walksLong 199616 # Table walker walks initiated with long descriptors +system.cpu.checker.dtb.walker.walkWaitTime::samples 199616 # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walkWaitTime::0 199616 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walkWaitTime::total 199616 # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walksPending::samples 1622408500 # Table walker pending requests distribution +system.cpu.checker.dtb.walker.walksPending::0 1622408500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.checker.dtb.walker.walksPending::total 1622408500 # Table walker pending requests distribution +system.cpu.checker.dtb.walker.walkPageSizes::4K 155025 91.25% 91.25% # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkPageSizes::2M 14865 8.75% 100.00% # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkPageSizes::total 169890 # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 199616 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 200795 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 170955 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 199616 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 169890 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 170955 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin::total 371750 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 169890 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin::total 369506 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 160924630 # DTB read hits -system.cpu.checker.dtb.read_misses 149513 # DTB read misses -system.cpu.checker.dtb.write_hits 145982592 # DTB write hits -system.cpu.checker.dtb.write_misses 51282 # DTB write misses +system.cpu.checker.dtb.read_hits 160527490 # DTB read hits +system.cpu.checker.dtb.read_misses 148526 # DTB read misses +system.cpu.checker.dtb.write_hits 145616651 # DTB write hits +system.cpu.checker.dtb.write_misses 51090 # DTB write misses system.cpu.checker.dtb.flush_tlb 20 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.dtb.flush_tlb_mva_asid 79718 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.dtb.flush_tlb_asid 2054 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 72580 # Number of entries that have been flushed from TLB +system.cpu.checker.dtb.flush_tlb_mva_asid 79428 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.dtb.flush_tlb_asid 2050 # Number of times TLB was flushed by ASID +system.cpu.checker.dtb.flush_entries 72318 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 7050 # Number of TLB faults due to prefetch +system.cpu.checker.dtb.prefetch_faults 7517 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.dtb.perms_faults 19166 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 161074143 # DTB read accesses -system.cpu.checker.dtb.write_accesses 146033874 # DTB write accesses +system.cpu.checker.dtb.perms_faults 19125 # Number of TLB faults due to permissions restrictions +system.cpu.checker.dtb.read_accesses 160676016 # DTB read accesses +system.cpu.checker.dtb.write_accesses 145667741 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 306907222 # DTB hits -system.cpu.checker.dtb.misses 200795 # DTB misses -system.cpu.checker.dtb.accesses 307108017 # DTB accesses +system.cpu.checker.dtb.hits 306144141 # DTB hits +system.cpu.checker.dtb.misses 199616 # DTB misses +system.cpu.checker.dtb.accesses 306343757 # DTB accesses system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -443,46 +447,46 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.walker.walks 120591 # Table walker walks requested -system.cpu.checker.itb.walker.walksLong 120591 # Table walker walks initiated with long descriptors -system.cpu.checker.itb.walker.walkWaitTime::samples 120591 # Table walker wait (enqueue to first request) latency -system.cpu.checker.itb.walker.walkWaitTime::0 120591 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.checker.itb.walker.walkWaitTime::total 120591 # Table walker wait (enqueue to first request) latency -system.cpu.checker.itb.walker.walksPending::samples 1637932000 # Table walker pending requests distribution -system.cpu.checker.itb.walker.walksPending::0 1637932000 100.00% 100.00% # Table walker pending requests distribution -system.cpu.checker.itb.walker.walksPending::total 1637932000 # Table walker pending requests distribution -system.cpu.checker.itb.walker.walkPageSizes::4K 108617 98.83% 98.83% # Table walker page sizes translated -system.cpu.checker.itb.walker.walkPageSizes::2M 1291 1.17% 100.00% # Table walker page sizes translated -system.cpu.checker.itb.walker.walkPageSizes::total 109908 # Table walker page sizes translated +system.cpu.checker.itb.walker.walks 120521 # Table walker walks requested +system.cpu.checker.itb.walker.walksLong 120521 # Table walker walks initiated with long descriptors +system.cpu.checker.itb.walker.walkWaitTime::samples 120521 # Table walker wait (enqueue to first request) latency +system.cpu.checker.itb.walker.walkWaitTime::0 120521 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.checker.itb.walker.walkWaitTime::total 120521 # Table walker wait (enqueue to first request) latency +system.cpu.checker.itb.walker.walksPending::samples 1621807000 # Table walker pending requests distribution +system.cpu.checker.itb.walker.walksPending::0 1621807000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.checker.itb.walker.walksPending::total 1621807000 # Table walker pending requests distribution +system.cpu.checker.itb.walker.walkPageSizes::4K 108578 98.83% 98.83% # Table walker page sizes translated +system.cpu.checker.itb.walker.walkPageSizes::2M 1286 1.17% 100.00% # Table walker page sizes translated +system.cpu.checker.itb.walker.walkPageSizes::total 109864 # Table walker page sizes translated system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 120591 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 120591 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 120521 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 120521 # Table walker requests started/completed, data/inst system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 109908 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 109908 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin::total 230499 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.inst_hits 855922330 # ITB inst hits -system.cpu.checker.itb.inst_misses 120591 # ITB inst misses +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 109864 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 109864 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin::total 230385 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.inst_hits 853734937 # ITB inst hits +system.cpu.checker.itb.inst_misses 120521 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses system.cpu.checker.itb.write_hits 0 # DTB write hits system.cpu.checker.itb.write_misses 0 # DTB write misses system.cpu.checker.itb.flush_tlb 20 # Number of times complete TLB was flushed system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.itb.flush_tlb_mva_asid 79718 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.itb.flush_tlb_asid 2054 # Number of times TLB was flushed by ASID -system.cpu.checker.itb.flush_entries 52096 # Number of entries that have been flushed from TLB +system.cpu.checker.itb.flush_tlb_mva_asid 79428 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.itb.flush_tlb_asid 2050 # Number of times TLB was flushed by ASID +system.cpu.checker.itb.flush_entries 52057 # Number of entries that have been flushed from TLB system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 856042921 # ITB inst accesses -system.cpu.checker.itb.hits 855922330 # DTB hits -system.cpu.checker.itb.misses 120591 # DTB misses -system.cpu.checker.itb.accesses 856042921 # DTB accesses -system.cpu.checker.numCycles 1005785493 # number of cpu cycles simulated +system.cpu.checker.itb.inst_accesses 853855458 # ITB inst accesses +system.cpu.checker.itb.hits 853734937 # DTB hits +system.cpu.checker.itb.misses 120521 # DTB misses +system.cpu.checker.itb.accesses 853855458 # DTB accesses +system.cpu.checker.numCycles 1003246954 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -514,86 +518,87 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 945525 # Table walker walks requested -system.cpu.dtb.walker.walksLong 945525 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 17037 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 156802 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 426099 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 519426 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 1842.763936 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 11883.435839 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-32767 513062 98.77% 98.77% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::32768-65535 3320 0.64% 99.41% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::65536-98303 1249 0.24% 99.65% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::98304-131071 1137 0.22% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::131072-163839 115 0.02% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::163840-196607 205 0.04% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::196608-229375 84 0.02% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::229376-262143 60 0.01% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::262144-294911 94 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::294912-327679 5 0.00% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::327680-360447 21 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::360448-393215 44 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::393216-425983 30 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 519426 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 477950 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 21079.702044 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 16676.748393 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 15514.599645 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 472923 98.95% 98.95% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 4117 0.86% 99.81% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 574 0.12% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 200 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 75 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 25 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 26 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 8 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walks 951838 # Table walker walks requested +system.cpu.dtb.walker.walksLong 951838 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 16475 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 156308 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 435006 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 516832 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 1986.510123 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 12487.736879 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-32767 508349 98.36% 98.36% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::32768-65535 5443 1.05% 99.41% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::65536-98303 1244 0.24% 99.65% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::98304-131071 1085 0.21% 99.86% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::131072-163839 165 0.03% 99.89% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::163840-196607 178 0.03% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::196608-229375 121 0.02% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::229376-262143 54 0.01% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::262144-294911 95 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::294912-327679 7 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::327680-360447 5 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::360448-393215 38 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::393216-425983 41 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::425984-458751 7 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 516832 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 485267 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 21943.293074 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 17562.054008 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 15786.896980 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 475094 97.90% 97.90% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 9290 1.91% 99.82% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 546 0.11% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 199 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 82 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 29 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 20 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 5 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 477950 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 768700308080 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.730043 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.512304 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 766743156580 99.75% 99.75% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 1060609500 0.14% 99.88% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 401667500 0.05% 99.94% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 174666000 0.02% 99.96% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 138312000 0.02% 99.98% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 106588500 0.01% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 24500000 0.00% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 48487000 0.01% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::16-17 2321000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 768700308080 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 156803 90.20% 90.20% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 17037 9.80% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 173840 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 945525 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkCompletionTime::total 485267 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 776250627376 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.722476 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.519579 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 774163165376 99.73% 99.73% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 1120728500 0.14% 99.88% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 435636500 0.06% 99.93% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 187638500 0.02% 99.96% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 148036000 0.02% 99.97% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 113935000 0.01% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 26323500 0.00% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 52542500 0.01% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::16-17 2621500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 776250627376 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 156309 90.46% 90.46% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 16475 9.54% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 172784 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 951838 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 945525 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 173840 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 951838 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 172784 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 173840 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 1119365 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 172784 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 1124622 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 170900022 # DTB read hits -system.cpu.dtb.read_misses 675244 # DTB read misses -system.cpu.dtb.write_hits 148749524 # DTB write hits -system.cpu.dtb.write_misses 270281 # DTB write misses +system.cpu.dtb.read_hits 170417440 # DTB read hits +system.cpu.dtb.read_misses 677013 # DTB read misses +system.cpu.dtb.write_hits 148384109 # DTB write hits +system.cpu.dtb.write_misses 274825 # DTB write misses system.cpu.dtb.flush_tlb 20 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 79718 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 2054 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 72825 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 117 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 10420 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_tlb_mva_asid 79428 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 2050 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 72556 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 110 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 10696 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 69816 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 171575266 # DTB read accesses -system.cpu.dtb.write_accesses 149019805 # DTB write accesses +system.cpu.dtb.perms_faults 70061 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 171094453 # DTB read accesses +system.cpu.dtb.write_accesses 148658934 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 319649546 # DTB hits -system.cpu.dtb.misses 945525 # DTB misses -system.cpu.dtb.accesses 320595071 # DTB accesses +system.cpu.dtb.hits 318801549 # DTB hits +system.cpu.dtb.misses 951838 # DTB misses +system.cpu.dtb.accesses 319753387 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -623,209 +628,209 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 161869 # Table walker walks requested -system.cpu.itb.walker.walksLong 161869 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walks 162167 # Table walker walks requested +system.cpu.itb.walker.walksLong 162167 # Table walker walks initiated with long descriptors system.cpu.itb.walker.walksLongTerminationLevel::Level2 1433 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 122204 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 17648 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 144221 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 1045.076653 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 6935.040907 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-32767 143697 99.64% 99.64% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::32768-65535 129 0.09% 99.73% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::65536-98303 259 0.18% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::98304-131071 98 0.07% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::131072-163839 18 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::163840-196607 10 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::196608-229375 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::229376-262143 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::262144-294911 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 144221 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 141285 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 26183.154631 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 21986.379296 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 16137.175101 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 139260 98.57% 98.57% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 1739 1.23% 99.80% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 189 0.13% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 61 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 22 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 9 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksLongTerminationLevel::Level3 122178 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 17760 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 144407 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 1087.128740 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 7079.961036 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-32767 143546 99.40% 99.40% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::32768-65535 491 0.34% 99.74% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::65536-98303 245 0.17% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::98304-131071 86 0.06% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::131072-163839 14 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::163840-196607 13 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::196608-229375 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::229376-262143 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::262144-294911 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::294912-327679 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 144407 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 141371 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 27408.566821 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 23535.121999 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 16611.953111 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 138940 98.28% 98.28% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 2106 1.49% 99.77% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 209 0.15% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 62 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 27 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 18 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 7 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 141285 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 652736132088 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.935835 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.245289 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 41920855152 6.42% 6.42% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 610778213436 93.57% 99.99% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 36269000 0.01% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::3 794000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::4 500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 652736132088 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 122204 98.84% 98.84% # Table walker page sizes translated +system.cpu.itb.walker.walkCompletionTime::total 141371 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 655988501088 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.936740 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.243710 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 41542191152 6.33% 6.33% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 614402729936 93.66% 99.99% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 43110500 0.01% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 467500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::4 2000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 655988501088 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 122178 98.84% 98.84% # Table walker page sizes translated system.cpu.itb.walker.walkPageSizes::2M 1433 1.16% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 123637 # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 123611 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 161869 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 161869 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 162167 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 162167 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 123637 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 123637 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 285506 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 359459512 # ITB inst hits -system.cpu.itb.inst_misses 161869 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 123611 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 123611 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 285778 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 358625455 # ITB inst hits +system.cpu.itb.inst_misses 162167 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 20 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 79718 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 2054 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 53398 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 79428 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 2050 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 53363 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 372095 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 372145 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 359621381 # ITB inst accesses -system.cpu.itb.hits 359459512 # DTB hits -system.cpu.itb.misses 161869 # DTB misses -system.cpu.itb.accesses 359621381 # DTB accesses -system.cpu.numCycles 1580751099 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 358787622 # ITB inst accesses +system.cpu.itb.hits 358625455 # DTB hits +system.cpu.itb.misses 162167 # DTB misses +system.cpu.itb.accesses 358787622 # DTB accesses +system.cpu.numCycles 1590418745 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 647898483 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1008720689 # Number of instructions fetch has processed -system.cpu.fetch.Branches 226088242 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 135418520 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 855549558 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 26139542 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 3573192 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 26865 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9268939 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1033386 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 427 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 359070671 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6123790 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 48662 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 1530420621 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.772272 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.159981 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 646410999 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1006402404 # Number of instructions fetch has processed +system.cpu.fetch.Branches 225557622 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 135087620 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 866562323 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 26107474 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 3678311 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 25439 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 9275413 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1023850 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 676 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 358236204 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6112300 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 49056 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 1540030748 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.765724 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.157325 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 968902908 63.31% 63.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 215807485 14.10% 77.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 71036994 4.64% 82.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 274673234 17.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 979927440 63.63% 63.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 215057699 13.96% 77.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 70955696 4.61% 82.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 274089913 17.80% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1530420621 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.143026 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.638127 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 526178421 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 508648126 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 435713994 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 50619608 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9260472 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 33861678 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 3868815 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1093600087 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 29077129 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9260472 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 571338545 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 48532565 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 364379914 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 441167933 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 95741192 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1073752213 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 6802962 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 5086497 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 358848 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 628248 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 43820548 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 20190 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1021575372 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1655508848 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1270030956 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1469892 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 955737015 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 65838354 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 27320538 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23636945 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 103635545 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 174900719 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 152333814 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 9971771 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9081144 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1038303468 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 27624460 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1054196021 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3299994 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 60716319 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33847358 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 315461 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1530420621 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.688828 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.927358 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1540030748 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.141823 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.632791 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 525466953 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 519947088 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 434864784 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 50506307 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 9245616 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 33796734 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 3867997 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1090931528 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 29050280 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 9245616 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 570424085 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 50840114 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 363017689 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 440398811 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 106104433 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1071115355 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 6801917 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 5040663 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 343395 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 645255 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 54344412 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 20434 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1018974666 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1651092433 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1266893179 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1473696 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 953236782 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 65737881 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 27206823 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23528426 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 103688094 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 174464093 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 151959443 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 9931077 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9032567 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1035787653 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 27506074 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1051526043 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3293799 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 60619533 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33780075 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 314140 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1540030748 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.682795 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.925415 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 877745445 57.35% 57.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 337069342 22.02% 79.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 236293073 15.44% 94.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 72729594 4.75% 99.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6564084 0.43% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 19083 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 888949202 57.72% 57.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 336251490 21.83% 79.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 235798342 15.31% 94.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 72468185 4.71% 99.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6544331 0.42% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 19198 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1530420621 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1540030748 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 58206836 35.09% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 99242 0.06% 35.15% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 26725 0.02% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 744 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44573023 26.87% 62.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 62969604 37.96% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 58035888 35.01% 35.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 99674 0.06% 35.07% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 26738 0.02% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 574 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44566242 26.88% 61.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 63041416 38.03% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 57 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 725956407 68.86% 68.86% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2542188 0.24% 69.10% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 123122 0.01% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 724142674 68.87% 68.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2543730 0.24% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 122779 0.01% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 376 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.12% # Type of FU issued @@ -847,102 +852,102 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.12% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 120904 0.01% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 121012 0.01% 69.13% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.13% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.13% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 174804143 16.58% 85.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 150649152 14.29% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 174312709 16.58% 85.71% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 150282706 14.29% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1054196021 # Type of FU issued -system.cpu.iq.rate 0.666896 # Inst issue rate -system.cpu.iq.fu_busy_cnt 165876174 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.157349 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3805514237 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1125839347 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1036122901 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 2474593 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 946702 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 909865 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1218517790 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1554348 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 4347401 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1051526043 # Type of FU issued +system.cpu.iq.rate 0.661163 # Inst issue rate +system.cpu.iq.fu_busy_cnt 165770532 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.157648 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3809671307 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1123107931 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1033541701 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 2475857 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 947397 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 910004 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1215741366 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1555198 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 4333965 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 13878328 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14961 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 143108 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6347044 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 13839303 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14833 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 143349 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6338712 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2552620 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1870361 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2540349 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1552925 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9260472 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 6554396 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 3651492 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1066150871 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 9245616 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 6389360 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 5797347 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1063516239 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 174900719 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 152333814 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 23208148 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 59700 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3513413 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 143108 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3675827 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 5121930 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8797757 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1042985483 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 170888878 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10276947 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 174464093 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 151959443 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23100216 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 59008 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5663632 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 143349 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3667729 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 5111764 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8779493 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1040328227 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 170406440 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10257681 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 222943 # number of nop insts executed -system.cpu.iew.exec_refs 319634404 # number of memory reference insts executed -system.cpu.iew.exec_branches 197926826 # Number of branches executed -system.cpu.iew.exec_stores 148745526 # Number of stores executed -system.cpu.iew.exec_rate 0.659804 # Inst execution rate -system.cpu.iew.wb_sent 1037843882 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1037032766 # cumulative count of insts written-back -system.cpu.iew.wb_producers 441278048 # num instructions producing a value -system.cpu.iew.wb_consumers 713779914 # num instructions consuming a value +system.cpu.iew.exec_nop 222512 # number of nop insts executed +system.cpu.iew.exec_refs 318786335 # number of memory reference insts executed +system.cpu.iew.exec_branches 197400349 # Number of branches executed +system.cpu.iew.exec_stores 148379895 # Number of stores executed +system.cpu.iew.exec_rate 0.654122 # Inst execution rate +system.cpu.iew.wb_sent 1035262700 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1034451705 # cumulative count of insts written-back +system.cpu.iew.wb_producers 440415620 # num instructions producing a value +system.cpu.iew.wb_consumers 712619707 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.656038 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.618227 # average fanout of values written-back +system.cpu.iew.wb_rate 0.650427 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.618023 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 51563874 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 27308999 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 8427448 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1518403714 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.662019 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.290608 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 51498978 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 27191934 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 8413549 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1528028900 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.656188 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.286676 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 1001866977 65.98% 65.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 290832617 19.15% 85.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 121646355 8.01% 93.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 36740427 2.42% 95.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 28447666 1.87% 97.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14105700 0.93% 98.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8667985 0.57% 98.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4229973 0.28% 99.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 11866014 0.78% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 1013092181 66.30% 66.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 289858237 18.97% 85.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 121052617 7.92% 93.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 36682667 2.40% 95.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 28563883 1.87% 97.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14105791 0.92% 98.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8655946 0.57% 98.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4198069 0.27% 99.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 11819509 0.77% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1518403714 # Number of insts commited each cycle -system.cpu.commit.committedInsts 855512158 # Number of instructions committed -system.cpu.commit.committedOps 1005211605 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1528028900 # Number of insts commited each cycle +system.cpu.commit.committedInsts 853325819 # Number of instructions committed +system.cpu.commit.committedOps 1002674190 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 307009160 # Number of memory references committed -system.cpu.commit.loads 161022390 # Number of loads committed -system.cpu.commit.membars 6998413 # Number of memory barriers committed -system.cpu.commit.branches 190975004 # Number of branches committed -system.cpu.commit.fp_insts 896164 # Number of committed floating point instructions. -system.cpu.commit.int_insts 923410198 # Number of committed integer instructions. -system.cpu.commit.function_calls 25456304 # Number of function calls committed. +system.cpu.commit.refs 306245520 # Number of memory references committed +system.cpu.commit.loads 160624789 # Number of loads committed +system.cpu.commit.membars 6977905 # Number of memory barriers committed +system.cpu.commit.branches 190474151 # Number of branches committed +system.cpu.commit.fp_insts 896785 # Number of committed floating point instructions. +system.cpu.commit.int_insts 921116747 # Number of committed integer instructions. +system.cpu.commit.function_calls 25400785 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 695830631 69.22% 69.22% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 2161783 0.22% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 98401 0.01% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 694059947 69.22% 69.22% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2158876 0.22% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 98131 0.01% 69.45% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.45% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.45% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.45% # Class of committed instruction @@ -965,522 +970,535 @@ system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.45% # system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.45% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.45% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 111588 0.01% 69.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 111674 0.01% 69.46% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 161022390 16.02% 85.48% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 145986770 14.52% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 160624789 16.02% 85.48% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 145620731 14.52% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 1005211605 # Class of committed instruction -system.cpu.commit.bw_lim_events 11866014 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 2555711925 # The number of ROB reads -system.cpu.rob.rob_writes 2125474325 # The number of ROB writes -system.cpu.timesIdled 8142220 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 50330478 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 101060186847 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 855512158 # Number of Instructions Simulated -system.cpu.committedOps 1005211605 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.847725 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.847725 # CPI: Total CPI of All Threads -system.cpu.ipc 0.541206 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.541206 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1234726115 # number of integer regfile reads -system.cpu.int_regfile_writes 737118920 # number of integer regfile writes -system.cpu.fp_regfile_reads 1461359 # number of floating regfile reads -system.cpu.fp_regfile_writes 784484 # number of floating regfile writes -system.cpu.cc_regfile_reads 227546613 # number of cc regfile reads -system.cpu.cc_regfile_writes 228200703 # number of cc regfile writes -system.cpu.misc_regfile_reads 2526906641 # number of misc regfile reads -system.cpu.misc_regfile_writes 27367002 # number of misc regfile writes -system.cpu.dcache.tags.replacements 9794555 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.983548 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 285502634 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9795067 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.147594 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1659133250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.983548 # Average occupied blocks per requestor +system.cpu.commit.op_class_0::total 1002674190 # Class of committed instruction +system.cpu.commit.bw_lim_events 11819509 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 2562796067 # The number of ROB reads +system.cpu.rob.rob_writes 2120254358 # The number of ROB writes +system.cpu.timesIdled 8129447 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 50387997 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 101057024238 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 853325819 # Number of Instructions Simulated +system.cpu.committedOps 1002674190 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.863788 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.863788 # CPI: Total CPI of All Threads +system.cpu.ipc 0.536542 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.536542 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1231590969 # number of integer regfile reads +system.cpu.int_regfile_writes 735370650 # number of integer regfile writes +system.cpu.fp_regfile_reads 1462122 # number of floating regfile reads +system.cpu.fp_regfile_writes 782688 # number of floating regfile writes +system.cpu.cc_regfile_reads 226859046 # number of cc regfile reads +system.cpu.cc_regfile_writes 227515194 # number of cc regfile writes +system.cpu.misc_regfile_reads 2534481060 # number of misc regfile reads +system.cpu.misc_regfile_writes 27245755 # number of misc regfile writes +system.cpu.dcache.tags.replacements 9758519 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.983709 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 284707567 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9759031 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.173754 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1642601500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.983709 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999968 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999968 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 409 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 386 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1246939843 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1246939843 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 148420477 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 148420477 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 129257116 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 129257116 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 380071 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 380071 # number of SoftPFReq hits -system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 323830 # number of WriteInvalidateReq hits -system.cpu.dcache.WriteInvalidateReq_hits::total 323830 # number of WriteInvalidateReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3338713 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3338713 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 3738459 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3738459 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 277677593 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 277677593 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 278057664 # number of overall hits -system.cpu.dcache.overall_hits::total 278057664 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9529450 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9529450 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 11422113 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 11422113 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1191409 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1191409 # number of SoftPFReq misses -system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1233320 # number of WriteInvalidateReq misses -system.cpu.dcache.WriteInvalidateReq_misses::total 1233320 # number of WriteInvalidateReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 451226 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 451226 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 6 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 6 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 20951563 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 20951563 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 22142972 # number of overall misses -system.cpu.dcache.overall_misses::total 22142972 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 145395860730 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 145395860730 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 336812014094 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 336812014094 # number of WriteReq miss cycles -system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 35299806246 # number of WriteInvalidateReq miss cycles -system.cpu.dcache.WriteInvalidateReq_miss_latency::total 35299806246 # number of WriteInvalidateReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6459718484 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 6459718484 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 237001 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 237001 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 482207874824 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 482207874824 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 482207874824 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 482207874824 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 157949927 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 157949927 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 140679229 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 140679229 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1571480 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1571480 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1557150 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::total 1557150 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3789939 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3789939 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 3738465 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 3738465 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 298629156 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 298629156 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 300200636 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 300200636 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060332 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.060332 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081193 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.081193 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.758145 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.758145 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.792037 # miss rate for WriteInvalidateReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.792037 # miss rate for WriteInvalidateReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.119059 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.119059 # miss rate for LoadLockedReq accesses +system.cpu.dcache.tags.tag_accesses 1243872376 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1243872376 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 147964440 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 147964440 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 128940955 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 128940955 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 380183 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 380183 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 324678 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 324678 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3327415 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3327415 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 3725844 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 3725844 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 276905395 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 276905395 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 277285578 # number of overall hits +system.cpu.dcache.overall_hits::total 277285578 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9612542 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9612542 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 11385353 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 11385353 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1184834 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1184834 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1232047 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1232047 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 450033 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 450033 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 7 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 7 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 20997895 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 20997895 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 22182729 # number of overall misses +system.cpu.dcache.overall_misses::total 22182729 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 144669003500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 144669003500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 330867751444 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 330867751444 # number of WriteReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 63675897168 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 63675897168 # number of WriteLineReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6433485000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 6433485000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 251000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 251000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 475536754944 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 475536754944 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 475536754944 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 475536754944 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 157576982 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 157576982 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 140326308 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 140326308 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1565017 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1565017 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::cpu.data 1556725 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 1556725 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3777448 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3777448 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 3725851 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 3725851 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 297903290 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 297903290 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 299468307 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 299468307 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061002 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.061002 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081135 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.081135 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.757074 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.757074 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.791435 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.791435 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.119137 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.119137 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000002 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.070159 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.070159 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.073761 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.073761 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15257.529105 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15257.529105 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29487.715110 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29487.715110 # average WriteReq miss latency -system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 28621.773948 # average WriteInvalidateReq miss latency -system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 28621.773948 # average WriteInvalidateReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14315.927017 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14315.927017 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 39500.166667 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 39500.166667 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23015.365241 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23015.365241 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21777.016871 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21777.016871 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 20545206 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.070486 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.070486 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.074074 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.074074 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15050.025633 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15050.025633 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29060.825031 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29060.825031 # average WriteReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 51683.009794 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 51683.009794 # average WriteLineReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14295.584990 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14295.584990 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 35857.142857 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 35857.142857 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22646.877458 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22646.877458 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21437.252150 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21437.252150 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 35158879 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1559097 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1606955 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.177632 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.879193 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 7577660 # number of writebacks -system.cpu.dcache.writebacks::total 7577660 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4366240 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4366240 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9388231 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 9388231 # number of WriteReq MSHR hits -system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.data 7155 # number of WriteInvalidateReq MSHR hits -system.cpu.dcache.WriteInvalidateReq_mshr_hits::total 7155 # number of WriteInvalidateReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 220115 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 220115 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 13754471 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 13754471 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 13754471 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 13754471 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5163210 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5163210 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2033882 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2033882 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1184642 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1184642 # number of SoftPFReq MSHR misses -system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data 1226165 # number of WriteInvalidateReq MSHR misses -system.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1226165 # number of WriteInvalidateReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 231111 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 231111 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 6 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 6 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 7197092 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 7197092 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 8381734 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 8381734 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33661 # number of ReadReq MSHR uncacheable -system.cpu.dcache.ReadReq_mshr_uncacheable::total 33661 # number of ReadReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33682 # number of WriteReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::total 33682 # number of WriteReq MSHR uncacheable -system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67343 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 67343 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 73626554579 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 73626554579 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 56871439750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 56871439750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 19552019274 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 19552019274 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 33205804688 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 33205804688 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2956928250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2956928250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 227999 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 227999 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 130497994329 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 130497994329 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 150050013603 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 150050013603 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5746385500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5746385500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5629281968 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5629281968 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11375667468 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 11375667468 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032689 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032689 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014458 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014458 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.753838 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.753838 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.787442 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.787442 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060980 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060980 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.writebacks::writebacks 7549082 # number of writebacks +system.cpu.dcache.writebacks::total 7549082 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4467834 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4467834 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9360902 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 9360902 # number of WriteReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 7079 # number of WriteLineReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::total 7079 # number of WriteLineReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 219205 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 219205 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 13828736 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 13828736 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 13828736 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 13828736 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5144708 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5144708 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2024451 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2024451 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1178103 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1178103 # number of SoftPFReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1224968 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 1224968 # number of WriteLineReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 230828 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 230828 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 7 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 7 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 7169159 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 7169159 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 8347262 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 8347262 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33678 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadReq_mshr_uncacheable::total 33678 # number of ReadReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33696 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 33696 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67374 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 67374 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75818409500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 75818409500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57062160713 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 57062160713 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 20148080000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 20148080000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 62191648168 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 62191648168 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3063087000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3063087000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 244000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 244000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 132880570213 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 132880570213 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 153028650213 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 153028650213 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5828327500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5828327500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5707957967 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5707957967 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11536285467 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 11536285467 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032649 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032649 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014427 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014427 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.752773 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.752773 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786888 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786888 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.061107 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.061107 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000002 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024100 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.024100 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027920 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.027920 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14259.841180 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14259.841180 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27962.015373 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27962.015373 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16504.580518 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16504.580518 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 27081.024730 # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 27081.024730 # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12794.407233 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12794.407233 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 37999.833333 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 37999.833333 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18132.044766 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18132.044766 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17902.025238 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17902.025238 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 170713.451769 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 170713.451769 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 167130.276349 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 167130.276349 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 168921.305377 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 168921.305377 # average overall mshr uncacheable latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024065 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.024065 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027874 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.027874 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14737.164772 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14737.164772 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28186.486466 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28186.486466 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17102.137929 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17102.137929 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 50770.018619 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 50770.018619 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13269.997574 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13269.997574 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 34857.142857 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 34857.142857 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18535.029034 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18535.029034 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18332.795857 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18332.795857 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173060.380664 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173060.380664 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 169395.713646 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169395.713646 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 171227.557619 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 171227.557619 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 15070815 # number of replacements -system.cpu.icache.tags.tagsinuse 511.953323 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 343233622 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15071327 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 22.773948 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 14049577000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.953323 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999909 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999909 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 15042093 # number of replacements +system.cpu.icache.tags.tagsinuse 511.944879 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 342405629 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15042605 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 22.762389 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 17214303500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.944879 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999892 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999892 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 102 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 99 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 374120916 # Number of tag accesses -system.cpu.icache.tags.data_accesses 374120916 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 343233622 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 343233622 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 343233622 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 343233622 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 343233622 # number of overall hits -system.cpu.icache.overall_hits::total 343233622 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 15815747 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 15815747 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 15815747 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 15815747 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 15815747 # number of overall misses -system.cpu.icache.overall_misses::total 15815747 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 208885866517 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 208885866517 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 208885866517 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 208885866517 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 208885866517 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 208885866517 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 359049369 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 359049369 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 359049369 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 359049369 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 359049369 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 359049369 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.044049 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.044049 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.044049 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.044049 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.044049 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.044049 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13207.461305 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13207.461305 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13207.461305 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13207.461305 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13207.461305 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13207.461305 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 13684 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 373257734 # Number of tag accesses +system.cpu.icache.tags.data_accesses 373257734 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 342405629 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 342405629 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 342405629 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 342405629 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 342405629 # number of overall hits +system.cpu.icache.overall_hits::total 342405629 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 15809279 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 15809279 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 15809279 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 15809279 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 15809279 # number of overall misses +system.cpu.icache.overall_misses::total 15809279 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 208403044384 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 208403044384 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 208403044384 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 208403044384 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 208403044384 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 208403044384 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 358214908 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 358214908 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 358214908 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 358214908 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 358214908 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 358214908 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.044134 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.044134 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.044134 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.044134 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.044134 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.044134 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13182.324405 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13182.324405 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13182.324405 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13182.324405 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13182.324405 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13182.324405 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 15030 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 1126 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 1210 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 12.152753 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 12.421488 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 744199 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 744199 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 744199 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 744199 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 744199 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 744199 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15071548 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15071548 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15071548 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15071548 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15071548 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15071548 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 766453 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 766453 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 766453 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 766453 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 766453 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 766453 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15042826 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15042826 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 15042826 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 15042826 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 15042826 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 15042826 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 21295 # number of ReadReq MSHR uncacheable system.cpu.icache.ReadReq_mshr_uncacheable::total 21295 # number of ReadReq MSHR uncacheable system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 21295 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 21295 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 179787086612 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 179787086612 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 179787086612 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 179787086612 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 179787086612 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 179787086612 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1585009250 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1585009250 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1585009250 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 1585009250 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.041976 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.041976 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.041976 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.041976 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.041976 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.041976 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11928.906481 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11928.906481 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11928.906481 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11928.906481 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11928.906481 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11928.906481 # average overall mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 74431.051890 # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 74431.051890 # average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 74431.051890 # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 74431.051890 # average overall mshr uncacheable latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 186915451392 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 186915451392 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 186915451392 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 186915451392 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 186915451392 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 186915451392 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1594412000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1594412000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1594412000 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 1594412000 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.041994 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.041994 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.041994 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.041994 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.041994 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.041994 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12425.554307 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12425.554307 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12425.554307 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12425.554307 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12425.554307 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12425.554307 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 74872.599202 # average ReadReq mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 74872.599202 # average ReadReq mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 74872.599202 # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 74872.599202 # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1159288 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65272.997993 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 29043191 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1221496 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 23.776739 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2756226000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 37273.751083 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 319.528316 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 474.614102 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 7535.726920 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 19669.377573 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.568752 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004876 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007242 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.114986 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.300131 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.995987 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 304 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 61904 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 304 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 579 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2674 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5116 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 53473 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004639 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.944580 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 272839925 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 272839925 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 805883 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 304376 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 14986718 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 6321707 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 22418684 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 7577660 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 7577660 # number of Writeback hits -system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data 730602 # number of WriteInvalidateReq hits -system.cpu.l2cache.WriteInvalidateReq_hits::total 730602 # number of WriteInvalidateReq hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 9499 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 9499 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1579833 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1579833 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 805883 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 304376 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 14986718 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 7901540 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 23998517 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 805883 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 304376 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 14986718 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 7901540 # number of overall hits -system.cpu.l2cache.overall_hits::total 23998517 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 3166 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3020 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 84629 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 253686 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 344501 # number of ReadReq misses -system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data 495562 # number of WriteInvalidateReq misses -system.cpu.l2cache.WriteInvalidateReq_misses::total 495562 # number of WriteInvalidateReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 34430 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 34430 # number of UpgradeReq misses +system.cpu.l2cache.tags.replacements 1148683 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65278.817014 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 46198537 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1210914 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 38.151790 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 15659706000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 37192.962627 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 301.460755 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 460.210435 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 7626.713626 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 19697.469572 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.567520 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004600 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007022 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.116374 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.300560 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996076 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 380 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 61851 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 379 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 530 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2690 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5173 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 53395 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.005798 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.943771 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 410382726 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 410382726 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 788948 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 299798 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1088746 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 7549082 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 7549082 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 9455 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 9455 # number of UpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 4 # number of SCUpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::total 4 # number of SCUpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1576072 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1576072 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14958434 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 14958434 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6296354 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 6296354 # number of ReadSharedReq hits +system.cpu.l2cache.InvalidateReq_hits::cpu.data 732370 # number of InvalidateReq hits +system.cpu.l2cache.InvalidateReq_hits::total 732370 # number of InvalidateReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 788948 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 299798 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 14958434 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 7872426 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 23919606 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 788948 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 299798 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 14958434 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 7872426 # number of overall hits +system.cpu.l2cache.overall_hits::total 23919606 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 3175 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2963 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 6138 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 34552 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 34552 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 413693 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 413693 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 3166 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 3020 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 84629 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 667379 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 758194 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 3166 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 3020 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 84629 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 667379 # number of overall misses -system.cpu.l2cache.overall_misses::total 758194 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 276962259 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 263518500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 7145038838 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22760355464 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 30445875061 # number of ReadReq miss cycles -system.cpu.l2cache.WriteInvalidateReq_miss_latency::cpu.data 4785347 # number of WriteInvalidateReq miss cycles -system.cpu.l2cache.WriteInvalidateReq_miss_latency::total 4785347 # number of WriteInvalidateReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 553374801 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 553374801 # number of UpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 159000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 36882340129 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 36882340129 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 276962259 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 263518500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 7145038838 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 59642695593 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 67328215190 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 276962259 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 263518500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 7145038838 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 59642695593 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 67328215190 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 809049 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 307396 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 15071347 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 6575393 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 22763185 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 7577660 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 7577660 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data 1226164 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.l2cache.WriteInvalidateReq_accesses::total 1226164 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 43929 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 43929 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 6 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 6 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1993526 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1993526 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 809049 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 307396 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 15071347 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 8568919 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 24756711 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 809049 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 307396 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 15071347 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 8568919 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 24756711 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.003913 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.009824 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.005615 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.038581 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.015134 # miss rate for ReadReq accesses -system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data 0.404156 # miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.404156 # miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.783765 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.783765 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.207518 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.207518 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.003913 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.009824 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005615 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.077884 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.030626 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.003913 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.009824 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005615 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.077884 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.030626 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 87480.182881 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 87257.781457 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 84427.782888 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 89718.610660 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 88376.739287 # average ReadReq miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::cpu.data 9.656404 # average WriteInvalidateReq miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::total 9.656404 # average WriteInvalidateReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 16072.460093 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 16072.460093 # average UpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 53000 # average SCUpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 53000 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89153.889790 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89153.889790 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 87480.182881 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 87257.781457 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84427.782888 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89368.553091 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 88800.775514 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 87480.182881 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 87257.781457 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84427.782888 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89368.553091 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 88800.775514 # average overall miss latency +system.cpu.l2cache.ReadExReq_misses::cpu.data 407912 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 407912 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 84184 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 84184 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 253746 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 253746 # number of ReadSharedReq misses +system.cpu.l2cache.InvalidateReq_misses::cpu.data 492598 # number of InvalidateReq misses +system.cpu.l2cache.InvalidateReq_misses::total 492598 # number of InvalidateReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 3175 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 2963 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 84184 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 661658 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 751980 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 3175 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 2963 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 84184 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 661658 # number of overall misses +system.cpu.l2cache.overall_misses::total 751980 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 276956000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 265379500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 542335500 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 544075000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 544075000 # number of UpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 160500 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::total 160500 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 36032836500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 36032836500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 7082572500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 7082572500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 22536354000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 22536354000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 51203919000 # number of InvalidateReq miss cycles +system.cpu.l2cache.InvalidateReq_miss_latency::total 51203919000 # number of InvalidateReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 276956000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 265379500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 7082572500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 58569190500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 66194098500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 276956000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 265379500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 7082572500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 58569190500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 66194098500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 792123 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 302761 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1094884 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 7549082 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 7549082 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 44007 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 44007 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 7 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 7 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1983984 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1983984 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15042618 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 15042618 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 6550100 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 6550100 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1224968 # number of InvalidateReq accesses(hits+misses) +system.cpu.l2cache.InvalidateReq_accesses::total 1224968 # number of InvalidateReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 792123 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 302761 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 15042618 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 8534084 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 24671586 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 792123 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 302761 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 15042618 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 8534084 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 24671586 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.004008 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.009787 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.005606 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.785148 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.785148 # miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.428571 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.428571 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.205602 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.205602 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005596 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005596 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.038739 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.038739 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.402131 # miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::total 0.402131 # miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.004008 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.009787 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005596 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.077531 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.030480 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.004008 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.009787 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005596 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.077531 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.030480 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 87230.236220 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 89564.461694 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 88357.038123 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15746.555916 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15746.555916 # average UpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 53500 # average SCUpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 53500 # average SCUpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88334.828345 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88334.828345 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84132.050033 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84132.050033 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88814.617767 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88814.617767 # average ReadSharedReq miss latency +system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 103946.664420 # average InvalidateReq miss latency +system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 103946.664420 # average InvalidateReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 87230.236220 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 89564.461694 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84132.050033 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88518.827703 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 88026.408282 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 87230.236220 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 89564.461694 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84132.050033 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88518.827703 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 88026.408282 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1489,182 +1507,196 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 977263 # number of writebacks -system.cpu.l2cache.writebacks::total 977263 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 21 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 21 # number of ReadReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 967181 # number of writebacks +system.cpu.l2cache.writebacks::total 967181 # number of writebacks +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 21 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 21 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 21 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 21 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 3166 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3020 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 84629 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 253665 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 344480 # number of ReadReq MSHR misses -system.cpu.l2cache.WriteInvalidateReq_mshr_misses::cpu.data 495562 # number of WriteInvalidateReq MSHR misses -system.cpu.l2cache.WriteInvalidateReq_mshr_misses::total 495562 # number of WriteInvalidateReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 34430 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 34430 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 3175 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2963 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 6138 # number of ReadReq MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1073 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 1073 # number of CleanEvict MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 34552 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 34552 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 413693 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 413693 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 3166 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3020 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 84629 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 667358 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 758173 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 3166 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3020 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 84629 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 667358 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 758173 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 407912 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 407912 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 84184 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 84184 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 253725 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 253725 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 492598 # number of InvalidateReq MSHR misses +system.cpu.l2cache.InvalidateReq_mshr_misses::total 492598 # number of InvalidateReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 3175 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2963 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 84184 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 661637 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 751959 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 3175 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2963 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 84184 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 661637 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 751959 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 21295 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33661 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.ReadReq_mshr_uncacheable::total 54956 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33682 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33682 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33678 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::total 54973 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33696 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33696 # number of WriteReq MSHR uncacheable system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 21295 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67343 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::total 88638 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 237171251 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 225518000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6085544162 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19591961036 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 26140194449 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data 16855177398 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total 16855177398 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 611252927 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 611252927 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 153001 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 153001 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31729551871 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31729551871 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 237171251 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 225518000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6085544162 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 51321512907 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 57869746320 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 237171251 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 225518000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6085544162 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 51321512907 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 57869746320 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1276231250 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5274563500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6550794750 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5186666500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5186666500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1276231250 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10461230000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11737461250 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.003913 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.009824 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.005615 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.038578 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015133 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.404156 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.404156 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.783765 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.783765 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.207518 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.207518 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.003913 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.009824 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005615 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.077881 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.030625 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.003913 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.009824 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005615 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.077881 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.030625 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 74911.955464 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 74674.834437 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 71908.496638 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77235.570678 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 75883.054021 # average ReadReq mshr miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 34012.247505 # average WriteInvalidateReq mshr miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 34012.247505 # average WriteInvalidateReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17753.497735 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17753.497735 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 51000.333333 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 51000.333333 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76698.304953 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76698.304953 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 74911.955464 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 74674.834437 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71908.496638 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76902.521446 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76327.891286 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 74911.955464 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 74674.834437 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71908.496638 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76902.521446 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76327.891286 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 59931.028410 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 156696.577642 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 119200.719667 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 153989.267264 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 153989.267264 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 59931.028410 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 155342.500334 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 132420.195063 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67374 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 88669 # number of overall MSHR uncacheable misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 245206000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 235749500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 480955500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 717374500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 717374500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 161500 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 161500 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31953716500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31953716500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 6240732500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 6240732500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19997854000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19997854000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 46277939000 # number of InvalidateReq MSHR miss cycles +system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 46277939000 # number of InvalidateReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 245206000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 235749500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6240732500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 51951570500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 58673258500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 245206000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 235749500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6240732500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 51951570500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 58673258500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1328224500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5407344500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6735569000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5315951000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5315951000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1328224500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10723295500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 12051520000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.004008 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.009787 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.005606 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.785148 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.785148 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.428571 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.428571 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.205602 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.205602 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005596 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005596 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.038736 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.038736 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.402131 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.402131 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.004008 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.009787 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005596 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.077529 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.030479 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.004008 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.009787 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005596 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.077529 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.030479 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 77230.236220 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 79564.461694 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 78357.038123 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20762.170063 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20762.170063 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 53833.333333 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 53833.333333 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78334.828345 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78334.828345 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74132.050033 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74132.050033 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78817.042073 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78817.042073 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 93946.664420 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 93946.664420 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 77230.236220 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 79564.461694 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74132.050033 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78519.747989 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78027.204276 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 77230.236220 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 79564.461694 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74132.050033 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78519.747989 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78027.204276 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 62372.599202 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160560.143120 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 122525.039565 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 157762.078585 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157762.078585 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 62372.599202 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 159160.737080 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 135915.821764 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 23293786 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 23285542 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 33682 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 33682 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 7577660 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1332936 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1226164 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 43932 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 6 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 43938 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1993526 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1993526 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 30185484 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27390990 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 736951 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1962535 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 60275960 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 964906864 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1112084525 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2459168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6472392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2085922949 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 583028 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 34275542 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.049559 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.217032 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadReq 1633565 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 23227278 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33696 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 8622904 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 17438576 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 44010 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 44017 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1983984 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1983984 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 15042826 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 6558947 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1331632 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1224968 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45167572 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29499463 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 732865 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1940611 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 77340511 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 963068272 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1029563294 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2422088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6336984 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2001390638 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1864369 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 52693428 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.056141 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.230194 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 32576878 95.04% 95.04% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 1698664 4.96% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 49735173 94.39% 94.39% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 2958255 5.61% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 34275542 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 25901169608 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 52693428 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 33222815494 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 909000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1182000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 22654600125 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 22592032956 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13659008538 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13487423434 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 430754363 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 430634727 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1154477924 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1148958035 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40283 # Transaction distribution -system.iobus.trans_dist::ReadResp 40283 # Transaction distribution -system.iobus.trans_dist::WriteReq 136558 # Transaction distribution -system.iobus.trans_dist::WriteResp 29894 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution +system.iobus.trans_dist::ReadReq 40295 # Transaction distribution +system.iobus.trans_dist::ReadResp 40295 # Transaction distribution +system.iobus.trans_dist::WriteReq 136571 # Transaction distribution +system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -1675,17 +1707,17 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29496 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122652 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230950 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230950 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230948 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230948 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353682 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353732 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1696,17 +1728,17 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17529 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155805 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334232 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334224 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334224 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492123 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7492144 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) @@ -1727,7 +1759,7 @@ system.iobus.reqLayer16.occupancy 12000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 21908000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) @@ -1735,211 +1767,213 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 607064814 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 568813596 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92761000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 148363066 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147708000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 174500 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115456 # number of replacements -system.iocache.tags.tagsinuse 10.424607 # Cycle average of tags in use +system.iocache.tags.replacements 115455 # number of replacements +system.iocache.tags.tagsinuse 10.423947 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115472 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115471 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13092103918000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.544640 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.879967 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.221540 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.429998 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651538 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13095311635000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.544418 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.879529 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.221526 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.429971 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651497 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039632 # Number of tag accesses -system.iocache.tags.data_accesses 1039632 # Number of data accesses +system.iocache.tags.tag_accesses 1039623 # Number of tag accesses +system.iocache.tags.data_accesses 1039623 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8811 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8848 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8810 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8847 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8811 # number of demand (read+write) misses -system.iocache.demand_misses::total 8851 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8810 # number of demand (read+write) misses +system.iocache.demand_misses::total 8850 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8811 # number of overall misses -system.iocache.overall_misses::total 8851 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5072000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1609809480 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1614881480 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::realview.ethernet 352500 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 352500 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19830913268 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 19830913268 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5424500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1609809480 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1615233980 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5424500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1609809480 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1615233980 # number of overall miss cycles +system.iocache.overall_misses::realview.ide 8810 # number of overall misses +system.iocache.overall_misses::total 8850 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5069000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1621911166 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1626980166 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12610487430 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12610487430 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5420000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1621911166 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1627331166 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5420000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1621911166 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1627331166 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8811 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8848 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8810 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8847 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8811 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8851 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8810 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8850 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8811 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8851 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8810 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8850 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 182704.514811 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 182513.729656 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117500 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 117500 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 185919.459874 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 185919.459874 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 182704.514811 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 182491.693594 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 182704.514811 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 182491.693594 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 110252 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137000 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 184098.883768 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 183901.906409 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118226.275313 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118226.275313 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135500 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 184098.883768 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 183879.227797 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135500 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 184098.883768 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 183879.227797 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 31681 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 16154 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3345 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.825059 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.471151 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8811 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8848 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8810 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8847 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8811 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8851 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8810 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8850 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8811 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8851 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3142000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1150531536 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1153673536 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 193500 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 193500 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14284309344 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14284309344 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3335500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1150531536 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1153867036 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3335500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1150531536 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1153867036 # number of overall MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8810 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8850 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1181411166 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1184630166 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7277287430 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7277287430 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3420000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1181411166 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1184831166 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3420000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1181411166 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1184831166 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 84918.918919 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 130578.996255 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 130388.057866 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 64500 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 64500 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133918.748069 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133918.748069 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 130578.996255 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 130365.725455 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 130578.996255 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 130365.725455 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87000 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 134098.883768 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 133901.906409 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68226.275313 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68226.275313 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 134098.883768 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 133879.227797 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 134098.883768 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 133879.227797 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 408284 # Transaction distribution -system.membus.trans_dist::ReadResp 408284 # Transaction distribution -system.membus.trans_dist::WriteReq 33682 # Transaction distribution -system.membus.trans_dist::WriteResp 33682 # Transaction distribution -system.membus.trans_dist::Writeback 1083893 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 602073 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 602073 # Transaction distribution -system.membus.trans_dist::UpgradeReq 35223 # Transaction distribution +system.membus.trans_dist::ReadReq 54973 # Transaction distribution +system.membus.trans_dist::ReadResp 407867 # Transaction distribution +system.membus.trans_dist::WriteReq 33696 # Transaction distribution +system.membus.trans_dist::WriteResp 33696 # Transaction distribution +system.membus.trans_dist::Writeback 1073811 # Transaction distribution +system.membus.trans_dist::CleanEvict 187846 # Transaction distribution +system.membus.trans_dist::UpgradeReq 35358 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 35226 # Transaction distribution -system.membus.trans_dist::ReadExReq 413056 # Transaction distribution -system.membus.trans_dist::ReadExResp 413056 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122652 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeResp 35361 # Transaction distribution +system.membus.trans_dist::ReadExReq 899707 # Transaction distribution +system.membus.trans_dist::ReadExResp 899707 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 352894 # Transaction distribution +system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution +system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 60 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6848 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3600651 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3730211 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335301 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 335301 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4065512 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155805 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3753956 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3883578 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341714 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 341714 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4225292 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 436 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13696 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 143052172 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 143222109 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14066304 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14066304 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 157288413 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3023 # Total snoops (count) -system.membus.snoop_fanout::samples 2576774 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 141818700 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 141988686 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7244096 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7244096 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 149232782 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 2955 # Total snoops (count) +system.membus.snoop_fanout::samples 2747442 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2576774 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2747442 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2576774 # Request fanout histogram -system.membus.reqLayer0.occupancy 104078000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2747442 # Request fanout histogram +system.membus.reqLayer0.occupancy 104159500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 33000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5439500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5443500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 9540063820 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 7279924206 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 4726359104 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 6776038462 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 151502434 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 228860056 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -1984,6 +2018,6 @@ system.realview.ethernet.coalescedTotal 0 # av system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16160 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 16150 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt index 3de7ccdf1..8076f9ab6 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt @@ -1,172 +1,172 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.385466 # Number of seconds simulated -sim_ticks 47385466309500 # Number of ticks simulated -final_tick 47385466309500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.309771 # Number of seconds simulated +sim_ticks 47309771277000 # Number of ticks simulated +final_tick 47309771277000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 109383 # Simulator instruction rate (inst/s) -host_op_rate 128637 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5566054279 # Simulator tick rate (ticks/s) -host_mem_usage 771804 # Number of bytes of host memory used -host_seconds 8513.30 # Real time elapsed on the host -sim_insts 931207580 # Number of instructions simulated -sim_ops 1095127739 # Number of ops (including micro ops) simulated +host_inst_rate 108265 # Simulator instruction rate (inst/s) +host_op_rate 127309 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5527040503 # Simulator tick rate (ticks/s) +host_mem_usage 775928 # Number of bytes of host memory used +host_seconds 8559.69 # Real time elapsed on the host +sim_insts 926711685 # Number of instructions simulated +sim_ops 1089722710 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 167872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 148672 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 4509472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 15471624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 18877376 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 171456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 164224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3092064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 12069648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 17196544 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 427520 # Number of bytes read from this memory -system.physmem.bytes_read::total 72296472 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 4509472 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3092064 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 7601536 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 87689472 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 238272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 235456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 4799840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 48757000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 23433152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 111936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 80000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2674208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 14294352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 12912064 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 433024 # Number of bytes read from this memory +system.physmem.bytes_read::total 107969304 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 4799840 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2674208 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7474048 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 89515968 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 87710056 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2623 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2323 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 86413 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 241757 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 294959 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2679 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2566 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 48357 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 188601 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 268696 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6680 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1145654 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1370148 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 89536552 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 3723 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3679 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 90950 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 761841 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 366143 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1749 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1250 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 41828 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 223362 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 201751 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6766 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1703042 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1398687 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1372722 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3543 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 3138 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 95166 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 326506 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 398379 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 3618 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 3466 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 65253 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 254712 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 362908 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9022 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1525710 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 95166 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 65253 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 160419 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1850556 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1401261 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 5036 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 4977 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 101456 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1030590 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 495313 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2366 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 1691 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 56525 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 302144 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 272926 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9153 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2282178 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 101456 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 56525 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 157981 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1892124 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1850991 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1850556 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3543 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 3138 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 95166 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 326940 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 398379 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 3618 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 3466 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 65253 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 254712 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 362908 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9022 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3376701 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1145654 # Number of read requests accepted -system.physmem.writeReqs 2060182 # Number of write requests accepted -system.physmem.readBursts 1145654 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 2060182 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 73301632 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 20224 # Total number of bytes read from write queue -system.physmem.bytesWritten 128743424 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 72296472 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 131707496 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 316 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 48535 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 120456 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 65572 # Per bank write bursts -system.physmem.perBankRdBursts::1 75328 # Per bank write bursts -system.physmem.perBankRdBursts::2 66668 # Per bank write bursts -system.physmem.perBankRdBursts::3 73797 # Per bank write bursts -system.physmem.perBankRdBursts::4 73498 # Per bank write bursts -system.physmem.perBankRdBursts::5 82651 # Per bank write bursts -system.physmem.perBankRdBursts::6 70750 # Per bank write bursts -system.physmem.perBankRdBursts::7 70075 # Per bank write bursts -system.physmem.perBankRdBursts::8 62480 # Per bank write bursts -system.physmem.perBankRdBursts::9 88491 # Per bank write bursts -system.physmem.perBankRdBursts::10 66146 # Per bank write bursts -system.physmem.perBankRdBursts::11 72268 # Per bank write bursts -system.physmem.perBankRdBursts::12 67491 # Per bank write bursts -system.physmem.perBankRdBursts::13 74959 # Per bank write bursts -system.physmem.perBankRdBursts::14 69333 # Per bank write bursts -system.physmem.perBankRdBursts::15 65831 # Per bank write bursts -system.physmem.perBankWrBursts::0 122352 # Per bank write bursts -system.physmem.perBankWrBursts::1 129436 # Per bank write bursts -system.physmem.perBankWrBursts::2 124260 # Per bank write bursts -system.physmem.perBankWrBursts::3 131298 # Per bank write bursts -system.physmem.perBankWrBursts::4 127700 # Per bank write bursts -system.physmem.perBankWrBursts::5 133890 # Per bank write bursts -system.physmem.perBankWrBursts::6 125807 # Per bank write bursts -system.physmem.perBankWrBursts::7 124647 # Per bank write bursts -system.physmem.perBankWrBursts::8 116114 # Per bank write bursts -system.physmem.perBankWrBursts::9 124444 # Per bank write bursts -system.physmem.perBankWrBursts::10 122980 # Per bank write bursts -system.physmem.perBankWrBursts::11 126137 # Per bank write bursts -system.physmem.perBankWrBursts::12 123363 # Per bank write bursts -system.physmem.perBankWrBursts::13 128612 # Per bank write bursts -system.physmem.perBankWrBursts::14 126014 # Per bank write bursts -system.physmem.perBankWrBursts::15 124562 # Per bank write bursts +system.physmem.bw_write::total 1892559 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1892124 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 5036 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 4977 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 101456 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1031025 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 495313 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2366 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 1691 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 56525 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 302144 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 272926 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9153 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4174737 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1703042 # Number of read requests accepted +system.physmem.writeReqs 1401261 # Number of write requests accepted +system.physmem.readBursts 1703042 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1401261 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 108957568 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 37120 # Total number of bytes read from write queue +system.physmem.bytesWritten 89535296 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 107969304 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 89536552 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 580 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 222271 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 104244 # Per bank write bursts +system.physmem.perBankRdBursts::1 111881 # Per bank write bursts +system.physmem.perBankRdBursts::2 106230 # Per bank write bursts +system.physmem.perBankRdBursts::3 103315 # Per bank write bursts +system.physmem.perBankRdBursts::4 101355 # Per bank write bursts +system.physmem.perBankRdBursts::5 106401 # Per bank write bursts +system.physmem.perBankRdBursts::6 102755 # Per bank write bursts +system.physmem.perBankRdBursts::7 105565 # Per bank write bursts +system.physmem.perBankRdBursts::8 101297 # Per bank write bursts +system.physmem.perBankRdBursts::9 131029 # Per bank write bursts +system.physmem.perBankRdBursts::10 105406 # Per bank write bursts +system.physmem.perBankRdBursts::11 116947 # Per bank write bursts +system.physmem.perBankRdBursts::12 96908 # Per bank write bursts +system.physmem.perBankRdBursts::13 102973 # Per bank write bursts +system.physmem.perBankRdBursts::14 100156 # Per bank write bursts +system.physmem.perBankRdBursts::15 106000 # Per bank write bursts +system.physmem.perBankWrBursts::0 86649 # Per bank write bursts +system.physmem.perBankWrBursts::1 91854 # Per bank write bursts +system.physmem.perBankWrBursts::2 85255 # Per bank write bursts +system.physmem.perBankWrBursts::3 87156 # Per bank write bursts +system.physmem.perBankWrBursts::4 84624 # Per bank write bursts +system.physmem.perBankWrBursts::5 89053 # Per bank write bursts +system.physmem.perBankWrBursts::6 87549 # Per bank write bursts +system.physmem.perBankWrBursts::7 90107 # Per bank write bursts +system.physmem.perBankWrBursts::8 85432 # Per bank write bursts +system.physmem.perBankWrBursts::9 90372 # Per bank write bursts +system.physmem.perBankWrBursts::10 86508 # Per bank write bursts +system.physmem.perBankWrBursts::11 91779 # Per bank write bursts +system.physmem.perBankWrBursts::12 81073 # Per bank write bursts +system.physmem.perBankWrBursts::13 87139 # Per bank write bursts +system.physmem.perBankWrBursts::14 84132 # Per bank write bursts +system.physmem.perBankWrBursts::15 90307 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 81198 # Number of times write queue was full causing retry -system.physmem.totGap 47385464863500 # Total gap between requests +system.physmem.numWrRetry 40 # Number of times write queue was full causing retry +system.physmem.totGap 47309769886500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 21333 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1124296 # Read request sizes (log2) +system.physmem.readPktSize::6 1681684 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 2057608 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 487455 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 272298 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 106854 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 72030 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 47157 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 39210 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 35683 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 33198 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 29456 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 9611 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 4248 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2678 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1608 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1189 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 723 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 629 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 559 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 455 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 170 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 117 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1398687 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 611880 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 417253 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 192449 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 184576 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 110779 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 65725 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 35828 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 32285 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 29054 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 9028 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 4622 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2923 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1841 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1436 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 897 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 648 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 540 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 418 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 167 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 98 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see @@ -188,136 +188,168 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 29112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 48128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 57284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 64958 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 76298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 77584 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 81647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 91142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 91147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 94824 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 104842 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 97550 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 99736 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 122228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 105767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 99735 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 90681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 12739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 9828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 8966 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 9972 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 10412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 8782 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 8556 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 10053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 8187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 7840 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 7194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 7547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 6708 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 6021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 6115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 5369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 4788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 3634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 3586 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 3218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 2942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 2942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 2916 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 2764 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 2992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 3448 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 3971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 4529 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 7153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 8045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 352485 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1120451 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 180.324302 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 110.099448 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 247.440504 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 698811 62.37% 62.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 221320 19.75% 82.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 61667 5.50% 87.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 27543 2.46% 90.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 21267 1.90% 91.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 12605 1.12% 93.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 9064 0.81% 93.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 8274 0.74% 94.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 59900 5.35% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1120451 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 73379 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 15.608158 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 65.872388 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 73373 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 3 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 73379 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 73379 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.414056 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.095862 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 903.451601 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-4095 73376 100.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::98304-102399 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::102400-106495 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192512-196607 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 73379 # Writes before turning the bus around for reads -system.physmem.totQLat 58866128789 # Total ticks spent queuing -system.physmem.totMemAccLat 80341216289 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5726690000 # Total ticks spent in databus transfers -system.physmem.avgQLat 51396.29 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 19662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 22634 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35927 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 42991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 51483 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 60587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 69980 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 79960 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 85124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 91378 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 92978 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 97068 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 98211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 103646 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 116678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 108732 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 103454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 92841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 7303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 3997 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2565 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1572 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 925 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 663 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 470 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 378 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 469 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 367 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 104 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1072258 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 185.116224 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 114.248094 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 242.173437 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 644445 60.10% 60.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 212244 19.79% 79.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 67795 6.32% 86.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 36826 3.43% 89.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 25524 2.38% 92.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 13957 1.30% 93.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 14880 1.39% 94.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 9207 0.86% 95.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 47380 4.42% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1072258 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 80097 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.254829 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 256.467221 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 80095 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8192-12287 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::69632-73727 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 80097 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 80097 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.466185 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.028138 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 6.338596 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 75079 93.74% 93.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 2441 3.05% 96.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 604 0.75% 97.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 241 0.30% 97.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 302 0.38% 98.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 483 0.60% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 119 0.15% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 48 0.06% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 45 0.06% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 27 0.03% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 34 0.04% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 20 0.02% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 420 0.52% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 48 0.06% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 47 0.06% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 52 0.06% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 14 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 6 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 3 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 6 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 3 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 26 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 7 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::252-255 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 80097 # Writes before turning the bus around for reads +system.physmem.totQLat 88359532056 # Total ticks spent queuing +system.physmem.totMemAccLat 120280694556 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 8512310000 # Total ticks spent in databus transfers +system.physmem.avgQLat 51901.03 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 70146.29 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.55 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.72 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.53 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.78 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 70651.03 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.30 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.89 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.28 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.89 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage -system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.33 # Average write queue length when enqueuing -system.physmem.readRowHits 867894 # Number of row buffer hits during reads -system.physmem.writeRowHits 1168605 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.78 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 58.09 # Row buffer hit rate for writes -system.physmem.avgGap 14781000.92 # Average gap between requests -system.physmem.pageHitRate 64.51 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4336385760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2366083500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4510974000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 6605647200 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3094987836720 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1170067048560 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27404900969250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31687774944990 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.723600 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45590272941113 # Time in different power states -system.physmem_0.memoryStateTime::REF 1582304620000 # Time in different power states +system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.17 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.78 # Average write queue length when enqueuing +system.physmem.readRowHits 1368420 # Number of row buffer hits during reads +system.physmem.writeRowHits 660769 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.38 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 47.23 # Row buffer hit rate for writes +system.physmem.avgGap 15240061.90 # Average gap between requests +system.physmem.pageHitRate 65.43 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4037576760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2203042875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6565556400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4550560560 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3090044124960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1167667097760 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27361592107500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31636660066815 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.713051 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45518112024303 # Time in different power states +system.physmem_0.memoryStateTime::REF 1579777160000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 212884395887 # Time in different power states +system.physmem_0.memoryStateTime::ACT 211880830197 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 4134208680 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2255768625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4422568800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 6429624480 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3094987836720 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1167604821270 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27407060817750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31686895646325 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.705044 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45593855726560 # Time in different power states -system.physmem_1.memoryStateTime::REF 1582304620000 # Time in different power states +system.physmem_1.actEnergy 4068693720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2220021375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 6713584800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4514888160 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3090044124960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1175652112905 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27354587708250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31637801134170 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.737170 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45506397156129 # Time in different power states +system.physmem_1.memoryStateTime::REF 1579777160000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 209300747940 # Time in different power states +system.physmem_1.memoryStateTime::ACT 223594850121 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -351,15 +383,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 143219505 # Number of BP lookups -system.cpu0.branchPred.condPredicted 95215917 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 6874228 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 100849572 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 65904871 # Number of BTB hits +system.cpu0.branchPred.lookups 148829565 # Number of BP lookups +system.cpu0.branchPred.condPredicted 98586451 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 7318222 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 104779817 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 69383898 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 65.349678 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 19505246 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 190029 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 66.218762 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 20536581 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 208145 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -390,88 +422,90 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 557114 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 557114 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 11925 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 88835 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 245678 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 311436 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 1783.814331 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 11278.873416 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-65535 309571 99.40% 99.40% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-131071 1396 0.45% 99.85% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::131072-196607 332 0.11% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::196608-262143 57 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::262144-327679 59 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::327680-393215 14 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::393216-458751 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::458752-524287 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 311436 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 275434 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 16916.133019 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 14128.427647 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 15086.481481 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 261399 94.90% 94.90% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 11343 4.12% 99.02% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-98303 1146 0.42% 99.44% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-131071 802 0.29% 99.73% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 102 0.04% 99.77% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::163840-196607 163 0.06% 99.83% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-229375 287 0.10% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::229376-262143 70 0.03% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-294911 43 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::294912-327679 36 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-360447 22 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::360448-393215 9 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-425983 9 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::425984-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 275434 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 527372589640 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.581951 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.533395 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 526425698140 99.82% 99.82% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 513345500 0.10% 99.92% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 204440500 0.04% 99.96% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 94120000 0.02% 99.97% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 67519500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 37561500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 13535000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 16113500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 245000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::18-19 11000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 527372589640 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 88835 88.16% 88.16% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 11925 11.84% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 100760 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 557114 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 633176 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 633176 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 15593 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 103829 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 293482 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 339694 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 2057.107279 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 12691.149268 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-32767 334819 98.56% 98.56% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::32768-65535 2369 0.70% 99.26% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-98303 775 0.23% 99.49% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::98304-131071 1050 0.31% 99.80% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-163839 325 0.10% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::163840-196607 166 0.05% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::196608-229375 47 0.01% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::229376-262143 24 0.01% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::262144-294911 28 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::294912-327679 54 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::327680-360447 18 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::360448-393215 11 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::425984-458751 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::458752-491519 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::491520-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 339694 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 334006 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 19047.289570 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 15950.264710 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 18217.957975 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 329273 98.58% 98.58% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 3345 1.00% 99.58% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 501 0.15% 99.73% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 607 0.18% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 176 0.05% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 53 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 23 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 15 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 10 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 334006 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 554756829244 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.612373 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.535164 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 553440790244 99.76% 99.76% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 774310500 0.14% 99.90% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 264675000 0.05% 99.95% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 116251500 0.02% 99.97% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 83135500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 43553500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 14917000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 18677500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 518500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 554756829244 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 103830 86.94% 86.94% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 15593 13.06% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 119423 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 633176 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 557114 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 100760 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 633176 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 119423 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 100760 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 657874 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 119423 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 752599 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 103903304 # DTB read hits -system.cpu0.dtb.read_misses 386941 # DTB read misses -system.cpu0.dtb.write_hits 87265042 # DTB write hits -system.cpu0.dtb.write_misses 170173 # DTB write misses +system.cpu0.dtb.read_hits 108615139 # DTB read hits +system.cpu0.dtb.read_misses 465587 # DTB read misses +system.cpu0.dtb.write_hits 88878639 # DTB write hits +system.cpu0.dtb.write_misses 167589 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 44809 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1073 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 37535 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 216 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 6819 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 45077 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1071 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 45162 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 301 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 7481 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 40407 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 104290245 # DTB read accesses -system.cpu0.dtb.write_accesses 87435215 # DTB write accesses +system.cpu0.dtb.perms_faults 44285 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 109080726 # DTB read accesses +system.cpu0.dtb.write_accesses 89046228 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 191168346 # DTB hits -system.cpu0.dtb.misses 557114 # DTB misses -system.cpu0.dtb.accesses 191725460 # DTB accesses +system.cpu0.dtb.hits 197493778 # DTB hits +system.cpu0.dtb.misses 633176 # DTB misses +system.cpu0.dtb.accesses 198126954 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -501,1134 +535,1164 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 85759 # Table walker walks requested -system.cpu0.itb.walker.walksLong 85759 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 908 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 62470 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 9907 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 75852 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1136.575173 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 8938.964276 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-32767 75266 99.23% 99.23% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-65535 257 0.34% 99.57% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-98303 133 0.18% 99.74% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::98304-131071 159 0.21% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::131072-163839 9 0.01% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::163840-196607 8 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::196608-229375 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::229376-262143 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::262144-294911 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::294912-327679 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::327680-360447 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walks 92658 # Table walker walks requested +system.cpu0.itb.walker.walksLong 92658 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1215 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 67279 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 10404 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 82254 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1278.472779 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 8944.038924 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-32767 81396 98.96% 98.96% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-65535 425 0.52% 99.47% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-98303 229 0.28% 99.75% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::98304-131071 180 0.22% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::131072-163839 8 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::163840-196607 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::196608-229375 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::229376-262143 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::294912-327679 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::425984-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 75852 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 73285 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 21415.899529 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 18467.660437 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 19009.032462 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 71796 97.97% 97.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 1220 1.66% 99.63% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 122 0.17% 99.80% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 69 0.09% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 44 0.06% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 20 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 12 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 73285 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 394225556964 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.858766 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.348387 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 55694159292 14.13% 14.13% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 338516533172 85.87% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 13791500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 1055500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 17500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 394225556964 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 62470 98.57% 98.57% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 908 1.43% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 63378 # Table walker page sizes translated +system.cpu0.itb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 82254 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 78898 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 24333.924814 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 20592.654972 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 23297.887242 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 76185 96.56% 96.56% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 2219 2.81% 99.37% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 249 0.32% 99.69% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 140 0.18% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 58 0.07% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 30 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 7 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 6 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 78898 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 417288840772 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.850626 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.356648 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 62357623096 14.94% 14.94% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 354908424176 85.05% 99.99% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 20580000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 1826000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 387500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 417288840772 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 67279 98.23% 98.23% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 1215 1.77% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 68494 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 85759 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 85759 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 92658 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 92658 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 63378 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 63378 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 149137 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 225166936 # ITB inst hits -system.cpu0.itb.inst_misses 85759 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 68494 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 68494 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 161152 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 234838704 # ITB inst hits +system.cpu0.itb.inst_misses 92658 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 44809 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1073 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 26709 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 45077 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1071 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 33056 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 217420 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 232539 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 225252695 # ITB inst accesses -system.cpu0.itb.hits 225166936 # DTB hits -system.cpu0.itb.misses 85759 # DTB misses -system.cpu0.itb.accesses 225252695 # DTB accesses -system.cpu0.numCycles 777590959 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 234931362 # ITB inst accesses +system.cpu0.itb.hits 234838704 # DTB hits +system.cpu0.itb.misses 92658 # DTB misses +system.cpu0.itb.accesses 234931362 # DTB accesses +system.cpu0.numCycles 826354541 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 90148881 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 632830647 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 143219505 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 85410117 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 647310508 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 14846236 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 1771940 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 282653 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 6199385 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 737729 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 721364 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 224948990 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 1718929 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 28705 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 754595578 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.984480 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.221164 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 96417195 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 658349874 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 148829565 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 89920479 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 686511551 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 15731276 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 2082372 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 301509 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 6642770 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 777478 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 876995 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 234604466 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 1859928 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 30773 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 801475508 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.962394 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.215680 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 398817072 52.85% 52.85% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 138444624 18.35% 71.20% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 47562041 6.30% 77.50% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 169771841 22.50% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 432057914 53.91% 53.91% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 143320091 17.88% 71.79% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 50277190 6.27% 78.06% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 175820313 21.94% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 754595578 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.184184 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.813835 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 107688832 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 365256192 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 237731032 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 38638584 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 5280938 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 20683549 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 2184734 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 657953246 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 23988018 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 5280938 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 144086550 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 51798126 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 247348242 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 239349699 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 66732023 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 640403541 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 6134927 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 9593053 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 279391 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 288384 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 30790790 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 11378 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 609803525 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 987601051 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 757009838 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 819226 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 550929032 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 58874487 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 16040201 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 14019715 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 78263207 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 104115554 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 90761559 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 9526213 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 8179417 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 617656959 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 16134834 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 622248752 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 2762846 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 55648828 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 35830856 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 282296 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 754595578 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.824612 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.071196 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 801475508 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.180104 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.796692 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 115405888 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 393574581 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 246061591 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 40857295 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5576153 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 21574429 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 2334934 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 682682220 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 25205347 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5576153 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 153705251 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 60022582 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 253017805 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 248013590 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 81140127 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 664288996 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 6473093 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 10525488 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 404111 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 973821 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 42702914 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 12474 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 634198397 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 1026536806 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 783997445 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 728382 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 571881769 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 62316623 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 17028830 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 14786866 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 82376276 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 108687128 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 92520441 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 9956675 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 8516242 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 640223835 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 17051325 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 645202743 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 2940745 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 58459841 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 38213470 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 295844 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 801475508 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.805019 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.062618 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 416444489 55.19% 55.19% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 139981431 18.55% 73.74% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 120577545 15.98% 89.72% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 69261363 9.18% 98.90% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 8325608 1.10% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 5142 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 449210773 56.05% 56.05% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 147559174 18.41% 74.46% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 124891919 15.58% 90.04% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 71400363 8.91% 98.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 8407753 1.05% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 5526 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 754595578 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 801475508 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 64632492 45.32% 45.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 49764 0.03% 45.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 24321 0.02% 45.37% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.37% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.37% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.37% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.37% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.37% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.37% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.37% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.37% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.37% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.37% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.37% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.37% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.37% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.37% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.37% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.37% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.37% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.37% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.37% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.37% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.37% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.37% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 8 0.00% 45.37% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.37% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.37% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.37% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 36912792 25.88% 71.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 41006253 28.75% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 66711662 45.46% 45.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 70956 0.05% 45.50% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 22678 0.02% 45.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 31 0.00% 45.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 38740309 26.40% 71.92% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 41215825 28.08% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 425093937 68.32% 68.32% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 1435088 0.23% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 72707 0.01% 68.56% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 1 0.00% 68.56% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.56% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.56% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.56% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.56% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.56% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.56% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.56% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.56% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.56% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.56% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.56% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.56% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.56% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.56% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.56% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.56% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.56% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.56% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.56% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.56% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.56% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 80017 0.01% 68.57% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.57% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.57% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.57% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 106973715 17.19% 85.76% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 88593239 14.24% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 441248281 68.39% 68.39% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1607382 0.25% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 84016 0.01% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 12 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 46433 0.01% 68.66% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.66% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.66% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.66% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 111952136 17.35% 86.01% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 90264483 13.99% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 622248752 # Type of FU issued -system.cpu0.iq.rate 0.800226 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 142625630 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.229210 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 2143120412 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 689044772 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 604966692 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 1361144 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 552290 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 506244 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 764032585 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 841796 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 2890526 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 645202743 # Type of FU issued +system.cpu0.iq.rate 0.780782 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 146761461 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.227466 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 2240404538 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 715416173 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 626754280 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 1178660 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 474470 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 433754 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 791232333 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 731871 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 3009936 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 12594321 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 16775 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 157768 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 6060902 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 13422485 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 18059 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 156652 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 6220264 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2889033 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 4437246 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2933130 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5035754 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 5280938 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 6404578 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 3121375 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 633914393 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 5576153 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 8424043 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 6068776 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 657405938 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 104115554 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 90761559 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 13746258 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 66239 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 2987519 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 157768 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 2095186 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 2941806 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 5036992 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 614307958 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 103896068 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 7396426 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 108687128 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 92520441 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 14528017 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 62220 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 5930416 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 156652 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 2211475 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 3142674 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 5354149 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 636790575 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 108609704 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 7786358 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 122600 # number of nop insts executed -system.cpu0.iew.exec_refs 191163401 # number of memory reference insts executed -system.cpu0.iew.exec_branches 115873704 # Number of branches executed -system.cpu0.iew.exec_stores 87267333 # Number of stores executed -system.cpu0.iew.exec_rate 0.790014 # Inst execution rate -system.cpu0.iew.wb_sent 606266119 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 605472936 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 293481694 # num instructions producing a value -system.cpu0.iew.wb_consumers 481488998 # num instructions consuming a value +system.cpu0.iew.exec_nop 130778 # number of nop insts executed +system.cpu0.iew.exec_refs 197486892 # number of memory reference insts executed +system.cpu0.iew.exec_branches 120113448 # Number of branches executed +system.cpu0.iew.exec_stores 88877188 # Number of stores executed +system.cpu0.iew.exec_rate 0.770602 # Inst execution rate +system.cpu0.iew.wb_sent 628006707 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 627188034 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 305309945 # num instructions producing a value +system.cpu0.iew.wb_consumers 500537218 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.778652 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.609529 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.758982 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.609965 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 48614829 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 15852538 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 4732048 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 745378077 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.775637 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.576449 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 51032011 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 16755481 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 5028737 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 791775198 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.756295 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.558039 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 493396348 66.19% 66.19% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 129662648 17.40% 83.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 56044004 7.52% 91.11% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 18992920 2.55% 93.66% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 13761945 1.85% 95.50% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 9179296 1.23% 96.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 6220016 0.83% 97.57% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 3818014 0.51% 98.08% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 14302886 1.92% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 529474510 66.87% 66.87% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 135713871 17.14% 84.01% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 58480062 7.39% 91.40% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 19506672 2.46% 93.86% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 13859320 1.75% 95.61% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 9636766 1.22% 96.83% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 6431343 0.81% 97.64% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 3969096 0.50% 98.14% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 14703558 1.86% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 745378077 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 491403423 # Number of instructions committed -system.cpu0.commit.committedOps 578142958 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 791775198 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 510225692 # Number of instructions committed +system.cpu0.commit.committedOps 598815315 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 176221889 # Number of memory references committed -system.cpu0.commit.loads 91521232 # Number of loads committed -system.cpu0.commit.membars 3904419 # Number of memory barriers committed -system.cpu0.commit.branches 110044339 # Number of branches committed -system.cpu0.commit.fp_insts 493876 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 530522943 # Number of committed integer instructions. -system.cpu0.commit.function_calls 14584303 # Number of function calls committed. +system.cpu0.commit.refs 181564818 # Number of memory references committed +system.cpu0.commit.loads 95264643 # Number of loads committed +system.cpu0.commit.membars 4026241 # Number of memory barriers committed +system.cpu0.commit.branches 114090927 # Number of branches committed +system.cpu0.commit.fp_insts 424114 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 549390032 # Number of committed integer instructions. +system.cpu0.commit.function_calls 15322892 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 400598379 69.29% 69.29% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 1193753 0.21% 69.50% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 57671 0.01% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 8 0.00% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 13 0.00% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 21 0.00% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 71224 0.01% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 91521232 15.83% 85.35% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 84700657 14.65% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 415791168 69.44% 69.44% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1352857 0.23% 69.66% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 66520 0.01% 69.67% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.67% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.67% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.67% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.67% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.67% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 39952 0.01% 69.68% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.68% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.68% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.68% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 95264643 15.91% 85.59% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 86300175 14.41% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 578142958 # Class of committed instruction -system.cpu0.commit.bw_lim_events 14302886 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 1353470869 # The number of ROB reads -system.cpu0.rob.rob_writes 1262695982 # The number of ROB writes -system.cpu0.timesIdled 1015060 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 22995381 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 93993341722 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 491403423 # Number of Instructions Simulated -system.cpu0.committedOps 578142958 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.582388 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.582388 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.631956 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.631956 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 725839901 # number of integer regfile reads -system.cpu0.int_regfile_writes 430463320 # number of integer regfile writes -system.cpu0.fp_regfile_reads 805500 # number of floating regfile reads -system.cpu0.fp_regfile_writes 450680 # number of floating regfile writes -system.cpu0.cc_regfile_reads 133543353 # number of cc regfile reads -system.cpu0.cc_regfile_writes 134332816 # number of cc regfile writes -system.cpu0.misc_regfile_reads 1348291201 # number of misc regfile reads -system.cpu0.misc_regfile_writes 16059632 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 6141043 # number of replacements -system.cpu0.dcache.tags.tagsinuse 503.422627 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 163818652 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 6141554 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 26.673811 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 1929842500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 503.422627 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.983247 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.983247 # Average percentage of cache occupancy +system.cpu0.commit.op_class_0::total 598815315 # Class of committed instruction +system.cpu0.commit.bw_lim_events 14703558 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 1422522153 # The number of ROB reads +system.cpu0.rob.rob_writes 1309355495 # The number of ROB writes +system.cpu0.timesIdled 1107002 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 24879033 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 93793188049 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 510225692 # Number of Instructions Simulated +system.cpu0.committedOps 598815315 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.619586 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.619586 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.617442 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.617442 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 751256572 # number of integer regfile reads +system.cpu0.int_regfile_writes 446675945 # number of integer regfile writes +system.cpu0.fp_regfile_reads 709287 # number of floating regfile reads +system.cpu0.fp_regfile_writes 346140 # number of floating regfile writes +system.cpu0.cc_regfile_reads 138932349 # number of cc regfile reads +system.cpu0.cc_regfile_writes 139558794 # number of cc regfile writes +system.cpu0.misc_regfile_reads 1422736351 # number of misc regfile reads +system.cpu0.misc_regfile_writes 16846265 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 6557508 # number of replacements +system.cpu0.dcache.tags.tagsinuse 508.746857 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 168230159 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 6558019 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 25.652588 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 1887096000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 508.746857 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.993646 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.993646 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 366 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 40 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 174 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 302 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 35 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 365108655 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 365108655 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 84789793 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 84789793 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 73815215 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 73815215 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 223529 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 223529 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 254722 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 254722 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1935633 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1935633 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1977053 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1977053 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 158605008 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 158605008 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 158828537 # number of overall hits -system.cpu0.dcache.overall_hits::total 158828537 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 6791004 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 6791004 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 7631461 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 7631461 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 739012 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 739012 # number of SoftPFReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 806083 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 806083 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 273207 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 273207 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 195599 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 195599 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 14422465 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 14422465 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 15161477 # number of overall misses -system.cpu0.dcache.overall_misses::total 15161477 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 101570086088 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 101570086088 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 139050346077 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 139050346077 # number of WriteReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 37625975422 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 37625975422 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 3995007021 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 3995007021 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4127543324 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4127543324 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2928500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2928500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 240620432165 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 240620432165 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 240620432165 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 240620432165 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 91580797 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 91580797 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 81446676 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 81446676 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 962541 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 962541 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1060805 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 1060805 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2208840 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2208840 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2172652 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2172652 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 173027473 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 173027473 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 173990014 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 173990014 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.074153 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.074153 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.093699 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.093699 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.767772 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.767772 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.759879 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.759879 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.123688 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.123688 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.090028 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.090028 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.083354 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.083354 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.087140 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.087140 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14956.564020 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14956.564020 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18220.671779 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 18220.671779 # average WriteReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 46677.544896 # average WriteInvalidateReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 46677.544896 # average WriteInvalidateReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14622.637857 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14622.637857 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21102.067618 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21102.067618 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 376736198 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 376736198 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 88222232 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 88222232 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 74841943 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 74841943 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 232729 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 232729 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 258353 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 258353 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1906592 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1906592 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1977838 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1977838 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 163064175 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 163064175 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 163296904 # number of overall hits +system.cpu0.dcache.overall_hits::total 163296904 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 7298679 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 7298679 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 8186484 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 8186484 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 785305 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 785305 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 832077 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 832077 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 303324 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 303324 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 192936 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 192936 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 15485163 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 15485163 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 16270468 # number of overall misses +system.cpu0.dcache.overall_misses::total 16270468 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 111692276000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 111692276000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 148685242611 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 148685242611 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 79029404267 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 79029404267 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4531612500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 4531612500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4045324000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4045324000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3600000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3600000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 260377518611 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 260377518611 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 260377518611 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 260377518611 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 95520911 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 95520911 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 83028427 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 83028427 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 1018034 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 1018034 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1090430 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 1090430 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2209916 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2209916 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2170774 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2170774 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 178549338 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 178549338 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 179567372 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 179567372 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.076409 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.076409 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.098599 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.098599 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.771394 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.771394 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.763072 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.763072 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.137256 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.137256 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.088879 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.088879 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.086728 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.086728 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.090609 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.090609 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15303.081010 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15303.081010 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18162.283419 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 18162.283419 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 94978.474669 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 94978.474669 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14939.841556 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14939.841556 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 20967.180827 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 20967.180827 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16683.724465 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 16683.724465 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15870.513946 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 15870.513946 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 10994171 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 20243365 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 733732 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 746062 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.983906 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 27.133623 # average number of cycles each access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16814.645000 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 16814.645000 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16003.074934 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 16003.074934 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 24592023 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 22766928 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 764014 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 809850 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 32.187922 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 28.112525 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 4196368 # number of writebacks -system.cpu0.dcache.writebacks::total 4196368 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3475469 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 3475469 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6119501 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 6119501 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 4173 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 4173 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 141236 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 141236 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 9594970 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 9594970 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 9594970 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 9594970 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3315535 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3315535 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1511960 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1511960 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 732291 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 732291 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 801910 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 801910 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 131971 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 131971 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 195594 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 195594 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 4827495 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 4827495 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5559786 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5559786 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31767 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31767 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 31179 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 31179 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 62946 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 62946 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 45402822425 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 45402822425 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 28839272084 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 28839272084 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 16627256811 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 16627256811 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 36253693272 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 36253693272 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1734403771 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1734403771 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3825076676 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3825076676 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2835500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2835500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 74242094509 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 74242094509 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 90869351320 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 90869351320 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5616435750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5616435750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5304462017 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5304462017 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10920897767 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10920897767 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036203 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036203 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018564 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018564 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.760789 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.760789 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.755945 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.755945 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059747 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059747 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.090025 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.090025 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027900 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.027900 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031955 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.031955 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13693.965657 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13693.965657 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19074.097254 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19074.097254 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22705.805221 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22705.805221 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 45209.179674 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 45209.179674 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13142.309833 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13142.309833 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19556.206612 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19556.206612 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 4422416 # number of writebacks +system.cpu0.dcache.writebacks::total 4422416 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3749707 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 3749707 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6590276 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 6590276 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4547 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 4547 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 153940 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 153940 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 10339983 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 10339983 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 10339983 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 10339983 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3548972 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3548972 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1596208 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1596208 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 778051 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 778051 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 827530 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 827530 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 149384 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 149384 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 192928 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 192928 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 5145180 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 5145180 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5923231 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5923231 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20289 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20289 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 22269 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 22269 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 42558 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 42558 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 52135719000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 52135719000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 31476098425 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 31476098425 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 17784168000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 17784168000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 78021331267 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 78021331267 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 2035314000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 2035314000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3852473000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3852473000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3523000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3523000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 83611817425 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 83611817425 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 101395985425 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 101395985425 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3695888000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3695888000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3839366000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3839366000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7535254000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7535254000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037154 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037154 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019225 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019225 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.764268 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.764268 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.758902 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.758902 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.067597 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.067597 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.088875 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.088875 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028817 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028817 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032986 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032986 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14690.372029 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14690.372029 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19719.296248 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19719.296248 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22857.329404 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22857.329404 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 94282.178612 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 94282.178612 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13624.712151 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13624.712151 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19968.449370 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19968.449370 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15379.010130 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15379.010130 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16344.037580 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16344.037580 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 176800.949098 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 176800.949098 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170129.318355 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 170129.318355 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 173496.294713 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 173496.294713 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16250.513573 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16250.513573 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17118.357434 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17118.357434 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182162.156834 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 182162.156834 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 172408.550002 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172408.550002 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 177058.461394 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 177058.461394 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 6182706 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.960451 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 218406038 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 6183218 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 35.322390 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 14060425250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.960451 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999923 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999923 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 6585231 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.955630 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 227602766 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 6585743 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 34.559922 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 17287340000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.955630 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999913 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999913 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 346 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 53 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 310 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 110 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 456025787 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 456025787 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 218406038 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 218406038 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 218406038 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 218406038 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 218406038 # number of overall hits -system.cpu0.icache.overall_hits::total 218406038 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 6515233 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 6515233 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 6515233 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 6515233 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 6515233 # number of overall misses -system.cpu0.icache.overall_misses::total 6515233 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 69121769887 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 69121769887 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 69121769887 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 69121769887 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 69121769887 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 69121769887 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 224921271 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 224921271 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 224921271 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 224921271 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 224921271 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 224921271 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028967 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.028967 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028967 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.028967 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.028967 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.028967 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10609.255246 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10609.255246 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10609.255246 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10609.255246 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10609.255246 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10609.255246 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 9343070 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 429 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 716553 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.038910 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 47.666667 # average number of cycles each access was blocked +system.cpu0.icache.tags.tag_accesses 475737897 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 475737897 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 227602766 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 227602766 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 227602766 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 227602766 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 227602766 # number of overall hits +system.cpu0.icache.overall_hits::total 227602766 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 6973294 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 6973294 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 6973294 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 6973294 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 6973294 # number of overall misses +system.cpu0.icache.overall_misses::total 6973294 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 74030582287 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 74030582287 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 74030582287 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 74030582287 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 74030582287 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 74030582287 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 234576060 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 234576060 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 234576060 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 234576060 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 234576060 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 234576060 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029727 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.029727 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029727 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.029727 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029727 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.029727 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10616.300171 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10616.300171 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10616.300171 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10616.300171 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10616.300171 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10616.300171 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 10890869 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 530 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 815898 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 10 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.348322 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 53 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 331988 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 331988 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 331988 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 331988 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 331988 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 331988 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6183245 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 6183245 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 6183245 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 6183245 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 6183245 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 6183245 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 387516 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 387516 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 387516 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 387516 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 387516 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 387516 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6585778 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 6585778 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 6585778 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 6585778 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 6585778 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 6585778 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 21294 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 21294 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 21294 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 21294 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 59487086557 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 59487086557 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 59487086557 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 59487086557 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 59487086557 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 59487086557 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1881164498 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1881164498 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1881164498 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 1881164498 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027491 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027491 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027491 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.027491 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027491 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.027491 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9620.690520 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9620.690520 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9620.690520 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 9620.690520 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9620.690520 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 9620.690520 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88342.467268 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88342.467268 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88342.467268 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88342.467268 # average overall mshr uncacheable latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 67014306188 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 67014306188 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 67014306188 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 67014306188 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 67014306188 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 67014306188 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1863746498 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1863746498 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1863746498 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 1863746498 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028075 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028075 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028075 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.028075 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028075 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.028075 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10175.609653 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10175.609653 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10175.609653 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10175.609653 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10175.609653 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10175.609653 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87524.490373 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 87524.490373 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87524.490373 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 87524.490373 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 7927934 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 8230587 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 262068 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 8598962 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 8934370 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 290328 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 1052933 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 2785828 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16244.844688 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 12810731 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2801890 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 4.572175 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 2265530500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 7084.641278 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 80.581753 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 91.908936 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4232.509595 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3861.356831 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 893.846295 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.432412 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004918 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.005610 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.258332 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.235679 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.054556 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.991507 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1296 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 85 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14681 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 27 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 251 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 612 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 406 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 47 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 20 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 17 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 140 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1442 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5343 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4502 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3254 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.079102 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005188 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.896057 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 290229122 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 290229122 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 541748 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 180817 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 5534153 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 3094433 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 9351151 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 4196351 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 4196351 # number of Writeback hits -system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 207942 # number of WriteInvalidateReq hits -system.cpu0.l2cache.WriteInvalidateReq_hits::total 207942 # number of WriteInvalidateReq hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 120308 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 120308 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 36466 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 36466 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 968728 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 968728 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 541748 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 180817 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 5534153 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 4063161 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 10319879 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 541748 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 180817 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 5534153 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 4063161 # number of overall hits -system.cpu0.l2cache.overall_hits::total 10319879 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 12343 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 9059 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 649075 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 1080475 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 1750952 # number of ReadReq misses -system.cpu0.l2cache.Writeback_misses::writebacks 10 # number of Writeback misses -system.cpu0.l2cache.Writeback_misses::total 10 # number of Writeback misses -system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 592445 # number of WriteInvalidateReq misses -system.cpu0.l2cache.WriteInvalidateReq_misses::total 592445 # number of WriteInvalidateReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 136302 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 136302 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 159123 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 159123 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 5 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 299943 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 299943 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 12343 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 9059 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 649075 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 1380418 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 2050895 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 12343 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 9059 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 649075 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 1380418 # number of overall misses -system.cpu0.l2cache.overall_misses::total 2050895 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 496433453 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 403677084 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 20306210078 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 39087285353 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 60293605968 # number of ReadReq miss cycles -system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data 252817543 # number of WriteInvalidateReq miss cycles -system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total 252817543 # number of WriteInvalidateReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2986484321 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 2986484321 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3304695138 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3304695138 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2772999 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2772999 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 16034165055 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 16034165055 # number of ReadExReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 496433453 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 403677084 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 20306210078 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 55121450408 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 76327771023 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 496433453 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 403677084 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 20306210078 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 55121450408 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 76327771023 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 554091 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 189876 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 6183228 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 4174908 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 11102103 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 4196361 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 4196361 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 800387 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.l2cache.WriteInvalidateReq_accesses::total 800387 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 256610 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 256610 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 195589 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 195589 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 5 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1268671 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 1268671 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 554091 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 189876 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 6183228 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 5443579 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 12370774 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 554091 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 189876 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 6183228 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 5443579 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 12370774 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.022276 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.047710 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.104973 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.258802 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.157714 # miss rate for ReadReq accesses -system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000002 # miss rate for Writeback accesses -system.cpu0.l2cache.Writeback_miss_rate::total 0.000002 # miss rate for Writeback accesses -system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.740198 # miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.740198 # miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.531164 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.531164 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.813558 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.813558 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.prefetcher.pfSpanPage 1159342 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 3030105 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16246.172494 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 22237347 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 3045780 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 7.301035 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 15974403000 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 7087.125273 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 75.689704 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 100.487660 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4186.697540 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3865.106436 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 931.065881 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.432564 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004620 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.006133 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.255536 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.235907 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.056828 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.991588 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1420 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 100 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14155 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 86 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 252 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 649 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 433 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 77 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 11 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 206 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 782 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4799 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4726 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3642 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.086670 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.006104 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.863953 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 448543088 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 448543088 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 611768 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 192592 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 804360 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 4422408 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 4422408 # number of Writeback hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 116889 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 116889 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 39729 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 39729 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 1062033 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 1062033 # number of ReadExReq hits +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5870980 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadCleanReq_hits::total 5870980 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3339122 # number of ReadSharedReq hits +system.cpu0.l2cache.ReadSharedReq_hits::total 3339122 # number of ReadSharedReq hits +system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 194533 # number of InvalidateReq hits +system.cpu0.l2cache.InvalidateReq_hits::total 194533 # number of InvalidateReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 611768 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 192592 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 5870980 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 4401155 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 11076495 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 611768 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 192592 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 5870980 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 4401155 # number of overall hits +system.cpu0.l2cache.overall_hits::total 11076495 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 14162 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 11237 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 25399 # number of ReadReq misses +system.cpu0.l2cache.Writeback_misses::writebacks 6 # number of Writeback misses +system.cpu0.l2cache.Writeback_misses::total 6 # number of Writeback misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 131236 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 131236 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 153191 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 153191 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 8 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::total 8 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 296814 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 296814 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 714775 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 714775 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1134930 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 1134930 # number of ReadSharedReq misses +system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 631728 # number of InvalidateReq misses +system.cpu0.l2cache.InvalidateReq_misses::total 631728 # number of InvalidateReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 14162 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 11237 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 714775 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 1431744 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 2171918 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 14162 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 11237 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 714775 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 1431744 # number of overall misses +system.cpu0.l2cache.overall_misses::total 2171918 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 627635500 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 557924000 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 1185559500 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2881179498 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 2881179498 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3211389999 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3211389999 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 3406498 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 3406498 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 17257972999 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 17257972999 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 22144079998 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::total 22144079998 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 43103483484 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::total 43103483484 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 74596156500 # number of InvalidateReq miss cycles +system.cpu0.l2cache.InvalidateReq_miss_latency::total 74596156500 # number of InvalidateReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 627635500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 557924000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 22144079998 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 60361456483 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 83691095981 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 627635500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 557924000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 22144079998 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 60361456483 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 83691095981 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 625930 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 203829 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 829759 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 4422414 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 4422414 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 248125 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 248125 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 192920 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 192920 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 8 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 8 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1358847 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 1358847 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 6585755 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::total 6585755 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4474052 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::total 4474052 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 826261 # number of InvalidateReq accesses(hits+misses) +system.cpu0.l2cache.InvalidateReq_accesses::total 826261 # number of InvalidateReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 625930 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 203829 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 6585755 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 5832899 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 13248413 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 625930 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 203829 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 6585755 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 5832899 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 13248413 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.022626 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.055130 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.030610 # miss rate for ReadReq accesses +system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000001 # miss rate for Writeback accesses +system.cpu0.l2cache.Writeback_miss_rate::total 0.000001 # miss rate for Writeback accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.528911 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.528911 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.794065 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.794065 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.236423 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.236423 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.022276 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.047710 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.104973 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.253586 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.165786 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.022276 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.047710 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.104973 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.253586 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.165786 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 40219.837398 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 44560.887957 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 31284.843936 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 36176.020133 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 34434.756617 # average ReadReq miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.data 426.735888 # average WriteInvalidateReq miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total 426.735888 # average WriteInvalidateReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21910.788697 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21910.788697 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20768.180200 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20768.180200 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 554599.800000 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 554599.800000 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 53457.373751 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 53457.373751 # average ReadExReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 40219.837398 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 44560.887957 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 31284.843936 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 39930.984968 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 37216.810721 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 40219.837398 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 44560.887957 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 31284.843936 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 39930.984968 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 37216.810721 # average overall miss latency -system.cpu0.l2cache.blocked_cycles::no_mshrs 70 # number of cycles access was blocked +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.218431 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.218431 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.108533 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.108533 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.253669 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.253669 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.764562 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.764562 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.022626 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.055130 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.108533 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.245460 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.163938 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.022626 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.055130 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.108533 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.245460 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.163938 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 44318.281316 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 49650.618492 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 46677.408559 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21954.185574 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21954.185574 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20963.307237 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20963.307237 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 425812.250000 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 425812.250000 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 58144.066651 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 58144.066651 # average ReadExReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 30980.490361 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 30980.490361 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 37978.979747 # average ReadSharedReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 37978.979747 # average ReadSharedReq miss latency +system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 118082.713605 # average InvalidateReq miss latency +system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 118082.713605 # average InvalidateReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 44318.281316 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 49650.618492 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 30980.490361 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42159.391960 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 38533.266901 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 44318.281316 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 49650.618492 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 30980.490361 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42159.391960 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 38533.266901 # average overall miss latency +system.cpu0.l2cache.blocked_cycles::no_mshrs 232 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu0.l2cache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 35 # average number of cycles each access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 77.333333 # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 1537125 # number of writebacks -system.cpu0.l2cache.writebacks::total 1537125 # number of writebacks -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 3 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 146 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 10 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 4037 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::total 4196 # number of ReadReq MSHR hits -system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::cpu0.data 18 # number of WriteInvalidateReq MSHR hits -system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::total 18 # number of WriteInvalidateReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 22490 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 22490 # number of ReadExReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 3 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 146 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 10 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 26527 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 26686 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 3 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 146 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 10 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 26527 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 26686 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 12340 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8913 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 649065 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 1076438 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 1746756 # number of ReadReq MSHR misses -system.cpu0.l2cache.Writeback_mshr_misses::writebacks 10 # number of Writeback MSHR misses -system.cpu0.l2cache.Writeback_mshr_misses::total 10 # number of Writeback MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 790245 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 790245 # number of HardPFReq MSHR misses -system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.data 592427 # number of WriteInvalidateReq MSHR misses -system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total 592427 # number of WriteInvalidateReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 136302 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 136302 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 159123 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 159123 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 5 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 277453 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 277453 # number of ReadExReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 12340 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8913 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 649065 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1353891 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 2024209 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 12340 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8913 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 649065 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1353891 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 790245 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 2814454 # number of overall MSHR misses +system.cpu0.l2cache.writebacks::writebacks 1656758 # number of writebacks +system.cpu0.l2cache.writebacks::total 1656758 # number of writebacks +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 4 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 144 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::total 148 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 25414 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 25414 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 4 # number of ReadCleanReq MSHR hits +system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 4 # number of ReadCleanReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 5426 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 5426 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 23 # number of InvalidateReq MSHR hits +system.cpu0.l2cache.InvalidateReq_mshr_hits::total 23 # number of InvalidateReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 4 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 144 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 30840 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 30992 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 4 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 144 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 30840 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 30992 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 14158 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 11093 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 25251 # number of ReadReq MSHR misses +system.cpu0.l2cache.Writeback_mshr_misses::writebacks 6 # number of Writeback MSHR misses +system.cpu0.l2cache.Writeback_mshr_misses::total 6 # number of Writeback MSHR misses +system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 124422 # number of CleanEvict MSHR misses +system.cpu0.l2cache.CleanEvict_mshr_misses::total 124422 # number of CleanEvict MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 859401 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 859401 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 131236 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 131236 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 153191 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 153191 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 8 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 8 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 271400 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 271400 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 714771 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 714771 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1129504 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1129504 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 631705 # number of InvalidateReq MSHR misses +system.cpu0.l2cache.InvalidateReq_mshr_misses::total 631705 # number of InvalidateReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 14158 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 11093 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 714771 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1400904 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 2140926 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 14158 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 11093 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 714771 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1400904 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 859401 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 3000327 # number of overall MSHR misses system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 21294 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31767 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 53061 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 31179 # number of WriteReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 31179 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 20289 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 41583 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 22269 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 22269 # number of WriteReq MSHR uncacheable system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 21294 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 62946 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 84240 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 415403075 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 337276526 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 16064432920 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 31701439881 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 48518552402 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 48655967065 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 48655967065 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 28919407002 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 28919407002 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2740989495 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2740989495 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2358203392 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2358203392 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2369999 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2369999 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 11491009195 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 11491009195 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 415403075 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 337276526 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 16064432920 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 43192449076 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 60009561597 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 415403075 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 337276526 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 16064432920 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 43192449076 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 48655967065 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 108665528662 # number of overall MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1711512000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5362208750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7073720750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5065245463 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5065245463 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1711512000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10427454213 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12138966213 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.022271 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.046941 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.104972 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.257835 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.157336 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000002 # mshr miss rate for Writeback accesses -system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000002 # mshr miss rate for Writeback accesses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 42558 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 63852 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 542595500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 483807000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 1026402500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 56082760333 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 56082760333 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2730207494 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2730207494 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2385366995 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2385366995 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2944498 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2944498 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 12497558999 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 12497558999 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 17855117998 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 17855117998 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 35928472484 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 35928472484 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 70805243000 # number of InvalidateReq MSHR miss cycles +system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 70805243000 # number of InvalidateReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 542595500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 483807000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 17855117998 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 48426031483 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 67307551981 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 542595500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 483807000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 17855117998 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 48426031483 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 56082760333 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 123390312314 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1704040500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 3533504500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5237545000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3666920967 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3666920967 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1704040500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7200425467 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 8904465967 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.022619 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.054423 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.030432 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for Writeback accesses +system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000001 # mshr miss rate for Writeback accesses +system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.740176 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.740176 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.531164 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.531164 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.813558 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.813558 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.528911 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.528911 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.794065 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.794065 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.218696 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.218696 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.022271 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.046941 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.104972 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.248713 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.163628 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.022271 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.046941 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.104972 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.248713 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.199728 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.199728 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.108533 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.108533 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.252457 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.252457 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.764534 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.764534 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.022619 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.054423 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.108533 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.240173 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.161599 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.022619 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.054423 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.108533 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.240173 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.227508 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 33663.134117 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 37840.965556 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24750.114272 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 29450.316582 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 27776.376553 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 61570.737006 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 61570.737006 # average HardPFReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 48815.140097 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 48815.140097 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20109.679205 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20109.679205 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14820.003343 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14820.003343 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 473999.800000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 473999.800000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41416.056756 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41416.056756 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 33663.134117 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 37840.965556 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24750.114272 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 31902.456753 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 29645.931619 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 33663.134117 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 37840.965556 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24750.114272 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 31902.456753 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 61570.737006 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38609.808035 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80375.316991 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 168798.084490 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 133312.993536 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162456.957022 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162456.957022 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80375.316991 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 165657.138071 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 144099.788853 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.226467 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 38324.304280 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 43613.720364 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 40647.994139 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65257.964947 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 65257.964947 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20803.799979 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20803.799979 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15571.195403 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15571.195403 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 368062.250000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 368062.250000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 46048.485626 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 46048.485626 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 24980.193654 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 24980.193654 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 31809.070604 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31809.070604 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 112085.930933 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 112085.930933 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 38324.304280 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 43613.720364 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24980.193654 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34567.701629 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31438.523322 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 38324.304280 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 43613.720364 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24980.193654 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34567.701629 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65257.964947 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 41125.621412 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80024.443505 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 174158.632757 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 125953.995623 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164664.824060 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 164664.824060 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80024.443505 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 169190.879905 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 139454.769890 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 13667246 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 11407678 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 38779 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 31179 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 4196361 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 1120333 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 10 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1176973 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 800387 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 496358 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 355576 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 523512 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 86 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 143 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1407436 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1277584 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 12409061 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17898439 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 414925 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1222034 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 31944459 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 396067296 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 675577736 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1519008 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4432728 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1077596768 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 4739028 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 22459193 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 1.235945 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.424588 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 1048889 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 12194005 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 38264 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 22269 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 8425423 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 11622390 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1249461 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 495211 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 344893 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 512947 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 79 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 148 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1710859 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1368930 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6585778 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 6660291 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 932989 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 826261 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 19798041 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 21027852 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 446745 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1372185 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 42644823 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 421828960 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 663719558 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1630632 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 5007440 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1092186590 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 11579815 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 39116658 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 1.312501 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.463513 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 17160060 76.41% 76.41% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 5299133 23.59% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 26892655 68.75% 68.75% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 12224003 31.25% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 22459193 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 14039414488 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 39116658 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 18374497429 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 204401970 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 206346476 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 9316604024 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 9904865164 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 8912883405 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 9419389746 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 225880552 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 243194937 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 669143268 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 746720066 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 128543512 # Number of BP lookups -system.cpu1.branchPred.condPredicted 85865577 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 6421624 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 90850028 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 59627534 # Number of BTB hits +system.cpu1.branchPred.lookups 121710225 # Number of BP lookups +system.cpu1.branchPred.condPredicted 81714662 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 5979961 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 85476181 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 55576245 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 65.632929 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 17292026 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 181846 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 65.019570 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 16076930 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 165894 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1658,83 +1722,83 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 599268 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 599268 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 13824 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 99235 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 280644 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 318624 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 1973.247464 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 12034.928654 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-65535 316338 99.28% 99.28% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-131071 1742 0.55% 99.83% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::131072-196607 377 0.12% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::196608-262143 71 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::262144-327679 83 0.03% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::327680-393215 7 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::393216-458751 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walks 527361 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 527361 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10839 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 84415 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 237711 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 289650 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 2083.972035 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 12311.346834 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-65535 287768 99.35% 99.35% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-131071 1260 0.44% 99.79% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-196607 464 0.16% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::196608-262143 78 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::262144-327679 55 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::327680-393215 21 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::393216-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 318624 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 319817 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 17305.058052 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 14691.969456 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 15678.724582 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 316762 99.04% 99.04% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 2191 0.69% 99.73% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 345 0.11% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 267 0.08% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 157 0.05% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 61 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 16 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 8 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 10 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 319817 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 467242764496 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.609754 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.540089 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-1 466086530996 99.75% 99.75% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2-3 677505500 0.15% 99.90% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-5 222526000 0.05% 99.95% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6-7 100711000 0.02% 99.97% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-9 81855500 0.02% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10-11 40422000 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-13 15395000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14-15 17231500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-17 579500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::18-19 7500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 467242764496 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 99236 87.77% 87.77% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 13824 12.23% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 113060 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 599268 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 289650 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 263786 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 17712.334999 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 15356.267972 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 12186.421874 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 262356 99.46% 99.46% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1127 0.43% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 155 0.06% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 73 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 35 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 26 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 9 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 263786 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 425904638364 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.594204 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.544845 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-1 424921434364 99.77% 99.77% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2-3 524417000 0.12% 99.89% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-5 206354500 0.05% 99.94% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6-7 102255000 0.02% 99.96% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-9 73118500 0.02% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10-11 43959500 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-13 13868000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14-15 18884000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-17 347500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 425904638364 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 84415 88.62% 88.62% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 10839 11.38% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 95254 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 527361 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 599268 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 113060 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 527361 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 95254 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 113060 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 712328 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 95254 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 622615 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 95146273 # DTB read hits -system.cpu1.dtb.read_misses 436726 # DTB read misses -system.cpu1.dtb.write_hits 76756681 # DTB write hits -system.cpu1.dtb.write_misses 162542 # DTB write misses +system.cpu1.dtb.read_hits 90076123 # DTB read hits +system.cpu1.dtb.read_misses 364024 # DTB read misses +system.cpu1.dtb.write_hits 74326349 # DTB write hits +system.cpu1.dtb.write_misses 163337 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 44809 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1073 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 41064 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 604 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 6738 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 45077 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1071 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 33241 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 185 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 5418 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 39860 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 95582999 # DTB read accesses -system.cpu1.dtb.write_accesses 76919223 # DTB write accesses +system.cpu1.dtb.perms_faults 36861 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 90440147 # DTB read accesses +system.cpu1.dtb.write_accesses 74489686 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 171902954 # DTB hits -system.cpu1.dtb.misses 599268 # DTB misses -system.cpu1.dtb.accesses 172502222 # DTB accesses +system.cpu1.dtb.hits 164402472 # DTB hits +system.cpu1.dtb.misses 527361 # DTB misses +system.cpu1.dtb.accesses 164929833 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1764,1128 +1828,1155 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 83675 # Table walker walks requested -system.cpu1.itb.walker.walksLong 83675 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 922 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 60249 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 9641 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 74034 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 1137.571926 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 8570.962609 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-32767 73376 99.11% 99.11% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-65535 334 0.45% 99.56% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-98303 142 0.19% 99.75% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::98304-131071 157 0.21% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::131072-163839 4 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::163840-196607 7 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::196608-229375 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::229376-262143 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::262144-294911 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::294912-327679 4 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 74034 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 70812 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 21947.603838 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 18689.139556 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 20589.258424 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 68933 97.35% 97.35% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 1547 2.18% 99.53% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 153 0.22% 99.75% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 111 0.16% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 33 0.05% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 27 0.04% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 4 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 77446 # Table walker walks requested +system.cpu1.itb.walker.walksLong 77446 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 594 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 55102 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 9325 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 68121 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1127.809339 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 8184.124599 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-65535 67907 99.69% 99.69% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-131071 190 0.28% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::131072-196607 8 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::196608-262143 12 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::262144-327679 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 68121 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 65021 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 21947.540026 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 19801.580238 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 14876.528667 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 64283 98.86% 98.86% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 594 0.91% 99.78% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 78 0.12% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 35 0.05% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 16 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 7 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 5 0.01% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 70812 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 419972060240 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.852209 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.355033 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 62087724216 14.78% 14.78% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 357865938524 85.21% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 17105000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 1290000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 2500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 419972060240 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 60249 98.49% 98.49% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 922 1.51% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 61171 # Table walker page sizes translated +system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 65021 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 387249857200 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.854665 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.352569 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 56297043096 14.54% 14.54% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 330938122104 85.46% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 13360500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 1244000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 37500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::5 50000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 387249857200 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 55102 98.93% 98.93% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 594 1.07% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 55696 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 83675 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 83675 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 77446 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 77446 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 61171 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 61171 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 144846 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 203060553 # ITB inst hits -system.cpu1.itb.inst_misses 83675 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55696 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55696 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 133142 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 191622824 # ITB inst hits +system.cpu1.itb.inst_misses 77446 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 44809 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1073 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 29792 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 45077 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1071 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 23450 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 217868 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 204512 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 203144228 # ITB inst accesses -system.cpu1.itb.hits 203060553 # DTB hits -system.cpu1.itb.misses 83675 # DTB misses -system.cpu1.itb.accesses 203144228 # DTB accesses -system.cpu1.numCycles 689224896 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 191700270 # ITB inst accesses +system.cpu1.itb.hits 191622824 # DTB hits +system.cpu1.itb.misses 77446 # DTB misses +system.cpu1.itb.accesses 191700270 # DTB accesses +system.cpu1.numCycles 652098782 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 83111859 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 570743281 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 128543512 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 76919560 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 571668142 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 13828506 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 1777982 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 253475 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 6260799 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 781198 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 699050 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 202821648 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 1630400 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 27635 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 671466758 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.996773 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.223843 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 77581821 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 539946872 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 121710225 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 71653175 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 543040637 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 12931684 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 1632229 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 244335 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 5898534 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 685251 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 721414 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 191398691 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 1512045 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 26398 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 636270063 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.997205 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.224602 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 351036099 52.28% 52.28% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 124470987 18.54% 70.82% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 43050208 6.41% 77.23% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 152909464 22.77% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 332513921 52.26% 52.26% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 118489139 18.62% 70.88% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 39798398 6.25% 77.14% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 145468605 22.86% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 671466758 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.186504 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.828094 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 100354838 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 318587695 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 211284340 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 36331371 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 4908514 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 18177231 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 2045887 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 591006296 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 22089664 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 4908514 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 134210773 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 44178364 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 216212349 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 213325919 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 58630839 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 574898328 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 5600894 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 8989963 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 383271 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 860464 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 24265786 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 10988 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 548407946 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 889065279 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 679031773 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 678204 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 493384651 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 55023295 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 15514043 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 13585261 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 73076002 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 95606432 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 79961275 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 8917606 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 7761424 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 553073173 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 15730545 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 557717167 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 2597694 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 51818937 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 33853803 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 272876 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 671466758 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.830595 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.066249 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 636270063 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.186644 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.828014 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 93717841 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 303303779 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 200797968 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 33854734 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 4595741 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 17115460 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 1907562 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 560589350 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 20699594 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 4595741 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 125431952 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 39494252 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 209485809 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 202527049 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 54735260 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 545352444 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 5255771 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 8923159 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 236326 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 251378 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 23064401 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 10277 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 518904030 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 842346329 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 645518990 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 772636 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 467533188 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 51370836 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 14457491 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 12765800 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 68374020 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 90157460 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 77360116 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 8411660 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 7288721 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 524903956 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 14739695 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 529653671 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 2395600 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 48736249 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 31414673 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 252865 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 636270063 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.832435 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.069985 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 364901654 54.34% 54.34% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 131371089 19.56% 73.91% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 106572496 15.87% 89.78% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 61289322 9.13% 98.91% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 7327865 1.09% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 4332 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 346386206 54.44% 54.44% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 123009687 19.33% 73.77% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 101156259 15.90% 89.67% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 58544050 9.20% 98.87% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 7169989 1.13% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 3872 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 671466758 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 636270063 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 55930906 44.08% 44.08% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 67479 0.05% 44.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 9405 0.01% 44.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 14 0.00% 44.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 34760931 27.40% 71.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 36114343 28.46% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 53039712 43.72% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 43863 0.04% 43.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 10928 0.01% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 13 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 32632716 26.90% 70.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 35589452 29.34% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 41 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 380161908 68.16% 68.16% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 1344725 0.24% 68.41% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 78828 0.01% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 3 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 5 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 45642 0.01% 68.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.43% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 98115732 17.59% 86.02% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 77970283 13.98% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 2 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 360085884 67.99% 67.99% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1163863 0.22% 68.20% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 64768 0.01% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 79405 0.01% 68.23% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.23% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.23% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.23% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 92781248 17.52% 85.75% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 75478453 14.25% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 557717167 # Type of FU issued -system.cpu1.iq.rate 0.809195 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 126883078 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.227504 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 1915274546 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 620324151 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 541832642 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 1107318 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 438573 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 407875 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 683910466 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 689738 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 2496582 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 529653671 # Type of FU issued +system.cpu1.iq.rate 0.812229 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 121316684 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.229049 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 1818002123 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 587994704 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 514426397 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 1287564 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 520666 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 480327 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 650175074 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 795279 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 2341712 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 11949439 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 17528 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 140940 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 5567236 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 11071583 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 15258 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 136605 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 5366212 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 2504839 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 3936319 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 2403910 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 3823950 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 4908514 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 7583348 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 1594599 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 568926208 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 4595741 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 5738657 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 1529256 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 539757610 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 95606432 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 79961275 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 13359998 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 58436 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 1466228 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 140940 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 1941130 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2763310 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 4704440 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 550354066 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 95142052 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 6771828 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 90157460 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 77360116 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 12526602 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 63879 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 1404906 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 136605 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 1813433 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2553447 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 4366880 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 522753556 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 90069669 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 6385743 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 122490 # number of nop insts executed -system.cpu1.iew.exec_refs 171896040 # number of memory reference insts executed -system.cpu1.iew.exec_branches 103292614 # Number of branches executed -system.cpu1.iew.exec_stores 76753988 # Number of stores executed -system.cpu1.iew.exec_rate 0.798512 # Inst execution rate -system.cpu1.iew.wb_sent 542951378 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 542240517 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 263529127 # num instructions producing a value -system.cpu1.iew.wb_consumers 431811268 # num instructions consuming a value +system.cpu1.iew.exec_nop 113959 # number of nop insts executed +system.cpu1.iew.exec_refs 164397082 # number of memory reference insts executed +system.cpu1.iew.exec_branches 97927466 # Number of branches executed +system.cpu1.iew.exec_stores 74327413 # Number of stores executed +system.cpu1.iew.exec_rate 0.801648 # Inst execution rate +system.cpu1.iew.wb_sent 515591253 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 514906724 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 248837648 # num instructions producing a value +system.cpu1.iew.wb_consumers 408235008 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.786740 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.610288 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.789615 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.609545 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 45371481 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 15457669 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 4415885 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 662874998 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.779913 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.574524 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 42654937 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 14486830 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4109860 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 628197112 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.781454 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.577369 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 435019222 65.63% 65.63% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 119535237 18.03% 83.66% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 49733246 7.50% 91.16% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 16752738 2.53% 93.69% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 12005106 1.81% 95.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 8186664 1.24% 96.74% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 5495672 0.83% 97.56% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 3379842 0.51% 98.07% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 12767271 1.93% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 412381395 65.65% 65.65% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 112703002 17.94% 83.59% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 47448288 7.55% 91.14% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 15899123 2.53% 93.67% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 11433065 1.82% 95.49% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 7648889 1.22% 96.71% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 5327937 0.85% 97.56% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3177183 0.51% 98.06% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 12178230 1.94% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 662874998 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 439804157 # Number of instructions committed -system.cpu1.commit.committedOps 516984781 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 628197112 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 416485993 # Number of instructions committed +system.cpu1.commit.committedOps 490907395 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 158051032 # Number of memory references committed -system.cpu1.commit.loads 83656993 # Number of loads committed -system.cpu1.commit.membars 3709079 # Number of memory barriers committed -system.cpu1.commit.branches 98009532 # Number of branches committed -system.cpu1.commit.fp_insts 399401 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 474457036 # Number of committed integer instructions. -system.cpu1.commit.function_calls 12875376 # Number of function calls committed. +system.cpu1.commit.refs 151079780 # Number of memory references committed +system.cpu1.commit.loads 79085876 # Number of loads committed +system.cpu1.commit.membars 3553216 # Number of memory barriers committed +system.cpu1.commit.branches 92889165 # Number of branches committed +system.cpu1.commit.fp_insts 468052 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 450541794 # Number of committed integer instructions. +system.cpu1.commit.function_calls 11963242 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 357731742 69.20% 69.20% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 1099808 0.21% 69.41% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 62550 0.01% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 39649 0.01% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 83656993 16.18% 85.61% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 74394039 14.39% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 338771351 69.01% 69.01% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 933774 0.19% 69.20% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 51484 0.01% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 70964 0.01% 69.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.22% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 79085876 16.11% 85.33% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 71993904 14.67% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 516984781 # Class of committed instruction -system.cpu1.commit.bw_lim_events 12767271 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 1208536006 # The number of ROB reads -system.cpu1.rob.rob_writes 1133266670 # The number of ROB writes -system.cpu1.timesIdled 962801 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 17758138 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 94081707774 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 439804157 # Number of Instructions Simulated -system.cpu1.committedOps 516984781 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.567118 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.567118 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.638114 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.638114 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 649922276 # number of integer regfile reads -system.cpu1.int_regfile_writes 385926927 # number of integer regfile writes -system.cpu1.fp_regfile_reads 666608 # number of floating regfile reads -system.cpu1.fp_regfile_writes 325148 # number of floating regfile writes -system.cpu1.cc_regfile_reads 119080359 # number of cc regfile reads -system.cpu1.cc_regfile_writes 119756232 # number of cc regfile writes -system.cpu1.misc_regfile_reads 1205246137 # number of misc regfile reads -system.cpu1.misc_regfile_writes 15455536 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 5466279 # number of replacements -system.cpu1.dcache.tags.tagsinuse 430.006906 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 146874051 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5466791 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 26.866593 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8478589492000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 430.006906 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.839857 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.839857 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 328243838 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 328243838 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 77663514 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 77663514 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 64795157 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 64795157 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 170774 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 170774 # number of SoftPFReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 62879 # number of WriteInvalidateReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::total 62879 # number of WriteInvalidateReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1733317 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1733317 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1753267 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1753267 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 142458671 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 142458671 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 142629445 # number of overall hits -system.cpu1.dcache.overall_hits::total 142629445 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 6440843 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 6440843 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 7141641 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 7141641 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 671959 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 671959 # number of SoftPFReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 448993 # number of WriteInvalidateReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::total 448993 # number of WriteInvalidateReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 259783 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 259783 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 195367 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 195367 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 13582484 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 13582484 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 14254443 # number of overall misses -system.cpu1.dcache.overall_misses::total 14254443 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 96129677540 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 96129677540 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 127902484654 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 127902484654 # number of WriteReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 14399209171 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 14399209171 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3810993278 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 3810993278 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4142660469 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4142660469 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3781500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3781500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 224032162194 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 224032162194 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 224032162194 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 224032162194 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 84104357 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 84104357 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 71936798 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 71936798 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 842733 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 842733 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 511872 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::total 511872 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1993100 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1993100 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1948634 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1948634 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 156041155 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 156041155 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 156883888 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 156883888 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.076582 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.076582 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.099277 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.099277 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.797357 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.797357 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.877159 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.877159 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.130341 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.130341 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100258 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100258 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.087044 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.087044 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.090860 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.090860 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14925.014868 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14925.014868 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17909.397106 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 17909.397106 # average WriteReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 32070.008154 # average WriteInvalidateReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 32070.008154 # average WriteInvalidateReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14669.910187 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14669.910187 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21204.504696 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21204.504696 # average StoreCondReq miss latency +system.cpu1.commit.op_class_0::total 490907395 # Class of committed instruction +system.cpu1.commit.bw_lim_events 12178230 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 1145716069 # The number of ROB reads +system.cpu1.rob.rob_writes 1075160501 # The number of ROB writes +system.cpu1.timesIdled 888623 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 15828719 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 93967443806 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 416485993 # Number of Instructions Simulated +system.cpu1.committedOps 490907395 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.565716 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.565716 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.638685 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.638685 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 618570567 # number of integer regfile reads +system.cpu1.int_regfile_writes 365658107 # number of integer regfile writes +system.cpu1.fp_regfile_reads 762313 # number of floating regfile reads +system.cpu1.fp_regfile_writes 433520 # number of floating regfile writes +system.cpu1.cc_regfile_reads 112664520 # number of cc regfile reads +system.cpu1.cc_regfile_writes 113502103 # number of cc regfile writes +system.cpu1.misc_regfile_reads 1139246007 # number of misc regfile reads +system.cpu1.misc_regfile_writes 14605610 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 5006870 # number of replacements +system.cpu1.dcache.tags.tagsinuse 430.966811 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 140806906 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5007379 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 28.119882 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8489665359000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 430.966811 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.841732 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.841732 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 370 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 313329932 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 313329932 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 73478112 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 73478112 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 62922278 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 62922278 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 161792 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 161792 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 60224 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 60224 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1740937 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1740937 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1748633 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1748633 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 136400390 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 136400390 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 136562182 # number of overall hits +system.cpu1.dcache.overall_hits::total 136562182 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 5886586 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 5886586 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 6650181 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 6650181 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 625497 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 625497 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 420972 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 420972 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 235563 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 235563 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 185045 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 185045 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 12536767 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 12536767 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 13162264 # number of overall misses +system.cpu1.dcache.overall_misses::total 13162264 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 84434005000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 84434005000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 115550287907 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 115550287907 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 14693527706 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 14693527706 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3280765000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 3280765000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3888950500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 3888950500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3327000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3327000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 199984292907 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 199984292907 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 199984292907 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 199984292907 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 79364698 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 79364698 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 69572459 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 69572459 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 787289 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 787289 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 481196 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 481196 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1976500 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1976500 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1933678 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1933678 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 148937157 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 148937157 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 149724446 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 149724446 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.074171 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.074171 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.095586 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.095586 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.794495 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.794495 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.874845 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.874845 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119182 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119182 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.095696 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.095696 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.084175 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.084175 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.087910 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.087910 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14343.459010 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14343.459010 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17375.510216 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 17375.510216 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 34903.812382 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 34903.812382 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13927.335787 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13927.335787 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21016.241995 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21016.241995 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16494.196658 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 16494.196658 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15716.654954 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15716.654954 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 3725007 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 19991584 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 377661 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 721598 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.863362 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 27.704600 # average number of cycles each access was blocked +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15951.823377 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 15951.823377 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15193.760960 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15193.760960 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 3842918 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 18319630 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 344375 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 666302 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 11.159109 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 27.494484 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 3504875 # number of writebacks -system.cpu1.dcache.writebacks::total 3504875 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3270021 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 3270021 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5779466 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 5779466 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 3415 # number of WriteInvalidateReq MSHR hits -system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 3415 # number of WriteInvalidateReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 132178 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 132178 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 9049487 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 9049487 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 9049487 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 9049487 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3170822 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 3170822 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1362175 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1362175 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 671771 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 671771 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 445578 # number of WriteInvalidateReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 445578 # number of WriteInvalidateReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 127605 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 127605 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 195366 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 195366 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4532997 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4532997 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 5204768 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 5204768 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 7126 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 7126 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7600 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 7600 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 14726 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 14726 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 42364690330 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 42364690330 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 24508372089 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 24508372089 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14203530799 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14203530799 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 13616215076 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 13616215076 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1679833771 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1679833771 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3840214031 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3840214031 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3660000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3660000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 66873062419 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 66873062419 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 81076593218 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 81076593218 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 831425000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 831425000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 995372500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 995372500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1826797500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1826797500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037701 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037701 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018936 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018936 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.797134 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.797134 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.870487 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.870487 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064023 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.064023 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100258 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100258 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029050 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.029050 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033176 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.033176 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13360.791091 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13360.791091 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17992.087719 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17992.087719 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21143.411667 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21143.411667 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 30558.544354 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 30558.544354 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13164.325622 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13164.325622 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19656.511527 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19656.511527 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 3252895 # number of writebacks +system.cpu1.dcache.writebacks::total 3252895 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3007786 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 3007786 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5379273 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 5379273 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3474 # number of WriteLineReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::total 3474 # number of WriteLineReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 121870 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 121870 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 8387059 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 8387059 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 8387059 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 8387059 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2878800 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2878800 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1270908 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1270908 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 625447 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 625447 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 417498 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 417498 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 113693 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 113693 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 185035 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 185035 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4149708 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4149708 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 4775155 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 4775155 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 18068 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 18068 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 15995 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 15995 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 34063 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 34063 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 38840223500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 38840223500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 22606708667 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 22606708667 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13883914500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13883914500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 14151578206 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 14151578206 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1521353000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1521353000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3703986500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3703986500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3256000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3256000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 61446932167 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 61446932167 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 75330846667 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 75330846667 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2814873000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2814873000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2522981000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2522981000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 5337854000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 5337854000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036273 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036273 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018267 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018267 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.794431 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.794431 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.867626 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.867626 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.057522 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.057522 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.095691 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.095691 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027862 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027862 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031893 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.031893 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13491.810303 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13491.810303 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17787.840400 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17787.840400 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22198.386914 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22198.386914 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 33896.158080 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 33896.158080 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13381.237191 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13381.237191 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20017.761505 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20017.761505 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14752.505333 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14752.505333 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15577.369293 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15577.369293 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116674.852652 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 116674.852652 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 130970.065789 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 130970.065789 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 124052.526144 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 124052.526144 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14807.531558 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14807.531558 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15775.581456 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15775.581456 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 155793.280939 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 155793.280939 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 157735.604877 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 157735.604877 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 156705.340105 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 156705.340105 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 5740789 # number of replacements -system.cpu1.icache.tags.tagsinuse 501.866118 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 196754052 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 5741301 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 34.269942 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8518317120500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.866118 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980207 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.980207 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 5324088 # number of replacements +system.cpu1.icache.tags.tagsinuse 501.812989 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 185755475 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 5324600 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 34.886278 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8495816906000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.812989 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980103 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.980103 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 334 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 54 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 124 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 411371773 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 411371773 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 196754052 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 196754052 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 196754052 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 196754052 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 196754052 # number of overall hits -system.cpu1.icache.overall_hits::total 196754052 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 6061167 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 6061167 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 6061167 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 6061167 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 6061167 # number of overall misses -system.cpu1.icache.overall_misses::total 6061167 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 63767181305 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 63767181305 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 63767181305 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 63767181305 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 63767181305 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 63767181305 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 202815219 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 202815219 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 202815219 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 202815219 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 202815219 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 202815219 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029885 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.029885 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029885 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.029885 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029885 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.029885 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10520.611180 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 10520.611180 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10520.611180 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10520.611180 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10520.611180 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10520.611180 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 8678948 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 76 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 693947 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.506644 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 38 # average number of cycles each access was blocked +system.cpu1.icache.tags.tag_accesses 388109731 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 388109731 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 185755475 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 185755475 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 185755475 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 185755475 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 185755475 # number of overall hits +system.cpu1.icache.overall_hits::total 185755475 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 5637082 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 5637082 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 5637082 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 5637082 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 5637082 # number of overall misses +system.cpu1.icache.overall_misses::total 5637082 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 58647080384 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 58647080384 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 58647080384 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 58647080384 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 58647080384 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 58647080384 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 191392557 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 191392557 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 191392557 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 191392557 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 191392557 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 191392557 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029453 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.029453 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029453 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.029453 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029453 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.029453 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10403.801184 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 10403.801184 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10403.801184 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10403.801184 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10403.801184 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10403.801184 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 8439613 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 34 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 658051 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.825166 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 34 # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 319831 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 319831 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 319831 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 319831 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 319831 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 319831 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5741336 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 5741336 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 5741336 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 5741336 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 5741336 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 5741336 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 312465 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 312465 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 312465 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 312465 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 312465 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 312465 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5324617 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 5324617 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 5324617 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 5324617 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 5324617 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 5324617 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 67 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 67 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 54923658725 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 54923658725 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 54923658725 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 54923658725 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 54923658725 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 54923658725 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6151998 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6151998 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6151998 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 6151998 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.028308 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.028308 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.028308 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.028308 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.028308 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.028308 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9566.355065 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9566.355065 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9566.355065 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 9566.355065 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9566.355065 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 9566.355065 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 91820.865672 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 91820.865672 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 91820.865672 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 91820.865672 # average overall mshr uncacheable latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 53161463126 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 53161463126 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 53161463126 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 53161463126 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 53161463126 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 53161463126 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6100998 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6100998 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6100998 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 6100998 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027820 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027820 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027820 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.027820 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027820 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.027820 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9984.091462 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9984.091462 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9984.091462 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 9984.091462 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9984.091462 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 9984.091462 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 91059.671642 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 91059.671642 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 91059.671642 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 91059.671642 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 7332494 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 7535643 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 175627 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 6690086 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 6848412 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 136895 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 929621 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 2299794 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13092.282613 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 11932680 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2315440 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 5.153526 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9714628416493 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 5051.662856 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 84.315143 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 91.749127 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3269.093236 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3705.071376 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 890.390874 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.308329 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.005146 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005600 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.199530 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.226140 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.054345 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.799090 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1406 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 105 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14135 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 76 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 267 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 643 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 420 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 5 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 73 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 17 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 232 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 703 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4677 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4917 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3606 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.085815 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.006409 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.862732 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 260544625 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 260544625 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 585527 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 176354 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 5103092 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 2955317 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 8820290 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 3504868 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 3504868 # number of Writeback hits -system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 166502 # number of WriteInvalidateReq hits -system.cpu1.l2cache.WriteInvalidateReq_hits::total 166502 # number of WriteInvalidateReq hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 71993 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 71993 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 35298 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 35298 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 907237 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 907237 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 585527 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 176354 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 5103092 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3862554 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 9727527 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 585527 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 176354 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 5103092 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3862554 # number of overall hits -system.cpu1.l2cache.overall_hits::total 9727527 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 13010 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9568 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 638215 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 1012370 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 1673163 # number of ReadReq misses -system.cpu1.l2cache.Writeback_misses::writebacks 6 # number of Writeback misses -system.cpu1.l2cache.Writeback_misses::total 6 # number of Writeback misses -system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 277800 # number of WriteInvalidateReq misses -system.cpu1.l2cache.WriteInvalidateReq_misses::total 277800 # number of WriteInvalidateReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 139883 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 139883 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 160055 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 160055 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 13 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 13 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 249549 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 249549 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 13010 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9568 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 638215 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 1261919 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 1922712 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 13010 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9568 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 638215 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 1261919 # number of overall misses -system.cpu1.l2cache.overall_misses::total 1922712 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 512958208 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 430734867 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 18770053212 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 34728720424 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 54442466711 # number of ReadReq miss cycles -system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data 206094146 # number of WriteInvalidateReq miss cycles -system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 206094146 # number of WriteInvalidateReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3019471858 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 3019471858 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3326642430 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3326642430 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 3578499 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 3578499 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 12555468370 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 12555468370 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 512958208 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 430734867 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 18770053212 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 47284188794 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 66997935081 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 512958208 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 430734867 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 18770053212 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 47284188794 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 66997935081 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 598537 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 185922 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 5741307 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 3967687 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 10493453 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 3504874 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 3504874 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 444302 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.l2cache.WriteInvalidateReq_accesses::total 444302 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 211876 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 211876 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 195353 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 195353 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 13 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 13 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1156786 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 1156786 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 598537 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 185922 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 5741307 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 5124473 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 11650239 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 598537 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 185922 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 5741307 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 5124473 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 11650239 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.021736 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.051462 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.111162 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.255154 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.159448 # miss rate for ReadReq accesses -system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000002 # miss rate for Writeback accesses -system.cpu1.l2cache.Writeback_miss_rate::total 0.000002 # miss rate for Writeback accesses -system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.625250 # miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.625250 # miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.660212 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.660212 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.819312 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.819312 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.prefetcher.pfSpanPage 833652 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 2101281 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13129.737314 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 17962799 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 2117240 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 8.484064 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 10109948263500 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 3719.638298 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 30.194019 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 18.354708 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4841.731410 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3496.437967 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1023.380912 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.227029 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001843 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.001120 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.295516 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.213406 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.062462 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.801376 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1215 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 80 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14664 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 4 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 26 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 222 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 606 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 357 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 40 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 15 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 24 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 138 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1327 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5436 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4651 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3112 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.074158 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004883 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.895020 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 353923766 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 353923766 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 516145 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 163709 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 679854 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 3252875 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 3252875 # number of Writeback hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 76096 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 76096 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 32991 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 32991 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 823499 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 823499 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4739467 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 4739467 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2648300 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 2648300 # number of ReadSharedReq hits +system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 186015 # number of InvalidateReq hits +system.cpu1.l2cache.InvalidateReq_hits::total 186015 # number of InvalidateReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 516145 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 163709 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 4739467 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 3471799 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 8891120 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 516145 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 163709 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 4739467 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 3471799 # number of overall hits +system.cpu1.l2cache.overall_hits::total 8891120 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 10986 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 7768 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 18754 # number of ReadReq misses +system.cpu1.l2cache.Writeback_misses::writebacks 19 # number of Writeback misses +system.cpu1.l2cache.Writeback_misses::total 19 # number of Writeback misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 135316 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 135316 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 152038 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 152038 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 6 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 244643 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 244643 # number of ReadExReq misses +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 585139 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadCleanReq_misses::total 585139 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 965514 # number of ReadSharedReq misses +system.cpu1.l2cache.ReadSharedReq_misses::total 965514 # number of ReadSharedReq misses +system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 230258 # number of InvalidateReq misses +system.cpu1.l2cache.InvalidateReq_misses::total 230258 # number of InvalidateReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 10986 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 7768 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 585139 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 1210157 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 1814050 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 10986 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 7768 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 585139 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 1210157 # number of overall misses +system.cpu1.l2cache.overall_misses::total 1814050 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 393593000 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 283804000 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 677397000 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2923492500 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 2923492500 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3131932000 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3131932000 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 3149000 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 3149000 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 10851172997 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 10851172997 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 16931159000 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::total 16931159000 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 31232900488 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::total 31232900488 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 11958390500 # number of InvalidateReq miss cycles +system.cpu1.l2cache.InvalidateReq_miss_latency::total 11958390500 # number of InvalidateReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 393593000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 283804000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 16931159000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 42084073485 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 59692629485 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 393593000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 283804000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 16931159000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 42084073485 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 59692629485 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 527131 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 171477 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 698608 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 3252894 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 3252894 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 211412 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 211412 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 185029 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 185029 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 6 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1068142 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 1068142 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5324606 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::total 5324606 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3613814 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::total 3613814 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 416273 # number of InvalidateReq accesses(hits+misses) +system.cpu1.l2cache.InvalidateReq_accesses::total 416273 # number of InvalidateReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 527131 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 171477 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 5324606 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 4681956 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 10705170 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 527131 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 171477 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 5324606 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 4681956 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 10705170 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.020841 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.045301 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.026845 # miss rate for ReadReq accesses +system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000006 # miss rate for Writeback accesses +system.cpu1.l2cache.Writeback_miss_rate::total 0.000006 # miss rate for Writeback accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.640058 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.640058 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.821698 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.821698 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.215726 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.215726 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.021736 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.051462 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.111162 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.246253 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.165036 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.021736 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.051462 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.111162 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.246253 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.165036 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 39427.994466 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 45018.276233 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 29410.235128 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 34304.375302 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 32538.650873 # average ReadReq miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data 741.879575 # average WriteInvalidateReq miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 741.879575 # average WriteInvalidateReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21585.695603 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21585.695603 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20784.370560 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20784.370560 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 275269.153846 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 275269.153846 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 50312.637478 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 50312.637478 # average ReadExReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 39427.994466 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 45018.276233 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 29410.235128 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 37470.066458 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 34845.538532 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 39427.994466 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 45018.276233 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 29410.235128 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 37470.066458 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 34845.538532 # average overall miss latency -system.cpu1.l2cache.blocked_cycles::no_mshrs 20 # number of cycles access was blocked +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.229036 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.229036 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.109893 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.109893 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.267173 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.267173 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.553142 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.553142 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.020841 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.045301 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.109893 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.258473 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.169456 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.020841 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.045301 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.109893 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.258473 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.169456 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 35826.779538 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 36535.015448 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 36120.134371 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21604.928464 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21604.928464 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20599.665873 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20599.665873 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 524833.333333 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 524833.333333 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 44355.133795 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 44355.133795 # average ReadExReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 28935.276917 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 28935.276917 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 32348.469818 # average ReadSharedReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 32348.469818 # average ReadSharedReq miss latency +system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 51934.744938 # average InvalidateReq miss latency +system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 51934.744938 # average InvalidateReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 35826.779538 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 36535.015448 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 28935.276917 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34775.713800 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 32905.724476 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 35826.779538 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 36535.015448 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 28935.276917 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34775.713800 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 32905.724476 # average overall miss latency +system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 6.666667 # average number of cycles each access was blocked +system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 1059677 # number of writebacks -system.cpu1.l2cache.writebacks::total 1059677 # number of writebacks -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 6 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 183 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 3574 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::total 3763 # number of ReadReq MSHR hits -system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.data 5 # number of WriteInvalidateReq MSHR hits -system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total 5 # number of WriteInvalidateReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 19034 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 19034 # number of ReadExReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 6 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 183 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 22608 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 22797 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 6 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 183 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 22608 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 22797 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 13004 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9385 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 638215 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 1008796 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 1669400 # number of ReadReq MSHR misses -system.cpu1.l2cache.Writeback_mshr_misses::writebacks 6 # number of Writeback MSHR misses -system.cpu1.l2cache.Writeback_mshr_misses::total 6 # number of Writeback MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 738806 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 738806 # number of HardPFReq MSHR misses -system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.data 277795 # number of WriteInvalidateReq MSHR misses -system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total 277795 # number of WriteInvalidateReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 139883 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 139883 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 160055 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 160055 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 13 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 13 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 230515 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 230515 # number of ReadExReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 13004 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9385 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 638215 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1239311 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 1899915 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 13004 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9385 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 638215 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1239311 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 738806 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 2638721 # number of overall MSHR misses +system.cpu1.l2cache.writebacks::writebacks 947503 # number of writebacks +system.cpu1.l2cache.writebacks::total 947503 # number of writebacks +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 7 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 197 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::total 204 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 11124 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 11124 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 1 # number of ReadCleanReq MSHR hits +system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits +system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 2294 # number of ReadSharedReq MSHR hits +system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 2294 # number of ReadSharedReq MSHR hits +system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 25 # number of InvalidateReq MSHR hits +system.cpu1.l2cache.InvalidateReq_mshr_hits::total 25 # number of InvalidateReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 7 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 197 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 13418 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 13623 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 7 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 197 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 13418 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 13623 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 10979 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 7571 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 18550 # number of ReadReq MSHR misses +system.cpu1.l2cache.Writeback_mshr_misses::writebacks 19 # number of Writeback MSHR misses +system.cpu1.l2cache.Writeback_mshr_misses::total 19 # number of Writeback MSHR misses +system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 99449 # number of CleanEvict MSHR misses +system.cpu1.l2cache.CleanEvict_mshr_misses::total 99449 # number of CleanEvict MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 669869 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 669869 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 135316 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 135316 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 152038 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 152038 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 6 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 233519 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 233519 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 585138 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 585138 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 963220 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 963220 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 230233 # number of InvalidateReq MSHR misses +system.cpu1.l2cache.InvalidateReq_mshr_misses::total 230233 # number of InvalidateReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 10979 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 7571 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 585138 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1196739 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 1800427 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 10979 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 7571 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 585138 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1196739 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 669869 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 2470296 # number of overall MSHR misses system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 7126 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 7193 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 7600 # number of WriteReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 7600 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 18068 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 18135 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 15995 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 15995 # number of WriteReq MSHR uncacheable system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 14726 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 14793 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 427470062 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 361612807 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 14605198288 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 27880753226 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 43275034383 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 44447581689 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 44447581689 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 9533570164 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 9533570164 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2794262081 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2794262081 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2375248051 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2375248051 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 3051999 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 3051999 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8594281659 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8594281659 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 427470062 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 361612807 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 14605198288 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 36475034885 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 51869316042 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 427470062 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 361612807 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 14605198288 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 36475034885 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 44447581689 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 96316897731 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5626000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 774397000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 780023000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 938365000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 938365000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 5626000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1712762000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1718388000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.021726 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.050478 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.111162 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.254253 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.159090 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000002 # mshr miss rate for Writeback accesses -system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000002 # mshr miss rate for Writeback accesses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 34063 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 34130 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 327529500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 230470000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 557999500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 32826022044 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 32826022044 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2716564991 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2716564991 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2299520000 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2299520000 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2723000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2723000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8060381997 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8060381997 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 13420310000 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 13420310000 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 25345446988 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 25345446988 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 10575798500 # number of InvalidateReq MSHR miss cycles +system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 10575798500 # number of InvalidateReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 327529500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 230470000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 13420310000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 33405828985 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 47384138485 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 327529500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 230470000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 13420310000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 33405828985 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 32826022044 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 80210160529 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5597500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2670265000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2675862500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 2403001000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 2403001000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 5597500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 5073266000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 5078863500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.020828 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.044152 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.026553 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000006 # mshr miss rate for Writeback accesses +system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000006 # mshr miss rate for Writeback accesses +system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.625239 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.625239 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.660212 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.660212 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.819312 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.819312 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.640058 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.640058 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.821698 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.821698 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.199272 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.199272 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021726 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.050478 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.111162 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.241842 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.163079 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021726 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.050478 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.111162 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.241842 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.218622 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.218622 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.109893 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.109893 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.266538 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.266538 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.553082 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.553082 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020828 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.044152 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.109893 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.255607 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.168183 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020828 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.044152 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.109893 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.255607 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.226495 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 32872.197939 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 38530.933085 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22884.448482 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 27637.652435 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25922.507717 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 60161.370764 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 60161.370764 # average HardPFReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 34318.724829 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 34318.724829 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19975.708850 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19975.708850 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14840.199000 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14840.199000 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 234769.153846 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 234769.153846 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37282.960584 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37282.960584 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 32872.197939 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 38530.933085 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22884.448482 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 29431.704298 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27300.861376 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 32872.197939 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 38530.933085 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22884.448482 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 29431.704298 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 60161.370764 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 36501.357184 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 83970.149254 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 108672.046029 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 108441.957459 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 123469.078947 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 123469.078947 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 83970.149254 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 116308.705691 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 116162.238897 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.230757 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 29832.361782 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 30441.157047 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 30080.835580 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 49003.644062 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 49003.644062 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20075.711601 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20075.711601 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15124.639893 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15124.639893 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 453833.333333 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 453833.333333 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34517.028580 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34517.028580 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 22935.290478 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 22935.290478 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 26313.248259 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26313.248259 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 45935.198256 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 45935.198256 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 29832.361782 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 30441.157047 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22935.290478 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27914.047244 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26318.278100 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 29832.361782 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 30441.157047 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22935.290478 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27914.047244 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 49003.644062 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 32469.858077 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 83544.776119 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 147789.738765 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 147552.384891 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 150234.510785 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150234.510785 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 83544.776119 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 148937.733024 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 148809.361266 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 13189135 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 10749038 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 38779 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 7600 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 3504874 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 1040151 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 17 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1162830 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 444302 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 468816 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 354419 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 478843 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 75 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 143 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1323230 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1164313 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11482776 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15667685 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 405853 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1309392 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 28865706 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 367444720 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 587773064 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1487376 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4788296 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 961493456 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 5242184 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 21082310 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 1.277260 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.447646 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 892292 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 9878632 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 38264 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 15995 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 7255897 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 9976246 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 974296 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 4 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 447021 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 338151 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 459645 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 83 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 148 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1866908 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1075363 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5324617 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 6289738 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 523001 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 416273 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 15972735 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16223776 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 373937 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1157245 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 33727693 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 340775856 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 514151471 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1371816 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4217048 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 860516191 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 12204948 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 33927884 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 1.375605 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.484279 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 15237020 72.27% 72.27% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 5845290 27.73% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 21184404 62.44% 62.44% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 12743480 37.56% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 21082310 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 12037419620 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 33927884 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 14269396468 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 200301486 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 176820981 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 8624197196 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 7990923619 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 8185098674 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7460231410 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 220844820 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 202704009 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 711986885 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 630714293 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40346 # Transaction distribution -system.iobus.trans_dist::ReadResp 40346 # Transaction distribution -system.iobus.trans_dist::WriteReq 136632 # Transaction distribution -system.iobus.trans_dist::WriteResp 29904 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47732 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 40336 # Transaction distribution +system.iobus.trans_dist::ReadResp 40336 # Transaction distribution +system.iobus.trans_dist::WriteReq 136670 # Transaction distribution +system.iobus.trans_dist::WriteResp 136670 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47832 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -2895,18 +2986,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122614 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231262 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231262 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122766 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231166 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231166 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353956 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47752 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 354012 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47852 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2916,18 +3007,18 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155744 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339064 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7339064 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155873 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338680 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338680 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496894 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36253000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496639 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36328000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2947,7 +3038,7 @@ system.iobus.reqLayer16.occupancy 12000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) @@ -2955,780 +3046,757 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 607574888 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 569486466 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92713000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92827000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 148591827 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147862000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 170500 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115612 # number of replacements -system.iocache.tags.tagsinuse 11.304105 # Cycle average of tags in use +system.iocache.tags.replacements 115572 # number of replacements +system.iocache.tags.tagsinuse 11.309139 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115628 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115588 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9116941730000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.838498 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.465607 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.239906 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.466600 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.706507 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9081185715000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.844632 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.464507 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.240289 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.466532 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.706821 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1041036 # Number of tag accesses -system.iocache.tags.data_accesses 1041036 # Number of data accesses +system.iocache.tags.tag_accesses 1040604 # Number of tag accesses +system.iocache.tags.data_accesses 1040604 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8903 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8940 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8855 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8892 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8903 # number of demand (read+write) misses -system.iocache.demand_misses::total 8943 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8855 # number of demand (read+write) misses +system.iocache.demand_misses::total 8895 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8903 # number of overall misses -system.iocache.overall_misses::total 8943 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5195500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1642618319 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1647813819 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19871992742 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 19871992742 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5564500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1642618319 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1648182819 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5564500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1642618319 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1648182819 # number of overall miss cycles +system.iocache.overall_misses::realview.ide 8855 # number of overall misses +system.iocache.overall_misses::total 8895 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5195000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1639991052 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1645186052 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::realview.ethernet 373000 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 373000 # number of WriteReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12624663414 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12624663414 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5568000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1639991052 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1645559052 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5568000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1639991052 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1645559052 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8903 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8940 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8855 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8892 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8903 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8943 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8855 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8895 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8903 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8943 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8855 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8895 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140418.918919 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 184501.664495 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 184319.219128 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186192.871055 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 186192.871055 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 184501.664495 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 184298.649111 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 184501.664495 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 184298.649111 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 111619 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 185205.087747 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 185018.674314 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::realview.ethernet 124333.333333 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 124333.333333 # average WriteReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118288.203789 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118288.203789 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139200 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 185205.087747 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 184998.207083 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139200 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 185205.087747 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 184998.207083 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 32135 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 16154 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3455 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.909682 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.301013 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106694 # number of writebacks -system.iocache.writebacks::total 106694 # number of writebacks +system.iocache.writebacks::writebacks 106702 # number of writebacks +system.iocache.writebacks::total 106702 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8903 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8940 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8855 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8892 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106728 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 106728 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8903 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8943 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8855 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8895 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8903 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8943 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3270500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1178449871 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1181720371 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 213000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 213000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14322034844 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14322034844 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3483500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1178449871 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1181933371 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3483500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1178449871 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1181933371 # number of overall MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8855 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8895 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3345000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1197241052 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1200586052 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 223000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 223000 # number of WriteReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7288263414 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7288263414 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3568000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1197241052 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1200809052 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3568000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1197241052 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1200809052 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 88391.891892 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 132365.480288 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 132183.486689 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 71000 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 71000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134191.916311 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134191.916311 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 132365.480288 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 132162.962205 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 132365.480288 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 132162.962205 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 135205.087747 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 135018.674314 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 74333.333333 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 74333.333333 # average WriteReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68288.203789 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68288.203789 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89200 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 135205.087747 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 134998.207083 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89200 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 135205.087747 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 134998.207083 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1633733 # number of replacements -system.l2c.tags.tagsinuse 64442.276820 # Cycle average of tags in use -system.l2c.tags.total_refs 4812382 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1694389 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.840187 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 3265660000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 17567.436669 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 345.231271 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 471.940947 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4509.499901 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 13049.127195 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 17952.495565 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 52.864907 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 70.453845 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2659.379343 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 4127.659130 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3636.188048 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.268058 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.005268 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.007201 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.068810 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.199114 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.273933 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000807 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.001075 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.040579 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.062983 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.055484 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.983311 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 10750 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 247 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 49659 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 1276 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 687 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 8787 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 238 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 294 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2518 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4806 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 41987 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.164032 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003769 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.757736 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 65067124 # Number of tag accesses -system.l2c.tags.data_accesses 65067124 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 6771 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4585 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 583685 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 633203 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 298139 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 6546 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 4209 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 589652 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 570600 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 281047 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2978437 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 2596817 # number of Writeback hits -system.l2c.Writeback_hits::total 2596817 # number of Writeback hits -system.l2c.WriteInvalidateReq_hits::cpu0.data 138250 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::cpu1.data 130696 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::total 268946 # number of WriteInvalidateReq hits -system.l2c.UpgradeReq_hits::cpu0.data 34228 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 26005 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 60233 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 6128 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 6125 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 12253 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 55044 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 49984 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 105028 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 6771 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4585 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 583685 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 688247 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 298139 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 6546 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4209 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 589652 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 620584 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 281047 # number of demand (read+write) hits -system.l2c.demand_hits::total 3083465 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 6771 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4585 # number of overall hits -system.l2c.overall_hits::cpu0.inst 583685 # number of overall hits -system.l2c.overall_hits::cpu0.data 688247 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 298139 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 6546 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 4209 # number of overall hits -system.l2c.overall_hits::cpu1.inst 589652 # number of overall hits -system.l2c.overall_hits::cpu1.data 620584 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 281047 # number of overall hits -system.l2c.overall_hits::total 3083465 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 2623 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2323 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 65378 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 160715 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 295001 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 2679 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 2566 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 48562 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 132475 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 268900 # number of ReadReq misses -system.l2c.ReadReq_misses::total 981222 # number of ReadReq misses -system.l2c.WriteInvalidateReq_misses::cpu0.data 444602 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::cpu1.data 139009 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::total 583611 # number of WriteInvalidateReq misses -system.l2c.UpgradeReq_misses::cpu0.data 48239 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 46690 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 94929 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 9164 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 9498 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 18662 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 83588 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 58117 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 141705 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 2623 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2323 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 65378 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 244303 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 295001 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 2679 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 2566 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 48562 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 190592 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 268900 # number of demand (read+write) misses -system.l2c.demand_misses::total 1122927 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 2623 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 2323 # number of overall misses -system.l2c.overall_misses::cpu0.inst 65378 # number of overall misses -system.l2c.overall_misses::cpu0.data 244303 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 295001 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 2679 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 2566 # number of overall misses -system.l2c.overall_misses::cpu1.inst 48562 # number of overall misses -system.l2c.overall_misses::cpu1.data 190592 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 268900 # number of overall misses -system.l2c.overall_misses::total 1122927 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 244393039 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 217850761 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 5706510559 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 16014013375 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 43733676321 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 249111297 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 239093772 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 4255255686 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 13145453309 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 39841128623 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 123646486742 # number of ReadReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::cpu0.data 51997674 # number of WriteInvalidateReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 39165941 # number of WriteInvalidateReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::total 91163615 # number of WriteInvalidateReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 308199351 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 263365265 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 571564616 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 47104504 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 54418277 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 101522781 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 7762052110 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 5404141951 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 13166194061 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 244393039 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 217850761 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 5706510559 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 23776065485 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 43733676321 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 249111297 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 239093772 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 4255255686 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 18549595260 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 39841128623 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 136812680803 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 244393039 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 217850761 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 5706510559 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 23776065485 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 43733676321 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 249111297 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 239093772 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 4255255686 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 18549595260 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 39841128623 # number of overall miss cycles -system.l2c.overall_miss_latency::total 136812680803 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 9394 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 6908 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 649063 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 793918 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 593140 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 9225 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 6775 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 638214 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 703075 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 549947 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 3959659 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 2596817 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 2596817 # number of Writeback accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu0.data 582852 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu1.data 269705 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::total 852557 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 82467 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 72695 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 155162 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 15292 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 15623 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 30915 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 138632 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 108101 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 246733 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 9394 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 6908 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 649063 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 932550 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 593140 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 9225 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 6775 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 638214 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 811176 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 549947 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 4206392 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 9394 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 6908 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 649063 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 932550 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 593140 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 9225 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 6775 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 638214 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 811176 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 549947 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 4206392 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.279221 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.336277 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.100727 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.202433 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.497355 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.290407 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.378745 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.076090 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.188422 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.488956 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.247805 # miss rate for ReadReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.762804 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.515411 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::total 0.684542 # miss rate for WriteInvalidateReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.584949 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.642273 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.611806 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.599268 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.607950 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.603655 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.602949 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.537618 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.574325 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.279221 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.336277 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.100727 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.261973 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.497355 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.290407 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.378745 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.076090 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.234958 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.488956 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.266957 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.279221 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.336277 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.100727 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.261973 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.497355 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.290407 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.378745 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.076090 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.234958 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.488956 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.266957 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 93173.099123 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 93779.922944 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 87284.875019 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 99642.307034 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 148249.247701 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 92986.673012 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 93177.619641 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 87625.214901 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 99229.690953 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 148163.364161 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 126012.754241 # average ReadReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data 116.953307 # average WriteInvalidateReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data 281.751117 # average WriteInvalidateReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::total 156.206129 # average WriteInvalidateReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6389.007877 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5640.721032 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 6020.969525 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5140.168485 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5729.445883 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 5440.080431 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 92860.842585 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 92987.283428 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 92912.699347 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 93173.099123 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 93779.922944 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 87284.875019 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 97322.036508 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 148249.247701 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 92986.673012 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 93177.619641 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 87625.214901 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 97326.200785 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 148163.364161 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 121835.774545 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 93173.099123 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 93779.922944 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 87284.875019 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 97322.036508 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 148249.247701 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 92986.673012 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 93177.619641 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 87625.214901 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 97326.200785 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 148163.364161 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 121835.774545 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 14255 # number of cycles access was blocked +system.l2c.tags.replacements 1677022 # number of replacements +system.l2c.tags.tagsinuse 63960.007157 # Cycle average of tags in use +system.l2c.tags.total_refs 5998379 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1737036 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 3.453227 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 15741.839802 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 357.273948 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 484.122298 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4874.372847 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 16502.292162 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 20727.343192 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 11.818696 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 7.376448 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2388.813179 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1821.049873 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1043.704711 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.240201 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.005452 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.007387 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.074377 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.251805 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.316274 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000180 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000113 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.036450 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.027787 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.015926 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.975952 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 10260 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 258 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 49496 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 2 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 879 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 504 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 8874 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 254 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2439 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4866 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 41821 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.156555 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.003937 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.755249 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 75068652 # Number of tag accesses +system.l2c.tags.data_accesses 75068652 # Number of data accesses +system.l2c.Writeback_hits::writebacks 2604285 # number of Writeback hits +system.l2c.Writeback_hits::total 2604285 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 28546 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 29320 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 57866 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 6394 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 5412 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 11806 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 161030 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 157813 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 318843 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6923 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4910 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 644950 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 656166 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 305817 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5910 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4051 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 543185 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 555453 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 279182 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 3006547 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 6923 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4910 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 644950 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 817196 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 305817 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 5910 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 4051 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 543185 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 713266 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 279182 # number of demand (read+write) hits +system.l2c.demand_hits::total 3325390 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 6923 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 4910 # number of overall hits +system.l2c.overall_hits::cpu0.inst 644950 # number of overall hits +system.l2c.overall_hits::cpu0.data 817196 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 305817 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 5910 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 4051 # number of overall hits +system.l2c.overall_hits::cpu1.inst 543185 # number of overall hits +system.l2c.overall_hits::cpu1.data 713266 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 279182 # number of overall hits +system.l2c.overall_hits::total 3325390 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 46522 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 43915 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 90437 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 10622 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 7888 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 18510 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 567822 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 117808 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 685630 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 3723 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3679 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.inst 69821 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 197538 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 366356 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1749 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1250 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 41953 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 109150 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 201783 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 997002 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.dtb.walker 3723 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 3679 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 69821 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 765360 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 366356 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 1749 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 1250 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 41953 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 226958 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 201783 # number of demand (read+write) misses +system.l2c.demand_misses::total 1682632 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 3723 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 3679 # number of overall misses +system.l2c.overall_misses::cpu0.inst 69821 # number of overall misses +system.l2c.overall_misses::cpu0.data 765360 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 366356 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 1749 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 1250 # number of overall misses +system.l2c.overall_misses::cpu1.inst 41953 # number of overall misses +system.l2c.overall_misses::cpu1.data 226958 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 201783 # number of overall misses +system.l2c.overall_misses::total 1682632 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0.data 264342500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 275145500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 539488000 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 60602000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 45349000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 105951000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 73693634000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 12026393499 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 85720027499 # number of ReadExReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 347505000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 338090000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.inst 6068374002 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 19146364498 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 50780119067 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 166591000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 119960500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.inst 3610747500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 10634037494 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 27957366963 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 119169156024 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 347505000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 338090000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 6068374002 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 92839998498 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 50780119067 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 166591000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 119960500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 3610747500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 22660430993 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 27957366963 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 204889183523 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 347505000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 338090000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 6068374002 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 92839998498 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 50780119067 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 166591000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 119960500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 3610747500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 22660430993 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 27957366963 # number of overall miss cycles +system.l2c.overall_miss_latency::total 204889183523 # number of overall miss cycles +system.l2c.Writeback_accesses::writebacks 2604285 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 2604285 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 75068 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 73235 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 148303 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 17016 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 13300 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 30316 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 728852 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 275621 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 1004473 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 10646 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 8589 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.inst 714771 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 853704 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 672173 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 7659 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 5301 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.inst 585138 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 664603 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 480965 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 4003549 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 10646 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 8589 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 714771 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1582556 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 672173 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 7659 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 5301 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 585138 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 940224 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 480965 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 5008022 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 10646 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 8589 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 714771 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1582556 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 672173 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 7659 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 5301 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 585138 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 940224 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 480965 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 5008022 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.619731 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.599645 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.609812 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.624236 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.593083 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.610569 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.779064 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.427428 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.682577 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.349709 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.428339 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.097683 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.231389 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.545032 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.228359 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.235805 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.071698 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.164233 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.419538 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.249030 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.349709 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.428339 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.097683 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.483623 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.545032 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.228359 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.235805 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.071698 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.241387 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.419538 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.335987 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.349709 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.428339 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.097683 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.483623 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.545032 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.228359 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.235805 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.071698 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.241387 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.419538 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.335987 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 5682.096642 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6265.410452 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 5965.346042 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5705.328563 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5749.112576 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 5723.987034 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 129782.984809 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 102084.692882 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 125023.740938 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 93340.048348 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 91897.254689 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 86913.306913 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 96924.968857 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 138608.673168 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 95249.285306 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 95968.400000 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 86066.491073 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 97425.904663 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 138551.646883 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 119527.499467 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 93340.048348 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 91897.254689 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 86913.306913 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 121302.391682 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 138608.673168 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 95249.285306 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 95968.400000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 86066.491073 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 99844.160563 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 138551.646883 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 121767.078911 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 93340.048348 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 91897.254689 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 86913.306913 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 121302.391682 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 138608.673168 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 95249.285306 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 95968.400000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 86066.491073 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 99844.160563 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 138551.646883 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 121767.078911 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 9470 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 149 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 105 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 95.671141 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 90.190476 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 1263454 # number of writebacks -system.l2c.writebacks::total 1263454 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 235 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.data 55 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 249 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.data 31 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 570 # number of ReadReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu0.data 1 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 1 # number of ReadExReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 235 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 56 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 249 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 31 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 571 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 235 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 56 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 249 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 31 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 571 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 2623 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2323 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 65143 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 160660 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 295001 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 2679 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 2566 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 48313 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 132444 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 268900 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 980652 # number of ReadReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::cpu0.data 444602 # number of WriteInvalidateReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data 139009 # number of WriteInvalidateReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::total 583611 # number of WriteInvalidateReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 48239 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 46690 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 94929 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 9164 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 9498 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 18662 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 83587 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 58117 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 141704 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 2623 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 2323 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 65143 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 244247 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 295001 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 2679 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 2566 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 48313 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 190561 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 268900 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 1122356 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 2623 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 2323 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 65143 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 244247 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 295001 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 2679 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 2566 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 48313 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 190561 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 268900 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 1122356 # number of overall MSHR misses +system.l2c.writebacks::writebacks 1291985 # number of writebacks +system.l2c.writebacks::total 1291985 # number of writebacks +system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 127 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu0.data 25 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 183 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.data 37 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 372 # number of ReadSharedReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 127 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 25 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 183 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 37 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 372 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 127 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 25 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 183 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 37 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 372 # number of overall MSHR hits +system.l2c.CleanEvict_mshr_misses::writebacks 57543 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 57543 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 46522 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 43915 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 90437 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 10622 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 7888 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 18510 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 567822 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 117808 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 685630 # number of ReadExReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 3723 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 3679 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 69694 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 197513 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 366356 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1749 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1250 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 41770 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 109113 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 201783 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 996630 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 3723 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 3679 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 69694 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 765335 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 366356 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 1749 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 1250 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 41770 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 226921 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 201783 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 1682260 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 3723 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 3679 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 69694 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 765335 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 366356 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 1749 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 1250 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 41770 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 226921 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 201783 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 1682260 # number of overall MSHR misses system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 21294 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31767 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 20289 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 7124 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 60252 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 31179 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 7600 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 38779 # number of WriteReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 18066 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 59716 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 22269 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 15995 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 38264 # number of WriteReq MSHR uncacheable system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 21294 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 62946 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 42558 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 14724 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 99031 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 211330935 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 188610731 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 4870726193 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 14004672382 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 40114542013 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 215342695 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 206771700 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 3630382313 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 11489733691 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 36539403375 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 111471516028 # number of ReadReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data 17621248292 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 4582826059 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::total 22204074351 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 860739549 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 832018870 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 1692758419 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 163139115 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 169125946 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 332265061 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6720926126 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4681733537 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 11402659663 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 211330935 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 188610731 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 4870726193 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 20725598508 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 40114542013 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 215342695 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 206771700 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 3630382313 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 16171467228 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 36539403375 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 122874175691 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 211330935 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 188610731 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 4870726193 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 20725598508 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 40114542013 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 215342695 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 206771700 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 3630382313 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 16171467228 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 36539403375 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 122874175691 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1285623000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4741851751 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 4289000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 634532000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 6666295751 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4487720539 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 797339000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 5285059539 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1285623000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9229572290 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 4289000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1431871000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 11951355290 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.279221 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.336277 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.100365 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.202363 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.497355 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.290407 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.378745 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.075700 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.188378 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.488956 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.247661 # mshr miss rate for ReadReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.762804 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.515411 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.684542 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.584949 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.642273 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.611806 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.599268 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.607950 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.603655 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.602942 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.537618 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.574321 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.279221 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.336277 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.100365 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.261913 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.497355 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.290407 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.378745 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.075700 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.234919 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.488956 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.266822 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.279221 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.336277 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.100365 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.261913 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.497355 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.290407 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.378745 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.075700 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.234919 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.488956 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.266822 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 80568.408311 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 81192.738269 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 74769.755661 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 87169.627673 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135981.037396 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 80381.745054 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 80581.332814 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 75142.970070 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 86751.636095 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 135884.728059 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 113670.819035 # average ReadReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 39633.758490 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32967.837039 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 38046.017555 # average WriteInvalidateReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17843.229524 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17820.065753 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17831.836625 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17802.173178 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17806.479891 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17804.365073 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 80406.356563 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 80557.040745 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 80468.156601 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 80568.408311 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 81192.738269 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74769.755661 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 84855.079113 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135981.037396 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 80381.745054 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 80581.332814 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75142.970070 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 84862.417955 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 135884.728059 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 109478.788986 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 80568.408311 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 81192.738269 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74769.755661 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 84855.079113 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135981.037396 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 80381.745054 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 80581.332814 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75142.970070 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 84862.417955 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 135884.728059 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 109478.788986 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60374.894336 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 149269.737495 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 64014.925373 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 89069.623807 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 110640.240175 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 143934.075467 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 104913.026316 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 136286.638103 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60374.894336 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 146626.827598 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 64014.925373 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 97247.419180 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 120682.970888 # average overall mshr uncacheable latency +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 34061 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 97980 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 967860505 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 912939509 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 1880800014 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 220678503 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 163861499 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 384540002 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 68015414000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 10848313499 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 78863727499 # number of ReadExReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 310275000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 301300000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 5361144002 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 17169186498 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 47116559067 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 149101000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 107460500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 3179316500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 9539742994 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 25939536963 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 109173622524 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 310275000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 301300000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 5361144002 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 85184600498 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 47116559067 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 149101000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 107460500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 3179316500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 20388056493 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 25939536963 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 188037350023 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 310275000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 301300000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 5361144002 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 85184600498 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 47116559067 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 149101000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 107460500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 3179316500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 20388056493 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 25939536963 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 188037350023 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1320748000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3168263000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 4391000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2345032500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 6838434500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3288254533 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2131065000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 5419319533 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1320748000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 6456517533 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 4391000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 4476097500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 12257754033 # number of overall MSHR uncacheable cycles +system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.619731 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.599645 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.609812 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.624236 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.593083 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.610569 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.779064 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.427428 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.682577 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.349709 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.428339 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.097505 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.231360 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.545032 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.228359 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.235805 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.071385 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.164178 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.419538 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.248937 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.349709 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.428339 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.097505 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.483607 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.545032 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.228359 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.235805 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.071385 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.241348 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.419538 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.335913 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.349709 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.428339 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.097505 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.483607 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.545032 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.228359 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.235805 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.071385 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.241348 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.419538 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.335913 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20804.361485 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20788.785358 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20796.797926 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20775.607513 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20773.516608 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20774.716478 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 119782.984809 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 92084.692882 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 115023.740938 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 83340.048348 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 81897.254689 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 76924.039401 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 86926.868095 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 128608.673168 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 85249.285306 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 85968.400000 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 76114.831219 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 87429.939549 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 128551.646883 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 109542.781698 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 83340.048348 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 81897.254689 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 76924.039401 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 111303.678125 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 128608.673168 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 85249.285306 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 85968.400000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76114.831219 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 89846.495005 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 128551.646883 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 111776.627883 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 83340.048348 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 81897.254689 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 76924.039401 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 111303.678125 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 128608.673168 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 85249.285306 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 85968.400000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76114.831219 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 89846.495005 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 128551.646883 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 111776.627883 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62024.420024 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 156156.685889 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 65537.313433 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 129803.636666 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 114515.950499 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 147660.628362 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 133233.197874 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141629.718090 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62024.420024 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 151711.018680 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 65537.313433 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 131414.154018 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 125104.654348 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 1049844 # Transaction distribution -system.membus.trans_dist::ReadResp 1049844 # Transaction distribution -system.membus.trans_dist::WriteReq 38779 # Transaction distribution -system.membus.trans_dist::WriteResp 38779 # Transaction distribution -system.membus.trans_dist::Writeback 1370148 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 687460 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 687460 # Transaction distribution -system.membus.trans_dist::UpgradeReq 443336 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 306800 # Transaction distribution -system.membus.trans_dist::UpgradeResp 120479 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution -system.membus.trans_dist::ReadExReq 155568 # Transaction distribution -system.membus.trans_dist::ReadExResp 137698 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122614 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 59716 # Transaction distribution +system.membus.trans_dist::ReadResp 1065238 # Transaction distribution +system.membus.trans_dist::WriteReq 38264 # Transaction distribution +system.membus.trans_dist::WriteResp 38264 # Transaction distribution +system.membus.trans_dist::Writeback 1398687 # Transaction distribution +system.membus.trans_dist::CleanEvict 273545 # Transaction distribution +system.membus.trans_dist::UpgradeReq 431435 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 293289 # Transaction distribution +system.membus.trans_dist::UpgradeResp 115559 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution +system.membus.trans_dist::ReadExReq 699678 # Transaction distribution +system.membus.trans_dist::ReadExResp 679021 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1005522 # Transaction distribution +system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution +system.membus.trans_dist::InvalidateResp 106728 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122766 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27506 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5597252 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5747450 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335773 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 335773 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6083223 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155744 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25252 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5818316 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5966412 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342390 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 342390 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6308802 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155873 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 572 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55012 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 189917440 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 190128768 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14086528 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14086528 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 204215296 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 650589 # Total snoops (count) -system.membus.snoop_fanout::samples 4133180 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50504 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 190243904 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 190450853 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7261952 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7261952 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 197712805 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 632700 # Total snoops (count) +system.membus.snoop_fanout::samples 4309210 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 4133180 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 4309210 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 4133180 # Request fanout histogram -system.membus.reqLayer0.occupancy 98178497 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 4309210 # Request fanout histogram +system.membus.reqLayer0.occupancy 98315494 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 55000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 22861986 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 21255984 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 12090027529 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 9692600374 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 6852398799 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 9139212712 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 152088673 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 229129958 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -3772,49 +3840,50 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 4896771 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4889534 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38779 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38779 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 2596817 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 959438 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 852557 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 496684 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 319053 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 815737 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 143 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 143 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 305200 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 305200 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8223954 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6618870 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 14842824 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 276507544 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 214143912 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 490651456 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1673717 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 9649223 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.012003 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.108901 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 59718 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4906213 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38264 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38264 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 4003012 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1629651 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 482692 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 305095 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 787787 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 148 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 148 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1150777 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1150777 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 4853770 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 106728 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9404841 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6602998 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 16007839 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 297836822 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 190023375 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 487860197 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 3506825 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 13882904 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.137454 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.344326 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 9533399 98.80% 98.80% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 115824 1.20% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 11974647 86.25% 86.25% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 1908257 13.75% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 9649223 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 8593373447 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 13882904 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 8939333587 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2556000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2427000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4622045284 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 5448458649 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4138277748 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4022349362 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 13964 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 4812 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 5482 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 13871 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt index df0d44cf6..ef8414f55 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt @@ -1,141 +1,141 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.320469 # Number of seconds simulated -sim_ticks 51320468905000 # Number of ticks simulated -final_tick 51320468905000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.323721 # Number of seconds simulated +sim_ticks 51323721423000 # Number of ticks simulated +final_tick 51323721423000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 115752 # Simulator instruction rate (inst/s) -host_op_rate 136007 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6943747154 # Simulator tick rate (ticks/s) -host_mem_usage 724128 # Number of bytes of host memory used -host_seconds 7390.89 # Real time elapsed on the host -sim_insts 855512158 # Number of instructions simulated -sim_ops 1005211605 # Number of ops (including micro ops) simulated +host_inst_rate 113854 # Simulator instruction rate (inst/s) +host_op_rate 133781 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6847821533 # Simulator tick rate (ticks/s) +host_mem_usage 727476 # Number of bytes of host memory used +host_seconds 7494.90 # Real time elapsed on the host +sim_insts 853325819 # Number of instructions simulated +sim_ops 1002674190 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 202624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 193280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5755680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 42629000 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 415488 # Number of bytes read from this memory -system.physmem.bytes_read::total 49196072 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5755680 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5755680 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 69369152 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 203200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 189632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5727200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 73778504 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 419776 # Number of bytes read from this memory +system.physmem.bytes_read::total 80318312 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5727200 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5727200 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 68723904 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 69389732 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 3166 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 3020 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 105885 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 666091 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6492 # Number of read requests responded to by this memory -system.physmem.num_reads::total 784654 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1083893 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 68744484 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 3175 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2963 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 105440 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1152802 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6559 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1270939 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1073811 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1086466 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 3948 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 3766 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 112152 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 830643 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8096 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 958605 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 112152 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 112152 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1351686 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1076384 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 3959 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 3695 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 111590 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1437513 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8179 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1564935 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 111590 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 111590 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1339028 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1352087 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1351686 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 3948 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 3766 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 112152 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 831044 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8096 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2310692 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 784654 # Number of read requests accepted -system.physmem.writeReqs 1688539 # Number of write requests accepted -system.physmem.readBursts 784654 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1688539 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 50184064 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 33792 # Total number of bytes read from write queue -system.physmem.bytesWritten 104909952 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 49196072 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 107922404 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 528 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 49293 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 35218 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 46664 # Per bank write bursts -system.physmem.perBankRdBursts::1 51485 # Per bank write bursts -system.physmem.perBankRdBursts::2 48018 # Per bank write bursts -system.physmem.perBankRdBursts::3 46409 # Per bank write bursts -system.physmem.perBankRdBursts::4 44064 # Per bank write bursts -system.physmem.perBankRdBursts::5 51949 # Per bank write bursts -system.physmem.perBankRdBursts::6 45895 # Per bank write bursts -system.physmem.perBankRdBursts::7 48923 # Per bank write bursts -system.physmem.perBankRdBursts::8 45299 # Per bank write bursts -system.physmem.perBankRdBursts::9 70789 # Per bank write bursts -system.physmem.perBankRdBursts::10 48156 # Per bank write bursts -system.physmem.perBankRdBursts::11 46739 # Per bank write bursts -system.physmem.perBankRdBursts::12 48771 # Per bank write bursts -system.physmem.perBankRdBursts::13 48997 # Per bank write bursts -system.physmem.perBankRdBursts::14 45133 # Per bank write bursts -system.physmem.perBankRdBursts::15 46835 # Per bank write bursts -system.physmem.perBankWrBursts::0 99610 # Per bank write bursts -system.physmem.perBankWrBursts::1 104326 # Per bank write bursts -system.physmem.perBankWrBursts::2 103481 # Per bank write bursts -system.physmem.perBankWrBursts::3 102430 # Per bank write bursts -system.physmem.perBankWrBursts::4 101747 # Per bank write bursts -system.physmem.perBankWrBursts::5 104971 # Per bank write bursts -system.physmem.perBankWrBursts::6 100056 # Per bank write bursts -system.physmem.perBankWrBursts::7 103888 # Per bank write bursts -system.physmem.perBankWrBursts::8 99840 # Per bank write bursts -system.physmem.perBankWrBursts::9 106110 # Per bank write bursts -system.physmem.perBankWrBursts::10 102643 # Per bank write bursts -system.physmem.perBankWrBursts::11 100858 # Per bank write bursts -system.physmem.perBankWrBursts::12 103355 # Per bank write bursts -system.physmem.perBankWrBursts::13 103593 # Per bank write bursts -system.physmem.perBankWrBursts::14 100350 # Per bank write bursts -system.physmem.perBankWrBursts::15 101960 # Per bank write bursts +system.physmem.bw_write::total 1339429 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1339028 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 3959 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 3695 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 111590 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1437914 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8179 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2904365 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1270939 # Number of read requests accepted +system.physmem.writeReqs 1076384 # Number of write requests accepted +system.physmem.readBursts 1270939 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1076384 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 81299584 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 40512 # Total number of bytes read from write queue +system.physmem.bytesWritten 68742976 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 80318312 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 68744484 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 633 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 142017 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 76590 # Per bank write bursts +system.physmem.perBankRdBursts::1 80112 # Per bank write bursts +system.physmem.perBankRdBursts::2 82312 # Per bank write bursts +system.physmem.perBankRdBursts::3 76894 # Per bank write bursts +system.physmem.perBankRdBursts::4 75148 # Per bank write bursts +system.physmem.perBankRdBursts::5 84486 # Per bank write bursts +system.physmem.perBankRdBursts::6 75307 # Per bank write bursts +system.physmem.perBankRdBursts::7 76047 # Per bank write bursts +system.physmem.perBankRdBursts::8 76921 # Per bank write bursts +system.physmem.perBankRdBursts::9 104197 # Per bank write bursts +system.physmem.perBankRdBursts::10 75653 # Per bank write bursts +system.physmem.perBankRdBursts::11 81028 # Per bank write bursts +system.physmem.perBankRdBursts::12 74845 # Per bank write bursts +system.physmem.perBankRdBursts::13 77383 # Per bank write bursts +system.physmem.perBankRdBursts::14 76622 # Per bank write bursts +system.physmem.perBankRdBursts::15 76761 # Per bank write bursts +system.physmem.perBankWrBursts::0 64108 # Per bank write bursts +system.physmem.perBankWrBursts::1 67910 # Per bank write bursts +system.physmem.perBankWrBursts::2 69982 # Per bank write bursts +system.physmem.perBankWrBursts::3 67432 # Per bank write bursts +system.physmem.perBankWrBursts::4 65959 # Per bank write bursts +system.physmem.perBankWrBursts::5 70786 # Per bank write bursts +system.physmem.perBankWrBursts::6 64733 # Per bank write bursts +system.physmem.perBankWrBursts::7 66187 # Per bank write bursts +system.physmem.perBankWrBursts::8 67287 # Per bank write bursts +system.physmem.perBankWrBursts::9 71812 # Per bank write bursts +system.physmem.perBankWrBursts::10 65064 # Per bank write bursts +system.physmem.perBankWrBursts::11 69201 # Per bank write bursts +system.physmem.perBankWrBursts::12 65082 # Per bank write bursts +system.physmem.perBankWrBursts::13 66370 # Per bank write bursts +system.physmem.perBankWrBursts::14 66024 # Per bank write bursts +system.physmem.perBankWrBursts::15 66172 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 560 # Number of times write queue was full causing retry -system.physmem.totGap 51320467654000 # Total gap between requests +system.physmem.numWrRetry 12 # Number of times write queue was full causing retry +system.physmem.totGap 51323720227500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 21272 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 763369 # Read request sizes (log2) +system.physmem.readPktSize::6 1249654 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1685966 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 521104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 214865 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 29991 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 12339 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 553 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 577 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 468 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 726 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 459 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1858 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 231 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 131 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 121 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 109 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 81 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 65 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1073811 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 646219 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 339232 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 151287 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 128129 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 684 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 489 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 502 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 533 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 812 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 936 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 392 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 192 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 135 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 119 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 118 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 100 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 87 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 63 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -159,160 +159,164 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 25954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 62903 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 63057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 90168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 80361 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 95410 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 92759 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 101527 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 92557 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 106064 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 84728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 110064 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 83833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 78687 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 89131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 74275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 70833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 66282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 8883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 7376 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 8392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 9232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 9334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 8685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 9103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 9266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 8544 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 8245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 7856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 7810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 7132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 5765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 6644 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 5091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 4890 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 3473 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 3916 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 2921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 3295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 2570 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 3011 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 2474 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 3139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 2181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 2765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 1862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 4424 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 820 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 1539 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 512637 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 302.540847 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 171.812512 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 339.509823 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 207576 40.49% 40.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 124268 24.24% 64.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 44401 8.66% 73.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 23774 4.64% 78.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 16232 3.17% 81.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 10193 1.99% 83.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8192 1.60% 84.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 7548 1.47% 86.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 70453 13.74% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 512637 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 56080 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 13.981651 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 75.084718 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 56073 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 5 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 56080 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 56080 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 29.229993 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 22.064414 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 40.823681 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-31 46001 82.03% 82.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-63 3837 6.84% 88.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-95 4190 7.47% 96.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-127 975 1.74% 98.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-159 304 0.54% 98.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-191 127 0.23% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-223 99 0.18% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-255 80 0.14% 99.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-287 114 0.20% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-319 122 0.22% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-351 75 0.13% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-383 40 0.07% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-415 26 0.05% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::416-447 17 0.03% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::448-479 12 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-511 8 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-543 13 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-575 10 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::576-607 5 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::608-639 3 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::640-671 4 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::672-703 5 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::704-735 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::736-767 3 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::768-799 4 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::896-927 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::992-1023 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1056-1087 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1184-1215 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 56080 # Writes before turning the bus around for reads -system.physmem.totQLat 15388206863 # Total ticks spent queuing -system.physmem.totMemAccLat 30090569363 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 3920630000 # Total ticks spent in databus transfers -system.physmem.avgQLat 19624.66 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 11927 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 14439 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 31518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 44897 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 53343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 63481 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 63532 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 67021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 67803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 70464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 69167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 70329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 66867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 85010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 86471 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 65847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 69713 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 62929 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1006 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 572 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 637 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 503 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 415 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 439 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 475 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 414 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 362 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 294 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 42 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 481355 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 311.708207 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 178.914901 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 339.146013 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 186832 38.81% 38.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 113175 23.51% 62.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 45398 9.43% 71.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 23450 4.87% 76.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 18101 3.76% 80.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 11671 2.42% 82.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 10460 2.17% 84.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 8315 1.73% 86.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 63953 13.29% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 481355 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 61522 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 20.647411 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 265.936082 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 61519 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-12287 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::63488-65535 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 61522 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 61522 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.458942 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.948779 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 6.823778 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 58490 95.07% 95.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 664 1.08% 96.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 448 0.73% 96.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 190 0.31% 97.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 308 0.50% 97.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 527 0.86% 98.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 143 0.23% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 33 0.05% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 36 0.06% 98.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 18 0.03% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 32 0.05% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 22 0.04% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 426 0.69% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 45 0.07% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 33 0.05% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 35 0.06% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 13 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 2 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 5 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 31 0.05% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 6 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-243 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 61522 # Writes before turning the bus around for reads +system.physmem.totQLat 31530968444 # Total ticks spent queuing +system.physmem.totMemAccLat 55349205944 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6351530000 # Total ticks spent in databus transfers +system.physmem.avgQLat 24821.55 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38374.66 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 0.98 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.04 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 0.96 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.10 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 43571.55 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.58 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.34 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.56 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.34 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.46 # Average write queue length when enqueuing -system.physmem.readRowHits 598254 # Number of row buffer hits during reads -system.physmem.writeRowHits 1312451 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.30 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.06 # Row buffer hit rate for writes -system.physmem.avgGap 20750692.59 # Average gap between requests -system.physmem.pageHitRate 78.84 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1947569400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1062661875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2990566800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5316898320 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3352003380960 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1226375853165 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29716511616000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34306208546520 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.470318 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49436040472112 # Time in different power states -system.physmem_0.memoryStateTime::REF 1713703160000 # Time in different power states +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing +system.physmem.avgWrQLen 22.31 # Average write queue length when enqueuing +system.physmem.readRowHits 1047361 # Number of row buffer hits during reads +system.physmem.writeRowHits 815697 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.45 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.94 # Row buffer hit rate for writes +system.physmem.avgGap 21864788.20 # Average gap between requests +system.physmem.pageHitRate 79.47 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1828287720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 997577625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4889757600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3480388560 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3352215959040 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1226219398425 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29718601656750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34308233025720 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.467372 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49439480717043 # Time in different power states +system.physmem_0.memoryStateTime::REF 1713811840000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 170725136888 # Time in different power states +system.physmem_0.memoryStateTime::ACT 170428636707 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1927966320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1051965750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3125569200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5305234320 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3352003380960 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1229368112910 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29713886826750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34306669056210 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.479291 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49431639282027 # Time in different power states -system.physmem_1.memoryStateTime::REF 1713703160000 # Time in different power states +system.physmem_1.actEnergy 1810756080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 988011750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 5018598000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3479837760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3352215959040 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1228704019020 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29716422156750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34308639338400 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.475289 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49435820968594 # Time in different power states +system.physmem_1.memoryStateTime::REF 1713811840000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 175126075973 # Time in different power states +system.physmem_1.memoryStateTime::ACT 174088371406 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 400 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory @@ -336,15 +340,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 226088242 # Number of BP lookups -system.cpu.branchPred.condPredicted 151212051 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12236747 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 159576730 # Number of BTB lookups -system.cpu.branchPred.BTBHits 104394184 # Number of BTB hits +system.cpu.branchPred.lookups 225557622 # Number of BP lookups +system.cpu.branchPred.condPredicted 150824960 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12221670 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 159273353 # Number of BTB lookups +system.cpu.branchPred.BTBHits 104130221 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 65.419428 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 31024336 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 344701 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 65.378307 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 30957399 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 344598 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -375,86 +379,87 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 945525 # Table walker walks requested -system.cpu.dtb.walker.walksLong 945525 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 17037 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 156802 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 426099 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 519426 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 1842.763936 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 11883.435839 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-32767 513062 98.77% 98.77% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::32768-65535 3320 0.64% 99.41% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::65536-98303 1249 0.24% 99.65% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::98304-131071 1137 0.22% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::131072-163839 115 0.02% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::163840-196607 205 0.04% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::196608-229375 84 0.02% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::229376-262143 60 0.01% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::262144-294911 94 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::294912-327679 5 0.00% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::327680-360447 21 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::360448-393215 44 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::393216-425983 30 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 519426 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 477950 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 21079.702044 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 16676.748393 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 15514.599645 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 472923 98.95% 98.95% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 4117 0.86% 99.81% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 574 0.12% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 200 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 75 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 25 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 26 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 8 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walks 951838 # Table walker walks requested +system.cpu.dtb.walker.walksLong 951838 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 16475 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 156308 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 435006 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 516832 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 1986.510123 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 12487.736879 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-32767 508349 98.36% 98.36% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::32768-65535 5443 1.05% 99.41% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::65536-98303 1244 0.24% 99.65% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::98304-131071 1085 0.21% 99.86% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::131072-163839 165 0.03% 99.89% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::163840-196607 178 0.03% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::196608-229375 121 0.02% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::229376-262143 54 0.01% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::262144-294911 95 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::294912-327679 7 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::327680-360447 5 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::360448-393215 38 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::393216-425983 41 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::425984-458751 7 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 516832 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 485267 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 21943.293074 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 17562.054008 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 15786.896980 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 475094 97.90% 97.90% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 9290 1.91% 99.82% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 546 0.11% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 199 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 82 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 29 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 20 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 5 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 477950 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 768700308080 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.730043 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.512304 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 766743156580 99.75% 99.75% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 1060609500 0.14% 99.88% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 401667500 0.05% 99.94% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 174666000 0.02% 99.96% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 138312000 0.02% 99.98% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 106588500 0.01% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 24500000 0.00% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 48487000 0.01% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::16-17 2321000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 768700308080 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 156803 90.20% 90.20% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 17037 9.80% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 173840 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 945525 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkCompletionTime::total 485267 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 776250627376 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.722476 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.519579 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 774163165376 99.73% 99.73% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 1120728500 0.14% 99.88% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 435636500 0.06% 99.93% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 187638500 0.02% 99.96% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 148036000 0.02% 99.97% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 113935000 0.01% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 26323500 0.00% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 52542500 0.01% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::16-17 2621500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 776250627376 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 156309 90.46% 90.46% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 16475 9.54% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 172784 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 951838 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 945525 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 173840 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 951838 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 172784 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 173840 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 1119365 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 172784 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 1124622 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 170900022 # DTB read hits -system.cpu.dtb.read_misses 675244 # DTB read misses -system.cpu.dtb.write_hits 148749524 # DTB write hits -system.cpu.dtb.write_misses 270281 # DTB write misses +system.cpu.dtb.read_hits 170417440 # DTB read hits +system.cpu.dtb.read_misses 677013 # DTB read misses +system.cpu.dtb.write_hits 148384109 # DTB write hits +system.cpu.dtb.write_misses 274825 # DTB write misses system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 39859 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 1027 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 72825 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 117 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 10420 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_tlb_mva_asid 39714 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1025 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 72556 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 110 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 10696 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 69816 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 171575266 # DTB read accesses -system.cpu.dtb.write_accesses 149019805 # DTB write accesses +system.cpu.dtb.perms_faults 70061 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 171094453 # DTB read accesses +system.cpu.dtb.write_accesses 148658934 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 319649546 # DTB hits -system.cpu.dtb.misses 945525 # DTB misses -system.cpu.dtb.accesses 320595071 # DTB accesses +system.cpu.dtb.hits 318801549 # DTB hits +system.cpu.dtb.misses 951838 # DTB misses +system.cpu.dtb.accesses 319753387 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -484,209 +489,209 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 161869 # Table walker walks requested -system.cpu.itb.walker.walksLong 161869 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walks 162167 # Table walker walks requested +system.cpu.itb.walker.walksLong 162167 # Table walker walks initiated with long descriptors system.cpu.itb.walker.walksLongTerminationLevel::Level2 1433 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 122204 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 17648 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 144221 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 1045.076653 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 6935.040907 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-32767 143697 99.64% 99.64% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::32768-65535 129 0.09% 99.73% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::65536-98303 259 0.18% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::98304-131071 98 0.07% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::131072-163839 18 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::163840-196607 10 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::196608-229375 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::229376-262143 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::262144-294911 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 144221 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 141285 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 26183.154631 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 21986.379296 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 16137.175101 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 139260 98.57% 98.57% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 1739 1.23% 99.80% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 189 0.13% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 61 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 22 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 9 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksLongTerminationLevel::Level3 122178 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 17760 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 144407 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 1087.128740 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 7079.961036 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-32767 143546 99.40% 99.40% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::32768-65535 491 0.34% 99.74% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::65536-98303 245 0.17% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::98304-131071 86 0.06% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::131072-163839 14 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::163840-196607 13 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::196608-229375 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::229376-262143 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::262144-294911 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::294912-327679 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 144407 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 141371 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 27408.566821 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 23535.121999 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 16611.953111 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 138940 98.28% 98.28% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 2106 1.49% 99.77% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 209 0.15% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 62 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 27 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 18 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 7 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 141285 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 652736132088 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.935835 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.245289 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 41920855152 6.42% 6.42% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 610778213436 93.57% 99.99% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 36269000 0.01% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::3 794000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::4 500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 652736132088 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 122204 98.84% 98.84% # Table walker page sizes translated +system.cpu.itb.walker.walkCompletionTime::total 141371 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 655988501088 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.936740 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.243710 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 41542191152 6.33% 6.33% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 614402729936 93.66% 99.99% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 43110500 0.01% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 467500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::4 2000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 655988501088 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 122178 98.84% 98.84% # Table walker page sizes translated system.cpu.itb.walker.walkPageSizes::2M 1433 1.16% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 123637 # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 123611 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 161869 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 161869 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 162167 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 162167 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 123637 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 123637 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 285506 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 359459512 # ITB inst hits -system.cpu.itb.inst_misses 161869 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 123611 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 123611 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 285778 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 358625455 # ITB inst hits +system.cpu.itb.inst_misses 162167 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 39859 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 1027 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 53398 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 39714 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1025 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 53363 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 372095 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 372145 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 359621381 # ITB inst accesses -system.cpu.itb.hits 359459512 # DTB hits -system.cpu.itb.misses 161869 # DTB misses -system.cpu.itb.accesses 359621381 # DTB accesses -system.cpu.numCycles 1580751099 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 358787622 # ITB inst accesses +system.cpu.itb.hits 358625455 # DTB hits +system.cpu.itb.misses 162167 # DTB misses +system.cpu.itb.accesses 358787622 # DTB accesses +system.cpu.numCycles 1590418745 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 647898483 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1008720689 # Number of instructions fetch has processed -system.cpu.fetch.Branches 226088242 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 135418520 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 855549558 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 26139542 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 3573192 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 26865 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9268939 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1033386 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 427 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 359070671 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6123790 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 48662 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 1530420621 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.772272 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.159981 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 646410999 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1006402404 # Number of instructions fetch has processed +system.cpu.fetch.Branches 225557622 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 135087620 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 866562323 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 26107474 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 3678311 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 25439 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 9275413 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1023850 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 676 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 358236204 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6112300 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 49056 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 1540030748 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.765724 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.157325 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 968902908 63.31% 63.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 215807485 14.10% 77.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 71036994 4.64% 82.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 274673234 17.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 979927440 63.63% 63.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 215057699 13.96% 77.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 70955696 4.61% 82.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 274089913 17.80% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1530420621 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.143026 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.638127 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 526178421 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 508648126 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 435713994 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 50619608 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9260472 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 33861678 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 3868815 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1093600087 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 29077129 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9260472 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 571338545 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 48532565 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 364379914 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 441167933 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 95741192 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1073752213 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 6802962 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 5086497 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 358848 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 628248 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 43820548 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 20190 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1021575372 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1655508848 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1270030956 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1469892 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 955737015 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 65838354 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 27320538 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23636945 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 103635545 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 174900719 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 152333814 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 9971771 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9081144 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1038303468 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 27624460 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1054196021 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3299994 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 60716319 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33847358 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 315461 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1530420621 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.688828 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.927358 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1540030748 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.141823 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.632791 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 525466953 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 519947088 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 434864784 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 50506307 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 9245616 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 33796734 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 3867997 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1090931528 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 29050280 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 9245616 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 570424085 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 50840114 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 363017689 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 440398811 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 106104433 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1071115355 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 6801917 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 5040663 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 343395 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 645255 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 54344412 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 20434 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1018974666 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1651092433 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1266893179 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1473696 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 953236782 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 65737881 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 27206823 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23528426 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 103688094 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 174464093 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 151959443 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 9931077 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9032567 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1035787653 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 27506074 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1051526043 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3293799 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 60619533 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33780075 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 314140 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1540030748 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.682795 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.925415 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 877745445 57.35% 57.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 337069342 22.02% 79.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 236293073 15.44% 94.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 72729594 4.75% 99.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6564084 0.43% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 19083 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 888949202 57.72% 57.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 336251490 21.83% 79.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 235798342 15.31% 94.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 72468185 4.71% 99.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6544331 0.42% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 19198 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1530420621 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1540030748 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 58206836 35.09% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 99242 0.06% 35.15% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 26725 0.02% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 744 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.17% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44573023 26.87% 62.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 62969604 37.96% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 58035888 35.01% 35.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 99674 0.06% 35.07% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 26738 0.02% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 574 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44566242 26.88% 61.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 63041416 38.03% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 57 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 725956407 68.86% 68.86% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2542188 0.24% 69.10% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 123122 0.01% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 724142674 68.87% 68.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2543730 0.24% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 122779 0.01% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 376 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.12% # Type of FU issued @@ -708,102 +713,102 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.12% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 120904 0.01% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 121012 0.01% 69.13% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.13% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.13% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 174804143 16.58% 85.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 150649152 14.29% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 174312709 16.58% 85.71% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 150282706 14.29% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1054196021 # Type of FU issued -system.cpu.iq.rate 0.666896 # Inst issue rate -system.cpu.iq.fu_busy_cnt 165876174 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.157349 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3805514237 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1125839347 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1036122901 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 2474593 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 946702 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 909865 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1218517790 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1554348 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 4347401 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1051526043 # Type of FU issued +system.cpu.iq.rate 0.661163 # Inst issue rate +system.cpu.iq.fu_busy_cnt 165770532 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.157648 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3809671307 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1123107931 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1033541701 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 2475857 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 947397 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 910004 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1215741366 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1555198 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 4333965 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 13878328 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14961 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 143108 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6347044 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 13839303 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14833 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 143349 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6338712 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2552620 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1870361 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2540349 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1552925 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9260472 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 6554396 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 3651492 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1066150871 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 9245616 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 6389360 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 5797347 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1063516239 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 174900719 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 152333814 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 23208148 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 59700 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3513413 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 143108 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3675827 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 5121930 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8797757 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1042985483 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 170888878 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10276947 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 174464093 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 151959443 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23100216 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 59008 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5663632 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 143349 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3667729 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 5111764 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8779493 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1040328227 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 170406440 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10257681 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 222943 # number of nop insts executed -system.cpu.iew.exec_refs 319634404 # number of memory reference insts executed -system.cpu.iew.exec_branches 197926826 # Number of branches executed -system.cpu.iew.exec_stores 148745526 # Number of stores executed -system.cpu.iew.exec_rate 0.659804 # Inst execution rate -system.cpu.iew.wb_sent 1037843882 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1037032766 # cumulative count of insts written-back -system.cpu.iew.wb_producers 441278048 # num instructions producing a value -system.cpu.iew.wb_consumers 713779914 # num instructions consuming a value +system.cpu.iew.exec_nop 222512 # number of nop insts executed +system.cpu.iew.exec_refs 318786335 # number of memory reference insts executed +system.cpu.iew.exec_branches 197400349 # Number of branches executed +system.cpu.iew.exec_stores 148379895 # Number of stores executed +system.cpu.iew.exec_rate 0.654122 # Inst execution rate +system.cpu.iew.wb_sent 1035262700 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1034451705 # cumulative count of insts written-back +system.cpu.iew.wb_producers 440415620 # num instructions producing a value +system.cpu.iew.wb_consumers 712619707 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.656038 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.618227 # average fanout of values written-back +system.cpu.iew.wb_rate 0.650427 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.618023 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 51563874 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 27308999 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 8427448 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1518403714 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.662019 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.290608 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 51498978 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 27191934 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 8413549 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1528028900 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.656188 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.286676 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 1001866977 65.98% 65.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 290832617 19.15% 85.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 121646355 8.01% 93.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 36740427 2.42% 95.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 28447666 1.87% 97.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14105700 0.93% 98.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8667985 0.57% 98.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4229973 0.28% 99.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 11866014 0.78% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 1013092181 66.30% 66.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 289858237 18.97% 85.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 121052617 7.92% 93.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 36682667 2.40% 95.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 28563883 1.87% 97.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14105791 0.92% 98.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8655946 0.57% 98.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4198069 0.27% 99.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 11819509 0.77% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1518403714 # Number of insts commited each cycle -system.cpu.commit.committedInsts 855512158 # Number of instructions committed -system.cpu.commit.committedOps 1005211605 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1528028900 # Number of insts commited each cycle +system.cpu.commit.committedInsts 853325819 # Number of instructions committed +system.cpu.commit.committedOps 1002674190 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 307009160 # Number of memory references committed -system.cpu.commit.loads 161022390 # Number of loads committed -system.cpu.commit.membars 6998413 # Number of memory barriers committed -system.cpu.commit.branches 190975004 # Number of branches committed -system.cpu.commit.fp_insts 896164 # Number of committed floating point instructions. -system.cpu.commit.int_insts 923410198 # Number of committed integer instructions. -system.cpu.commit.function_calls 25456304 # Number of function calls committed. +system.cpu.commit.refs 306245520 # Number of memory references committed +system.cpu.commit.loads 160624789 # Number of loads committed +system.cpu.commit.membars 6977905 # Number of memory barriers committed +system.cpu.commit.branches 190474151 # Number of branches committed +system.cpu.commit.fp_insts 896785 # Number of committed floating point instructions. +system.cpu.commit.int_insts 921116747 # Number of committed integer instructions. +system.cpu.commit.function_calls 25400785 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 695830631 69.22% 69.22% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 2161783 0.22% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 98401 0.01% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 694059947 69.22% 69.22% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2158876 0.22% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 98131 0.01% 69.45% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.45% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.45% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.45% # Class of committed instruction @@ -826,522 +831,535 @@ system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.45% # system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.45% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.45% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 111588 0.01% 69.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 111674 0.01% 69.46% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 161022390 16.02% 85.48% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 145986770 14.52% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 160624789 16.02% 85.48% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 145620731 14.52% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 1005211605 # Class of committed instruction -system.cpu.commit.bw_lim_events 11866014 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 2555711925 # The number of ROB reads -system.cpu.rob.rob_writes 2125474325 # The number of ROB writes -system.cpu.timesIdled 8142220 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 50330478 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 101060186847 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 855512158 # Number of Instructions Simulated -system.cpu.committedOps 1005211605 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.847725 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.847725 # CPI: Total CPI of All Threads -system.cpu.ipc 0.541206 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.541206 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1234726115 # number of integer regfile reads -system.cpu.int_regfile_writes 737118708 # number of integer regfile writes -system.cpu.fp_regfile_reads 1461359 # number of floating regfile reads -system.cpu.fp_regfile_writes 784484 # number of floating regfile writes -system.cpu.cc_regfile_reads 227546613 # number of cc regfile reads -system.cpu.cc_regfile_writes 228200703 # number of cc regfile writes -system.cpu.misc_regfile_reads 2526906641 # number of misc regfile reads -system.cpu.misc_regfile_writes 27367002 # number of misc regfile writes -system.cpu.dcache.tags.replacements 9794555 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.983548 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 285502634 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9795067 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.147594 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1659133250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.983548 # Average occupied blocks per requestor +system.cpu.commit.op_class_0::total 1002674190 # Class of committed instruction +system.cpu.commit.bw_lim_events 11819509 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 2562796067 # The number of ROB reads +system.cpu.rob.rob_writes 2120254358 # The number of ROB writes +system.cpu.timesIdled 8129447 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 50387997 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 101057024238 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 853325819 # Number of Instructions Simulated +system.cpu.committedOps 1002674190 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.863788 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.863788 # CPI: Total CPI of All Threads +system.cpu.ipc 0.536542 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.536542 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1231590969 # number of integer regfile reads +system.cpu.int_regfile_writes 735370525 # number of integer regfile writes +system.cpu.fp_regfile_reads 1462122 # number of floating regfile reads +system.cpu.fp_regfile_writes 782688 # number of floating regfile writes +system.cpu.cc_regfile_reads 226859046 # number of cc regfile reads +system.cpu.cc_regfile_writes 227515194 # number of cc regfile writes +system.cpu.misc_regfile_reads 2534481060 # number of misc regfile reads +system.cpu.misc_regfile_writes 27245755 # number of misc regfile writes +system.cpu.dcache.tags.replacements 9758519 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.983709 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 284707567 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9759031 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.173754 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1642601500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.983709 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999968 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999968 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 409 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 386 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1246939843 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1246939843 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 148420477 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 148420477 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 129257116 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 129257116 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 380071 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 380071 # number of SoftPFReq hits -system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 323830 # number of WriteInvalidateReq hits -system.cpu.dcache.WriteInvalidateReq_hits::total 323830 # number of WriteInvalidateReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3338713 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3338713 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 3738459 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3738459 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 277677593 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 277677593 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 278057664 # number of overall hits -system.cpu.dcache.overall_hits::total 278057664 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9529450 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9529450 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 11422113 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 11422113 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1191409 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1191409 # number of SoftPFReq misses -system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1233320 # number of WriteInvalidateReq misses -system.cpu.dcache.WriteInvalidateReq_misses::total 1233320 # number of WriteInvalidateReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 451226 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 451226 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 6 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 6 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 20951563 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 20951563 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 22142972 # number of overall misses -system.cpu.dcache.overall_misses::total 22142972 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 145395860730 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 145395860730 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 336812014094 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 336812014094 # number of WriteReq miss cycles -system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 35299806246 # number of WriteInvalidateReq miss cycles -system.cpu.dcache.WriteInvalidateReq_miss_latency::total 35299806246 # number of WriteInvalidateReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6459718484 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 6459718484 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 237001 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 237001 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 482207874824 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 482207874824 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 482207874824 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 482207874824 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 157949927 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 157949927 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 140679229 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 140679229 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1571480 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1571480 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1557150 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::total 1557150 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3789939 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3789939 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 3738465 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 3738465 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 298629156 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 298629156 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 300200636 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 300200636 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060332 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.060332 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081193 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.081193 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.758145 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.758145 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.792037 # miss rate for WriteInvalidateReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.792037 # miss rate for WriteInvalidateReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.119059 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.119059 # miss rate for LoadLockedReq accesses +system.cpu.dcache.tags.tag_accesses 1243872376 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1243872376 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 147964440 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 147964440 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 128940955 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 128940955 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 380183 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 380183 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 324678 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 324678 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3327415 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3327415 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 3725844 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 3725844 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 276905395 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 276905395 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 277285578 # number of overall hits +system.cpu.dcache.overall_hits::total 277285578 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9612542 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9612542 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 11385353 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 11385353 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1184834 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1184834 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1232047 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1232047 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 450033 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 450033 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 7 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 7 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 20997895 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 20997895 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 22182729 # number of overall misses +system.cpu.dcache.overall_misses::total 22182729 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 144669003500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 144669003500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 330867751444 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 330867751444 # number of WriteReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 63675897168 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 63675897168 # number of WriteLineReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6433485000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 6433485000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 251000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 251000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 475536754944 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 475536754944 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 475536754944 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 475536754944 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 157576982 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 157576982 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 140326308 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 140326308 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1565017 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1565017 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::cpu.data 1556725 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 1556725 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3777448 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3777448 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 3725851 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 3725851 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 297903290 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 297903290 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 299468307 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 299468307 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061002 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.061002 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081135 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.081135 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.757074 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.757074 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.791435 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.791435 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.119137 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.119137 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000002 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.070159 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.070159 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.073761 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.073761 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15257.529105 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15257.529105 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29487.715110 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29487.715110 # average WriteReq miss latency -system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 28621.773948 # average WriteInvalidateReq miss latency -system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 28621.773948 # average WriteInvalidateReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14315.927017 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14315.927017 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 39500.166667 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 39500.166667 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23015.365241 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23015.365241 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21777.016871 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21777.016871 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 20545206 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.070486 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.070486 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.074074 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.074074 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15050.025633 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15050.025633 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29060.825031 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29060.825031 # average WriteReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 51683.009794 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 51683.009794 # average WriteLineReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14295.584990 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14295.584990 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 35857.142857 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 35857.142857 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22646.877458 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22646.877458 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21437.252150 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21437.252150 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 35158879 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1559097 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1606955 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.177632 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.879193 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 7577660 # number of writebacks -system.cpu.dcache.writebacks::total 7577660 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4366240 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4366240 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9388231 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 9388231 # number of WriteReq MSHR hits -system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.data 7155 # number of WriteInvalidateReq MSHR hits -system.cpu.dcache.WriteInvalidateReq_mshr_hits::total 7155 # number of WriteInvalidateReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 220115 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 220115 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 13754471 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 13754471 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 13754471 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 13754471 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5163210 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5163210 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2033882 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2033882 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1184642 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1184642 # number of SoftPFReq MSHR misses -system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data 1226165 # number of WriteInvalidateReq MSHR misses -system.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1226165 # number of WriteInvalidateReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 231111 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 231111 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 6 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 6 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 7197092 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 7197092 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 8381734 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 8381734 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33661 # number of ReadReq MSHR uncacheable -system.cpu.dcache.ReadReq_mshr_uncacheable::total 33661 # number of ReadReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33682 # number of WriteReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::total 33682 # number of WriteReq MSHR uncacheable -system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67343 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 67343 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 73626554579 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 73626554579 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 56871439750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 56871439750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 19552019274 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 19552019274 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 33205804688 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 33205804688 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2956928250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2956928250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 227999 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 227999 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 130497994329 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 130497994329 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 150050013603 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 150050013603 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5746385500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5746385500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5629281968 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5629281968 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11375667468 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 11375667468 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032689 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032689 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014458 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014458 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.753838 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.753838 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.787442 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.787442 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060980 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060980 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.writebacks::writebacks 7549082 # number of writebacks +system.cpu.dcache.writebacks::total 7549082 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4467834 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4467834 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9360902 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 9360902 # number of WriteReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 7079 # number of WriteLineReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::total 7079 # number of WriteLineReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 219205 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 219205 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 13828736 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 13828736 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 13828736 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 13828736 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5144708 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5144708 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2024451 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2024451 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1178103 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1178103 # number of SoftPFReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1224968 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 1224968 # number of WriteLineReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 230828 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 230828 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 7 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 7 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 7169159 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 7169159 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 8347262 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 8347262 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33678 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadReq_mshr_uncacheable::total 33678 # number of ReadReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33696 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 33696 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67374 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 67374 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75818409500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 75818409500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57062160713 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 57062160713 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 20148080000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 20148080000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 62191648168 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 62191648168 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3063087000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3063087000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 244000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 244000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 132880570213 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 132880570213 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 153028650213 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 153028650213 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5828327500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5828327500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5707957967 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5707957967 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11536285467 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 11536285467 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032649 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032649 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014427 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014427 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.752773 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.752773 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786888 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786888 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.061107 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.061107 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000002 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024100 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.024100 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027920 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.027920 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14259.841180 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14259.841180 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27962.015373 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27962.015373 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16504.580518 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16504.580518 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 27081.024730 # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 27081.024730 # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12794.407233 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12794.407233 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 37999.833333 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 37999.833333 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18132.044766 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18132.044766 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17902.025238 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17902.025238 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 170713.451769 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 170713.451769 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 167130.276349 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 167130.276349 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 168921.305377 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 168921.305377 # average overall mshr uncacheable latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024065 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.024065 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027874 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.027874 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14737.164772 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14737.164772 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28186.486466 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28186.486466 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17102.137929 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17102.137929 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 50770.018619 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 50770.018619 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13269.997574 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13269.997574 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 34857.142857 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 34857.142857 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18535.029034 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18535.029034 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18332.795857 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18332.795857 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173060.380664 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173060.380664 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 169395.713646 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169395.713646 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 171227.557619 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 171227.557619 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 15070815 # number of replacements -system.cpu.icache.tags.tagsinuse 511.953323 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 343233622 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15071327 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 22.773948 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 14049577000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.953323 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999909 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999909 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 15042093 # number of replacements +system.cpu.icache.tags.tagsinuse 511.944879 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 342405629 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15042605 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 22.762389 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 17214303500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.944879 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999892 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999892 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 102 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 99 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 374120916 # Number of tag accesses -system.cpu.icache.tags.data_accesses 374120916 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 343233622 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 343233622 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 343233622 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 343233622 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 343233622 # number of overall hits -system.cpu.icache.overall_hits::total 343233622 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 15815747 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 15815747 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 15815747 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 15815747 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 15815747 # number of overall misses -system.cpu.icache.overall_misses::total 15815747 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 208885866517 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 208885866517 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 208885866517 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 208885866517 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 208885866517 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 208885866517 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 359049369 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 359049369 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 359049369 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 359049369 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 359049369 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 359049369 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.044049 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.044049 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.044049 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.044049 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.044049 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.044049 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13207.461305 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13207.461305 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13207.461305 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13207.461305 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13207.461305 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13207.461305 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 13684 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 373257734 # Number of tag accesses +system.cpu.icache.tags.data_accesses 373257734 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 342405629 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 342405629 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 342405629 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 342405629 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 342405629 # number of overall hits +system.cpu.icache.overall_hits::total 342405629 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 15809279 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 15809279 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 15809279 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 15809279 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 15809279 # number of overall misses +system.cpu.icache.overall_misses::total 15809279 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 208403044384 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 208403044384 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 208403044384 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 208403044384 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 208403044384 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 208403044384 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 358214908 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 358214908 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 358214908 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 358214908 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 358214908 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 358214908 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.044134 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.044134 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.044134 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.044134 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.044134 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.044134 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13182.324405 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13182.324405 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13182.324405 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13182.324405 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13182.324405 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13182.324405 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 15030 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 1126 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 1210 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 12.152753 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 12.421488 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 744199 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 744199 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 744199 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 744199 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 744199 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 744199 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15071548 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15071548 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15071548 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15071548 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15071548 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15071548 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 766453 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 766453 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 766453 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 766453 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 766453 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 766453 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15042826 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15042826 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 15042826 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 15042826 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 15042826 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 15042826 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 21295 # number of ReadReq MSHR uncacheable system.cpu.icache.ReadReq_mshr_uncacheable::total 21295 # number of ReadReq MSHR uncacheable system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 21295 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 21295 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 179787086612 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 179787086612 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 179787086612 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 179787086612 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 179787086612 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 179787086612 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1585009250 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1585009250 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1585009250 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 1585009250 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.041976 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.041976 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.041976 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.041976 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.041976 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.041976 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11928.906481 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11928.906481 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11928.906481 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11928.906481 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11928.906481 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11928.906481 # average overall mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 74431.051890 # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 74431.051890 # average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 74431.051890 # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 74431.051890 # average overall mshr uncacheable latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 186915451392 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 186915451392 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 186915451392 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 186915451392 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 186915451392 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 186915451392 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1594412000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1594412000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1594412000 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 1594412000 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.041994 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.041994 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.041994 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.041994 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.041994 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.041994 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12425.554307 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12425.554307 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12425.554307 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12425.554307 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12425.554307 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12425.554307 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 74872.599202 # average ReadReq mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 74872.599202 # average ReadReq mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 74872.599202 # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 74872.599202 # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1159288 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65272.997993 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 29043191 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1221496 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 23.776739 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2756226000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 37273.751083 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 319.528316 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 474.614102 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 7535.726920 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 19669.377573 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.568752 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004876 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007242 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.114986 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.300131 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.995987 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 304 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 61904 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 304 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 579 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2674 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5116 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 53473 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004639 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.944580 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 272839925 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 272839925 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 805883 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 304376 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 14986718 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 6321707 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 22418684 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 7577660 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 7577660 # number of Writeback hits -system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data 730602 # number of WriteInvalidateReq hits -system.cpu.l2cache.WriteInvalidateReq_hits::total 730602 # number of WriteInvalidateReq hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 9499 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 9499 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1579833 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1579833 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 805883 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 304376 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 14986718 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 7901540 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 23998517 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 805883 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 304376 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 14986718 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 7901540 # number of overall hits -system.cpu.l2cache.overall_hits::total 23998517 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 3166 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3020 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 84629 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 253686 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 344501 # number of ReadReq misses -system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data 495562 # number of WriteInvalidateReq misses -system.cpu.l2cache.WriteInvalidateReq_misses::total 495562 # number of WriteInvalidateReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 34430 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 34430 # number of UpgradeReq misses +system.cpu.l2cache.tags.replacements 1148683 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65278.817014 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 46198537 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1210914 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 38.151790 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 15659706000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 37192.962627 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 301.460755 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 460.210435 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 7626.713626 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 19697.469572 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.567520 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004600 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007022 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.116374 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.300560 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996076 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 380 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 61851 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 379 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 530 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2690 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5173 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 53395 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.005798 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.943771 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 410382726 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 410382726 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 788948 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 299798 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1088746 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 7549082 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 7549082 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 9455 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 9455 # number of UpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 4 # number of SCUpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::total 4 # number of SCUpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1576072 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1576072 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14958434 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 14958434 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6296354 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 6296354 # number of ReadSharedReq hits +system.cpu.l2cache.InvalidateReq_hits::cpu.data 732370 # number of InvalidateReq hits +system.cpu.l2cache.InvalidateReq_hits::total 732370 # number of InvalidateReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 788948 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 299798 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 14958434 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 7872426 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 23919606 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 788948 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 299798 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 14958434 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 7872426 # number of overall hits +system.cpu.l2cache.overall_hits::total 23919606 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 3175 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2963 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 6138 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 34552 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 34552 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 413693 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 413693 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 3166 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 3020 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 84629 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 667379 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 758194 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 3166 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 3020 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 84629 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 667379 # number of overall misses -system.cpu.l2cache.overall_misses::total 758194 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 276962259 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 263518500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 7145038838 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22760355464 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 30445875061 # number of ReadReq miss cycles -system.cpu.l2cache.WriteInvalidateReq_miss_latency::cpu.data 4785347 # number of WriteInvalidateReq miss cycles -system.cpu.l2cache.WriteInvalidateReq_miss_latency::total 4785347 # number of WriteInvalidateReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 553374801 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 553374801 # number of UpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 159000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 36882340129 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 36882340129 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 276962259 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 263518500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 7145038838 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 59642695593 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 67328215190 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 276962259 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 263518500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 7145038838 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 59642695593 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 67328215190 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 809049 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 307396 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 15071347 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 6575393 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 22763185 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 7577660 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 7577660 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data 1226164 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.l2cache.WriteInvalidateReq_accesses::total 1226164 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 43929 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 43929 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 6 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 6 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1993526 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1993526 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 809049 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 307396 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 15071347 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 8568919 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 24756711 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 809049 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 307396 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 15071347 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 8568919 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 24756711 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.003913 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.009824 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.005615 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.038581 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.015134 # miss rate for ReadReq accesses -system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data 0.404156 # miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.404156 # miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.783765 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.783765 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.207518 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.207518 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.003913 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.009824 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005615 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.077884 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.030626 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.003913 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.009824 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005615 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.077884 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.030626 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 87480.182881 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 87257.781457 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 84427.782888 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 89718.610660 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 88376.739287 # average ReadReq miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::cpu.data 9.656404 # average WriteInvalidateReq miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::total 9.656404 # average WriteInvalidateReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 16072.460093 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 16072.460093 # average UpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 53000 # average SCUpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 53000 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89153.889790 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89153.889790 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 87480.182881 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 87257.781457 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84427.782888 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89368.553091 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 88800.775514 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 87480.182881 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 87257.781457 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84427.782888 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89368.553091 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 88800.775514 # average overall miss latency +system.cpu.l2cache.ReadExReq_misses::cpu.data 407912 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 407912 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 84184 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 84184 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 253746 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 253746 # number of ReadSharedReq misses +system.cpu.l2cache.InvalidateReq_misses::cpu.data 492598 # number of InvalidateReq misses +system.cpu.l2cache.InvalidateReq_misses::total 492598 # number of InvalidateReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 3175 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 2963 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 84184 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 661658 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 751980 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 3175 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 2963 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 84184 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 661658 # number of overall misses +system.cpu.l2cache.overall_misses::total 751980 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 276956000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 265379500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 542335500 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 544075000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 544075000 # number of UpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 160500 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::total 160500 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 36032836500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 36032836500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 7082572500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 7082572500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 22536354000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 22536354000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 51203919000 # number of InvalidateReq miss cycles +system.cpu.l2cache.InvalidateReq_miss_latency::total 51203919000 # number of InvalidateReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 276956000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 265379500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 7082572500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 58569190500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 66194098500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 276956000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 265379500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 7082572500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 58569190500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 66194098500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 792123 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 302761 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1094884 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 7549082 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 7549082 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 44007 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 44007 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 7 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 7 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1983984 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1983984 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15042618 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 15042618 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 6550100 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 6550100 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1224968 # number of InvalidateReq accesses(hits+misses) +system.cpu.l2cache.InvalidateReq_accesses::total 1224968 # number of InvalidateReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 792123 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 302761 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 15042618 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 8534084 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 24671586 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 792123 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 302761 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 15042618 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 8534084 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 24671586 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.004008 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.009787 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.005606 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.785148 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.785148 # miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.428571 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.428571 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.205602 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.205602 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005596 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005596 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.038739 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.038739 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.402131 # miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::total 0.402131 # miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.004008 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.009787 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005596 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.077531 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.030480 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.004008 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.009787 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005596 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.077531 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.030480 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 87230.236220 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 89564.461694 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 88357.038123 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15746.555916 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15746.555916 # average UpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 53500 # average SCUpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 53500 # average SCUpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88334.828345 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88334.828345 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84132.050033 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84132.050033 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88814.617767 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88814.617767 # average ReadSharedReq miss latency +system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 103946.664420 # average InvalidateReq miss latency +system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 103946.664420 # average InvalidateReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 87230.236220 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 89564.461694 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84132.050033 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88518.827703 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 88026.408282 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 87230.236220 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 89564.461694 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84132.050033 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88518.827703 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 88026.408282 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1350,182 +1368,196 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 977263 # number of writebacks -system.cpu.l2cache.writebacks::total 977263 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 21 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 21 # number of ReadReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 967181 # number of writebacks +system.cpu.l2cache.writebacks::total 967181 # number of writebacks +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 21 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 21 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 21 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 21 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 3166 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3020 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 84629 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 253665 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 344480 # number of ReadReq MSHR misses -system.cpu.l2cache.WriteInvalidateReq_mshr_misses::cpu.data 495562 # number of WriteInvalidateReq MSHR misses -system.cpu.l2cache.WriteInvalidateReq_mshr_misses::total 495562 # number of WriteInvalidateReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 34430 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 34430 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 3175 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2963 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 6138 # number of ReadReq MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1073 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 1073 # number of CleanEvict MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 34552 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 34552 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 413693 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 413693 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 3166 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3020 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 84629 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 667358 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 758173 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 3166 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3020 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 84629 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 667358 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 758173 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 407912 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 407912 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 84184 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 84184 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 253725 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 253725 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 492598 # number of InvalidateReq MSHR misses +system.cpu.l2cache.InvalidateReq_mshr_misses::total 492598 # number of InvalidateReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 3175 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2963 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 84184 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 661637 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 751959 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 3175 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2963 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 84184 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 661637 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 751959 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 21295 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33661 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.ReadReq_mshr_uncacheable::total 54956 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33682 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33682 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33678 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::total 54973 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33696 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33696 # number of WriteReq MSHR uncacheable system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 21295 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67343 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::total 88638 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 237171251 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 225518000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6085544162 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19591961036 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 26140194449 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data 16855177398 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total 16855177398 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 611252927 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 611252927 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 153001 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 153001 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31729551871 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31729551871 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 237171251 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 225518000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6085544162 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 51321512907 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 57869746320 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 237171251 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 225518000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6085544162 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 51321512907 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 57869746320 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1276231250 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5274563500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6550794750 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5186666500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5186666500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1276231250 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10461230000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11737461250 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.003913 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.009824 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.005615 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.038578 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015133 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.404156 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.404156 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.783765 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.783765 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.207518 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.207518 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.003913 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.009824 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005615 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.077881 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.030625 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.003913 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.009824 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005615 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.077881 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.030625 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 74911.955464 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 74674.834437 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 71908.496638 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77235.570678 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 75883.054021 # average ReadReq mshr miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 34012.247505 # average WriteInvalidateReq mshr miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 34012.247505 # average WriteInvalidateReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17753.497735 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17753.497735 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 51000.333333 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 51000.333333 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76698.304953 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76698.304953 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 74911.955464 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 74674.834437 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71908.496638 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76902.521446 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76327.891286 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 74911.955464 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 74674.834437 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71908.496638 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76902.521446 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76327.891286 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 59931.028410 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 156696.577642 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 119200.719667 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 153989.267264 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 153989.267264 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 59931.028410 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 155342.500334 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 132420.195063 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67374 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 88669 # number of overall MSHR uncacheable misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 245206000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 235749500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 480955500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 717374500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 717374500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 161500 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 161500 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31953716500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31953716500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 6240732500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 6240732500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19997854000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19997854000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 46277939000 # number of InvalidateReq MSHR miss cycles +system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 46277939000 # number of InvalidateReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 245206000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 235749500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6240732500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 51951570500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 58673258500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 245206000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 235749500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6240732500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 51951570500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 58673258500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1328224500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5407344500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6735569000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5315951000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5315951000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1328224500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10723295500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 12051520000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.004008 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.009787 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.005606 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.785148 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.785148 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.428571 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.428571 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.205602 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.205602 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005596 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005596 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.038736 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.038736 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.402131 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.402131 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.004008 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.009787 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005596 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.077529 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.030479 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.004008 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.009787 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005596 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.077529 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.030479 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 77230.236220 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 79564.461694 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 78357.038123 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20762.170063 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20762.170063 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 53833.333333 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 53833.333333 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78334.828345 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78334.828345 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74132.050033 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74132.050033 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78817.042073 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78817.042073 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 93946.664420 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 93946.664420 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 77230.236220 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 79564.461694 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74132.050033 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78519.747989 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78027.204276 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 77230.236220 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 79564.461694 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74132.050033 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78519.747989 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78027.204276 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 62372.599202 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160560.143120 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 122525.039565 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 157762.078585 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157762.078585 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 62372.599202 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 159160.737080 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 135915.821764 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 23293786 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 23285542 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 33682 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 33682 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 7577660 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1332936 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1226164 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 43932 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 6 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 43938 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1993526 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1993526 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 30185484 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27390990 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 736951 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1962535 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 60275960 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 964906864 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1112084525 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2459168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6472392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2085922949 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 583028 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 34275542 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.049559 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.217032 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadReq 1633565 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 23227278 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33696 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 8622904 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 17438576 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 44010 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 44017 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1983984 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1983984 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 15042826 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 6558947 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1331632 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1224968 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45167572 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29499463 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 732865 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1940611 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 77340511 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 963068272 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1029563294 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2422088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6336984 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2001390638 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1864369 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 52693428 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.056141 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.230194 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 32576878 95.04% 95.04% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 1698664 4.96% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 49735173 94.39% 94.39% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 2958255 5.61% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 34275542 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 25901169608 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 52693428 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 33222815494 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 909000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1182000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 22654600125 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 22592032956 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13659008538 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13487423434 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 430754363 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 430634727 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1154477924 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1148958035 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40283 # Transaction distribution -system.iobus.trans_dist::ReadResp 40283 # Transaction distribution -system.iobus.trans_dist::WriteReq 136558 # Transaction distribution -system.iobus.trans_dist::WriteResp 29894 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution +system.iobus.trans_dist::ReadReq 40295 # Transaction distribution +system.iobus.trans_dist::ReadResp 40295 # Transaction distribution +system.iobus.trans_dist::WriteReq 136571 # Transaction distribution +system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -1536,17 +1568,17 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29496 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122652 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230950 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230950 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230948 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230948 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353682 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353732 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1557,17 +1589,17 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17529 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155805 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334232 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334224 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334224 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492123 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7492144 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) @@ -1588,7 +1620,7 @@ system.iobus.reqLayer16.occupancy 12000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 21908000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) @@ -1596,211 +1628,213 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 607064814 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 568813596 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92761000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 148363066 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147708000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 174500 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115456 # number of replacements -system.iocache.tags.tagsinuse 10.424607 # Cycle average of tags in use +system.iocache.tags.replacements 115455 # number of replacements +system.iocache.tags.tagsinuse 10.423947 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115472 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115471 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13092103918000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.544640 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.879967 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.221540 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.429998 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651538 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13095311635000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.544418 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.879529 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.221526 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.429971 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651497 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039632 # Number of tag accesses -system.iocache.tags.data_accesses 1039632 # Number of data accesses +system.iocache.tags.tag_accesses 1039623 # Number of tag accesses +system.iocache.tags.data_accesses 1039623 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8811 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8848 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8810 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8847 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8811 # number of demand (read+write) misses -system.iocache.demand_misses::total 8851 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8810 # number of demand (read+write) misses +system.iocache.demand_misses::total 8850 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8811 # number of overall misses -system.iocache.overall_misses::total 8851 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5072000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1609809480 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1614881480 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::realview.ethernet 352500 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 352500 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19830913268 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 19830913268 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5424500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1609809480 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1615233980 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5424500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1609809480 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1615233980 # number of overall miss cycles +system.iocache.overall_misses::realview.ide 8810 # number of overall misses +system.iocache.overall_misses::total 8850 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5069000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1621911166 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1626980166 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12610487430 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12610487430 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5420000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1621911166 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1627331166 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5420000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1621911166 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1627331166 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8811 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8848 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8810 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8847 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8811 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8851 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8810 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8850 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8811 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8851 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8810 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8850 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 182704.514811 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 182513.729656 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117500 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 117500 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 185919.459874 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 185919.459874 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 182704.514811 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 182491.693594 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 182704.514811 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 182491.693594 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 110252 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137000 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 184098.883768 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 183901.906409 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118226.275313 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118226.275313 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135500 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 184098.883768 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 183879.227797 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135500 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 184098.883768 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 183879.227797 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 31681 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 16154 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3345 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.825059 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.471151 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8811 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8848 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8810 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8847 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8811 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8851 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8810 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8850 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8811 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8851 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3142000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1150531536 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1153673536 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 193500 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 193500 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14284309344 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14284309344 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3335500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1150531536 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1153867036 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3335500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1150531536 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1153867036 # number of overall MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8810 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8850 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1181411166 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1184630166 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7277287430 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7277287430 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3420000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1181411166 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1184831166 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3420000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1181411166 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1184831166 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 84918.918919 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 130578.996255 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 130388.057866 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 64500 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 64500 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133918.748069 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133918.748069 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 130578.996255 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 130365.725455 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 130578.996255 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 130365.725455 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87000 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 134098.883768 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 133901.906409 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68226.275313 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68226.275313 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 134098.883768 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 133879.227797 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 134098.883768 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 133879.227797 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 408284 # Transaction distribution -system.membus.trans_dist::ReadResp 408284 # Transaction distribution -system.membus.trans_dist::WriteReq 33682 # Transaction distribution -system.membus.trans_dist::WriteResp 33682 # Transaction distribution -system.membus.trans_dist::Writeback 1083893 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 602073 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 602073 # Transaction distribution -system.membus.trans_dist::UpgradeReq 35223 # Transaction distribution +system.membus.trans_dist::ReadReq 54973 # Transaction distribution +system.membus.trans_dist::ReadResp 407867 # Transaction distribution +system.membus.trans_dist::WriteReq 33696 # Transaction distribution +system.membus.trans_dist::WriteResp 33696 # Transaction distribution +system.membus.trans_dist::Writeback 1073811 # Transaction distribution +system.membus.trans_dist::CleanEvict 187846 # Transaction distribution +system.membus.trans_dist::UpgradeReq 35358 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 35226 # Transaction distribution -system.membus.trans_dist::ReadExReq 413056 # Transaction distribution -system.membus.trans_dist::ReadExResp 413056 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122652 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeResp 35361 # Transaction distribution +system.membus.trans_dist::ReadExReq 899707 # Transaction distribution +system.membus.trans_dist::ReadExResp 899707 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 352894 # Transaction distribution +system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution +system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 60 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6848 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3600651 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3730211 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335301 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 335301 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4065512 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155805 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3753956 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3883578 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341714 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 341714 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4225292 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 436 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13696 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 143052172 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 143222109 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14066304 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14066304 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 157288413 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3023 # Total snoops (count) -system.membus.snoop_fanout::samples 2576774 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 141818700 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 141988686 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7244096 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7244096 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 149232782 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 2955 # Total snoops (count) +system.membus.snoop_fanout::samples 2747442 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2576774 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2747442 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2576774 # Request fanout histogram -system.membus.reqLayer0.occupancy 104078000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2747442 # Request fanout histogram +system.membus.reqLayer0.occupancy 104159500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 33000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5439500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5443500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 9540063820 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 7279924206 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 4726359104 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 6776038462 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 151502434 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 228860056 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -1845,6 +1879,6 @@ system.realview.ethernet.coalescedTotal 0 # av system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16160 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 16150 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt index 347570290..b60b333d0 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt @@ -4,53 +4,53 @@ sim_seconds 51.111153 # Nu sim_ticks 51111152682000 # Number of ticks simulated final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1198732 # Simulator instruction rate (inst/s) -host_op_rate 1408707 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 62228718243 # Simulator tick rate (ticks/s) -host_mem_usage 717580 # Number of bytes of host memory used -host_seconds 821.34 # Real time elapsed on the host +host_inst_rate 1400836 # Simulator instruction rate (inst/s) +host_op_rate 1646212 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 72720385640 # Simulator tick rate (ticks/s) +host_mem_usage 722712 # Number of bytes of host memory used +host_seconds 702.85 # Real time elapsed on the host sim_insts 984570519 # Number of instructions simulated sim_ops 1157031967 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 412352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 376512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5562740 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 74833672 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 441792 # Number of bytes read from this memory -system.physmem.bytes_read::total 81627068 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5562740 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5562740 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 103042944 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.itb.walker 376704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5543028 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 110110088 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 442112 # Number of bytes read from this memory +system.physmem.bytes_read::total 116884284 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5543028 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5543028 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 103060480 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 103063524 # Number of bytes written to this memory +system.physmem.bytes_written::total 103081060 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 6443 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 5883 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 127325 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1169289 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6903 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1315843 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1610046 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 5886 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 127017 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1720483 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6908 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1866737 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1610320 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1612619 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1612893 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 8068 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 7367 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 108836 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1464136 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8644 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1597050 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 108836 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 108836 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2016056 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 7370 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 108450 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2154326 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8650 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2286865 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 108450 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 108450 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2016399 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 403 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2016459 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2016056 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2016802 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2016399 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 8068 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 7367 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 108836 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1464539 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8644 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3613509 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 7370 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 108450 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2154729 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8650 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4303666 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -294,8 +294,8 @@ system.cpu.dcache.WriteReq_hits::cpu.data 159522870 # n system.cpu.dcache.WriteReq_hits::total 159522870 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 424020 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 424020 # number of SoftPFReq hits -system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 337709 # number of WriteInvalidateReq hits -system.cpu.dcache.WriteInvalidateReq_hits::total 337709 # number of WriteInvalidateReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 337709 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 337709 # number of WriteLineReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 4310545 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 4310545 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 4562464 # number of StoreCondReq hits @@ -310,8 +310,8 @@ system.cpu.dcache.WriteReq_misses::cpu.data 2570257 # system.cpu.dcache.WriteReq_misses::total 2570257 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 1584397 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 1584397 # number of SoftPFReq misses -system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1245349 # number of WriteInvalidateReq misses -system.cpu.dcache.WriteInvalidateReq_misses::total 1245349 # number of WriteInvalidateReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1245349 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1245349 # number of WriteLineReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 253721 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 253721 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses @@ -326,8 +326,8 @@ system.cpu.dcache.WriteReq_accesses::cpu.data 162093127 system.cpu.dcache.WriteReq_accesses::total 162093127 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 2008417 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 2008417 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1583058 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::total 1583058 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::cpu.data 1583058 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 1583058 # number of WriteLineReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4564266 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 4564266 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 4562465 # number of StoreCondReq accesses(hits+misses) @@ -342,8 +342,8 @@ system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015857 system.cpu.dcache.WriteReq_miss_rate::total 0.015857 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788879 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.788879 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.786673 # miss rate for WriteInvalidateReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.786673 # miss rate for WriteInvalidateReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786673 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.786673 # miss rate for WriteLineReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055589 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055589 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses @@ -360,8 +360,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 8921315 # number of writebacks -system.cpu.dcache.writebacks::total 8921315 # number of writebacks +system.cpu.dcache.writebacks::writebacks 8921279 # number of writebacks +system.cpu.dcache.writebacks::total 8921279 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 14295641 # number of replacements system.cpu.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use @@ -412,96 +412,102 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1722692 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65341.862502 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 29983424 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1785989 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 16.788135 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 1722572 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65341.862554 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 46968482 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1785868 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 26.300086 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 37141.715219 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 310.196824 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 443.735041 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 6261.263092 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 21184.952326 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.566738 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 37098.596964 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 310.195568 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 443.733962 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 6290.976194 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 21198.359866 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.566080 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004733 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006771 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.095539 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.323257 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.095993 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.323461 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.997038 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1023 278 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 63019 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 63018 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1023::4 278 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 588 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2715 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4911 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54669 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2714 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4910 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54670 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004242 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.961594 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 290307620 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 290307620 # Number of data accesses +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.961578 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 426199223 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 426199223 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 506612 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 255623 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 14211921 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 7504232 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 22478388 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 8921315 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 8921315 # number of Writeback hits -system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data 694333 # number of WriteInvalidateReq hits -system.cpu.l2cache.WriteInvalidateReq_hits::total 694333 # number of WriteInvalidateReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 255620 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 762232 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 8921279 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 8921279 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 11223 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 11223 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1692610 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1692610 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1692559 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1692559 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14212229 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 14212229 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7504111 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 7504111 # number of ReadSharedReq hits +system.cpu.l2cache.InvalidateReq_hits::cpu.data 694322 # number of InvalidateReq hits +system.cpu.l2cache.InvalidateReq_hits::total 694322 # number of InvalidateReq hits system.cpu.l2cache.demand_hits::cpu.dtb.walker 506612 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 255623 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 14211921 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 9196842 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 24170998 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 255620 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 14212229 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 9196670 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 24171131 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.dtb.walker 506612 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 255623 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 14211921 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 9196842 # number of overall hits -system.cpu.l2cache.overall_hits::total 24170998 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 255620 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 14212229 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 9196670 # number of overall hits +system.cpu.l2cache.overall_hits::total 24171131 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6443 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5883 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 84237 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 343966 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 440529 # number of ReadReq misses -system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data 551016 # number of WriteInvalidateReq misses -system.cpu.l2cache.WriteInvalidateReq_misses::total 551016 # number of WriteInvalidateReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5886 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 12329 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 39917 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 39917 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 826507 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 826507 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 826558 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 826558 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 83929 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 83929 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 344087 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 344087 # number of ReadSharedReq misses +system.cpu.l2cache.InvalidateReq_misses::cpu.data 551027 # number of InvalidateReq misses +system.cpu.l2cache.InvalidateReq_misses::total 551027 # number of InvalidateReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 6443 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 5883 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 84237 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1170473 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1267036 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 5886 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 83929 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1170645 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1266903 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 6443 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 5883 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 84237 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1170473 # number of overall misses -system.cpu.l2cache.overall_misses::total 1267036 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 5886 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 83929 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1170645 # number of overall misses +system.cpu.l2cache.overall_misses::total 1266903 # number of overall misses system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 513055 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 261506 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 14296158 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7848198 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 22918917 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 8921315 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 8921315 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data 1245349 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.l2cache.WriteInvalidateReq_accesses::total 1245349 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 774561 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 8921279 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 8921279 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 51140 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 51140 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 2519117 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 2519117 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 14296158 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 14296158 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7848198 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 7848198 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1245349 # number of InvalidateReq accesses(hits+misses) +system.cpu.l2cache.InvalidateReq_accesses::total 1245349 # number of InvalidateReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.dtb.walker 513055 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 261506 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.inst 14296158 # number of demand (read+write) accesses @@ -513,28 +519,30 @@ system.cpu.l2cache.overall_accesses::cpu.inst 14296158 system.cpu.l2cache.overall_accesses::cpu.data 10367315 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 25438034 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.012558 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.022497 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.005892 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.043827 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.019221 # miss rate for ReadReq accesses -system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data 0.442459 # miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.442459 # miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.022508 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.015917 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.780544 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.780544 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.328094 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.328094 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.328114 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.328114 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005871 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005871 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043843 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043843 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.442468 # miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::total 0.442468 # miss rate for InvalidateReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.012558 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.022497 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005892 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.112900 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.049809 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.022508 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005871 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.112917 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.049803 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.012558 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.022497 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005892 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.112900 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.049809 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.022508 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005871 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.112917 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.049803 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -543,48 +551,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1503415 # number of writebacks -system.cpu.l2cache.writebacks::total 1503415 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1503689 # number of writebacks +system.cpu.l2cache.writebacks::total 1503689 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 23372119 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 1227763 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 23372119 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 8921315 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1245349 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1245349 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 8921279 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 16986503 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 51140 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 51141 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 2519117 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 2519117 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 28678566 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32383245 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 14296158 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7848198 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1245349 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1245349 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 42974207 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 35074071 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758224 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1543944 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 63363979 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 80350446 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 915126612 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1314364326 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1234659686 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3032896 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6175776 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2238699610 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2158994970 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 116338 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 36258168 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.034933 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.183610 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 53244635 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.023788 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.152389 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 34991563 96.51% 96.51% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 1266605 3.49% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 51978030 97.62% 97.62% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 1266605 2.38% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 36258168 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 53244635 # Request fanout histogram system.iobus.trans_dist::ReadReq 40246 # Transaction distribution system.iobus.trans_dist::ReadResp 40246 # Transaction distribution system.iobus.trans_dist::WriteReq 136515 # Transaction distribution -system.iobus.trans_dist::WriteResp 29851 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution +system.iobus.trans_dist::WriteResp 136515 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47598 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -648,8 +658,8 @@ system.iocache.ReadReq_misses::realview.ide 8817 # system.iocache.ReadReq_misses::total 8854 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses system.iocache.demand_misses::realview.ide 8817 # number of demand (read+write) misses system.iocache.demand_misses::total 8857 # number of demand (read+write) misses @@ -661,8 +671,8 @@ system.iocache.ReadReq_accesses::realview.ide 8817 system.iocache.ReadReq_accesses::total 8854 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses system.iocache.demand_accesses::realview.ide 8817 # number of demand (read+write) accesses system.iocache.demand_accesses::total 8857 # number of demand (read+write) accesses @@ -674,8 +684,8 @@ system.iocache.ReadReq_miss_rate::realview.ide 1 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses @@ -693,46 +703,48 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 526062 # Transaction distribution -system.membus.trans_dist::ReadResp 526062 # Transaction distribution +system.membus.trans_dist::ReadReq 76679 # Transaction distribution +system.membus.trans_dist::ReadResp 525878 # Transaction distribution system.membus.trans_dist::WriteReq 33606 # Transaction distribution system.membus.trans_dist::WriteResp 33606 # Transaction distribution -system.membus.trans_dist::Writeback 1610046 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 657675 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 657675 # Transaction distribution +system.membus.trans_dist::Writeback 1610320 # Transaction distribution +system.membus.trans_dist::CleanEvict 228940 # Transaction distribution system.membus.trans_dist::UpgradeReq 40484 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution system.membus.trans_dist::UpgradeResp 40485 # Transaction distribution -system.membus.trans_dist::ReadExReq 825948 # Transaction distribution -system.membus.trans_dist::ReadExResp 825948 # Transaction distribution +system.membus.trans_dist::ReadExReq 1377021 # Transaction distribution +system.membus.trans_dist::ReadExResp 1377021 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 449199 # Transaction distribution +system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution +system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5310733 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5439925 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337673 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 337673 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5777598 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5530871 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5660063 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346505 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 346505 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6006568 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 212730912 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 212899962 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14217536 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14217536 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 227117498 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 212740640 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 212909690 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7391040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7391040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 220300730 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3693822 # Request fanout histogram +system.membus.snoop_fanout::samples 3922914 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3693822 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3922914 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3693822 # Request fanout histogram +system.membus.snoop_fanout::total 3922914 # Request fanout histogram system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt index 6328b25f9..5f37e786a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt @@ -4,74 +4,74 @@ sim_seconds 47.216814 # Nu sim_ticks 47216814145000 # Number of ticks simulated final_tick 47216814145000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1152960 # Simulator instruction rate (inst/s) -host_op_rate 1356355 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 55808802200 # Simulator tick rate (ticks/s) -host_mem_usage 723640 # Number of bytes of host memory used -host_seconds 846.05 # Real time elapsed on the host +host_inst_rate 1322702 # Simulator instruction rate (inst/s) +host_op_rate 1556041 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64025133870 # Simulator tick rate (ticks/s) +host_mem_usage 730036 # Number of bytes of host memory used +host_seconds 737.47 # Real time elapsed on the host sim_insts 975457230 # Number of instructions simulated sim_ops 1147538415 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 152320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3903156 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 35201416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 222016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 221568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2639368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 38466864 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 412736 # Number of bytes read from this memory -system.physmem.bytes_read::total 81348148 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3903156 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2639368 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6542524 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 100538752 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 152256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 127104 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3638260 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 62923528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 221632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 219968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2412168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 46368688 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 419904 # Number of bytes read from this memory +system.physmem.bytes_read::total 116483508 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3638260 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2412168 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6050428 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 101038848 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 100559336 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2380 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2011 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 101394 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 550035 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 3469 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 3462 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 41347 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 601061 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6449 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1311608 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1570918 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 101059432 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2379 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1986 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 97255 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 983193 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 3463 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 3437 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 37797 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 724527 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6561 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1860598 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1578732 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1573492 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3226 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2726 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 82665 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 745527 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 4702 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 4693 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 55899 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 814686 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8741 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1722864 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 82665 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 55899 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 138563 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2129300 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1581306 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3225 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2692 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 77054 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1332651 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 4694 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 4659 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 51087 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 982038 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8893 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2466992 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 77054 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 51087 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 128141 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2139891 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 436 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2129736 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2129300 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3226 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2726 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 82665 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 745963 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 4702 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 4693 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 55899 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 814686 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8741 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3852600 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2140327 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2139891 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3225 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2692 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 77054 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1333087 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 4694 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 4659 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 51087 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 982038 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8893 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4607319 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory @@ -319,46 +319,46 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::2 5 system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.dcache.tags.tag_accesses 363162250 # Number of tag accesses system.cpu0.dcache.tags.data_accesses 363162250 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 86214909 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 86214909 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 80919814 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 80919814 # number of WriteReq hits +system.cpu0.dcache.ReadReq_hits::cpu0.data 86214911 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 86214911 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 80919787 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 80919787 # number of WriteReq hits system.cpu0.dcache.SoftPFReq_hits::cpu0.data 215654 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::total 215654 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 262024 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 262024 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2076465 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 2076465 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2036713 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 2036713 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 167134723 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 167134723 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 167350377 # number of overall hits -system.cpu0.dcache.overall_hits::total 167350377 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3309384 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3309384 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1475628 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1475628 # number of WriteReq misses +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 262007 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 262007 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2076466 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 2076466 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2036572 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 2036572 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 167134698 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 167134698 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 167350352 # number of overall hits +system.cpu0.dcache.overall_hits::total 167350352 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3309382 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3309382 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1475655 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1475655 # number of WriteReq misses system.cpu0.dcache.SoftPFReq_misses::cpu0.data 772139 # number of SoftPFReq misses system.cpu0.dcache.SoftPFReq_misses::total 772139 # number of SoftPFReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 831696 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 831696 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 119817 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 119817 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 158430 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 158430 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 4785012 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 4785012 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 5557151 # number of overall misses -system.cpu0.dcache.overall_misses::total 5557151 # number of overall misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 831713 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 831713 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 119816 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 119816 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 158571 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 158571 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 4785037 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 4785037 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 5557176 # number of overall misses +system.cpu0.dcache.overall_misses::total 5557176 # number of overall misses system.cpu0.dcache.ReadReq_accesses::cpu0.data 89524293 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 89524293 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 82395442 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 82395442 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 987793 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::total 987793 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1093720 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 1093720 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1093720 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 1093720 # number of WriteLineReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2196282 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 2196282 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2195143 # number of StoreCondReq accesses(hits+misses) @@ -373,16 +373,16 @@ system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017909 system.cpu0.dcache.WriteReq_miss_rate::total 0.017909 # miss rate for WriteReq accesses system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781681 # miss rate for SoftPFReq accesses system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781681 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.760429 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.760429 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.760444 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.760444 # miss rate for WriteLineReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054554 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054554 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.072173 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.072173 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.072237 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.072237 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027833 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.027833 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032139 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.032139 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032140 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.032140 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -391,14 +391,14 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 4471084 # number of writebacks -system.cpu0.dcache.writebacks::total 4471084 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 4472506 # number of writebacks +system.cpu0.dcache.writebacks::total 4472506 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 5539078 # number of replacements +system.cpu0.icache.tags.replacements 5539081 # number of replacements system.cpu0.icache.tags.tagsinuse 511.989005 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 492212894 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 5539590 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 88.853669 # Average number of references to valid blocks. +system.cpu0.icache.tags.total_refs 492212891 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 5539593 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 88.853620 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 5759896500 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989005 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy @@ -409,20 +409,20 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::1 256 system.cpu0.icache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 1001044573 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 1001044573 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 492212894 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 492212894 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 492212894 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 492212894 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 492212894 # number of overall hits -system.cpu0.icache.overall_hits::total 492212894 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 5539595 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 5539595 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 5539595 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 5539595 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 5539595 # number of overall misses -system.cpu0.icache.overall_misses::total 5539595 # number of overall misses +system.cpu0.icache.tags.tag_accesses 1001044576 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 1001044576 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 492212891 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 492212891 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 492212891 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 492212891 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 492212891 # number of overall hits +system.cpu0.icache.overall_hits::total 492212891 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 5539598 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 5539598 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 5539598 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 5539598 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 5539598 # number of overall misses +system.cpu0.icache.overall_misses::total 5539598 # number of overall misses system.cpu0.icache.ReadReq_accesses::cpu0.inst 497752489 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 497752489 # number of ReadReq accesses(hits+misses) system.cpu0.icache.demand_accesses::cpu0.inst 497752489 # number of demand (read+write) accesses @@ -450,131 +450,139 @@ system.cpu0.l2cache.prefetcher.pfBufferHit 0 # system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 2709460 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16213.748169 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 11555205 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2725459 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 4.239728 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.replacements 2713035 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16212.776574 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 18780735 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2729020 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 6.881861 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 5709.903296 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 52.786445 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 57.022731 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4531.359232 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 5862.676466 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.348505 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003222 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003480 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.276572 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.357829 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.989609 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 48 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15951 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 33 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 9 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 234 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1167 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4590 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5333 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4627 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.002930 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.973572 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 278732920 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 278732920 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 271204 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 143552 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 4971662 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 2944246 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 8330664 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 4471084 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 4471084 # number of Writeback hits -system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 223142 # number of WriteInvalidateReq hits -system.cpu0.l2cache.WriteInvalidateReq_hits::total 223142 # number of WriteInvalidateReq hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 3523 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 3523 # number of UpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 635192 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 635192 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 271204 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 143552 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 4971662 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 3579438 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 8965856 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 271204 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 143552 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 4971662 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 3579438 # number of overall hits -system.cpu0.l2cache.overall_hits::total 8965856 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11221 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8442 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 567933 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 1257094 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 1844690 # number of ReadReq misses -system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 608192 # number of WriteInvalidateReq misses -system.cpu0.l2cache.WriteInvalidateReq_misses::total 608192 # number of WriteInvalidateReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 128237 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 128237 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 158430 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 158430 # number of SCUpgradeReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 709038 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 709038 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11221 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8442 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 567933 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 1966132 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 2553728 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11221 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8442 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 567933 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 1966132 # number of overall misses -system.cpu0.l2cache.overall_misses::total 2553728 # number of overall misses -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 282425 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 151994 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 5539595 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 4201340 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 10175354 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 4471084 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 4471084 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 831334 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.l2cache.WriteInvalidateReq_accesses::total 831334 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 131760 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 131760 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 158430 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 158430 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1344230 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 1344230 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 282425 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 151994 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 5539595 # number of demand (read+write) accesses +system.cpu0.l2cache.tags.occ_blocks::writebacks 5698.548759 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 52.293580 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 53.073220 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4549.413482 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 5859.447533 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.347812 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003192 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003239 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.277674 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.357632 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.989549 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 51 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15934 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 32 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 7 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 233 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1169 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4652 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5280 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4600 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003113 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.972534 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 396071662 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 396071662 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 267140 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 140047 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 407187 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 4472506 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 4472506 # number of Writeback hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 3480 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 3480 # number of UpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 634900 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 634900 # number of ReadExReq hits +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4970860 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadCleanReq_hits::total 4970860 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2942102 # number of ReadSharedReq hits +system.cpu0.l2cache.ReadSharedReq_hits::total 2942102 # number of ReadSharedReq hits +system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 223126 # number of InvalidateReq hits +system.cpu0.l2cache.InvalidateReq_hits::total 223126 # number of InvalidateReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 267140 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 140047 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 4970860 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 3577002 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 8955049 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 267140 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 140047 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 4970860 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 3577002 # number of overall hits +system.cpu0.l2cache.overall_hits::total 8955049 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11279 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8435 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 19714 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 128321 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 128321 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 158571 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 158571 # number of SCUpgradeReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 709333 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 709333 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 568738 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 568738 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1259235 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 1259235 # number of ReadSharedReq misses +system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 608208 # number of InvalidateReq misses +system.cpu0.l2cache.InvalidateReq_misses::total 608208 # number of InvalidateReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11279 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8435 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 568738 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 1968568 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 2557020 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11279 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8435 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 568738 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 1968568 # number of overall misses +system.cpu0.l2cache.overall_misses::total 2557020 # number of overall misses +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 278419 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 148482 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 426901 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 4472506 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 4472506 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 131801 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 131801 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 158571 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 158571 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1344233 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 1344233 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5539598 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::total 5539598 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4201337 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::total 4201337 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 831334 # number of InvalidateReq accesses(hits+misses) +system.cpu0.l2cache.InvalidateReq_accesses::total 831334 # number of InvalidateReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 278419 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 148482 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 5539598 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::cpu0.data 5545570 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 11519584 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 282425 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 151994 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 5539595 # number of overall (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 11512069 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 278419 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 148482 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 5539598 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.data 5545570 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 11519584 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.039731 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.055542 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.102522 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.299213 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.181290 # miss rate for ReadReq accesses -system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.731586 # miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.731586 # miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.973262 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.973262 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.overall_accesses::total 11512069 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.040511 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.056808 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.046179 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.973597 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.973597 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.527468 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.527468 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.039731 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.055542 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.102522 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.354541 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.221686 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.039731 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.055542 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.102522 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.354541 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.221686 # miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.527686 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.527686 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.102668 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.102668 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.299722 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.299722 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.731605 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.731605 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.040511 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.056808 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.102668 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.354980 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.222116 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.040511 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.056808 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.102668 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.354980 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.222116 # miss rate for overall accesses system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -583,43 +591,46 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 1573136 # number of writebacks -system.cpu0.l2cache.writebacks::total 1573136 # number of writebacks +system.cpu0.l2cache.writebacks::writebacks 1573891 # number of writebacks +system.cpu0.l2cache.writebacks::total 1573891 # number of writebacks system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 10363944 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadReq 623009 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadResp 10363944 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteReq 32419 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteResp 32419 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 4471084 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 831334 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 831334 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 131760 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 158430 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 290190 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1344230 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1344230 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 11165440 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17935148 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.trans_dist::Writeback 4472506 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 7339348 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 131801 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 158571 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 290372 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1344233 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1344233 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5539598 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4201337 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 831334 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 831334 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16704527 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19737201 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 366654 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 728076 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 30195318 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 354706580 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 694464585 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 37536458 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 354706772 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 641350217 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1466616 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2912304 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1053550085 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 3357578 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 20506010 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 1.181419 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.385365 # Request fanout histogram +system.cpu0.toL2Bus.pkt_size::total 1000435909 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 3360861 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 27849165 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 1.133662 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.340289 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 16785836 81.86% 81.86% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 3720174 18.14% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 24126791 86.63% 86.63% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 3722374 13.37% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 20506010 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 27849165 # Request fanout histogram system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -836,44 +847,44 @@ system.cpu1.dcache.tags.tag_accesses 348813711 # Nu system.cpu1.dcache.tags.data_accesses 348813711 # Number of data accesses system.cpu1.dcache.ReadReq_hits::cpu1.data 83697564 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 83697564 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 76990302 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 76990302 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 76990238 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 76990238 # number of WriteReq hits system.cpu1.dcache.SoftPFReq_hits::cpu1.data 187854 # number of SoftPFReq hits system.cpu1.dcache.SoftPFReq_hits::total 187854 # number of SoftPFReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 63438 # number of WriteInvalidateReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::total 63438 # number of WriteInvalidateReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 63440 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 63440 # number of WriteLineReq hits system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2062256 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 2062256 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2048921 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 2048921 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 160687866 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 160687866 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 160875720 # number of overall hits -system.cpu1.dcache.overall_hits::total 160875720 # number of overall hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2048840 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 2048840 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 160687802 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 160687802 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 160875656 # number of overall hits +system.cpu1.dcache.overall_hits::total 160875656 # number of overall hits system.cpu1.dcache.ReadReq_misses::cpu1.data 3358222 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 3358222 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1453174 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1453174 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1453238 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1453238 # number of WriteReq misses system.cpu1.dcache.SoftPFReq_misses::cpu1.data 792351 # number of SoftPFReq misses system.cpu1.dcache.SoftPFReq_misses::total 792351 # number of SoftPFReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 427061 # number of WriteInvalidateReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::total 427061 # number of WriteInvalidateReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 427059 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 427059 # number of WriteLineReq misses system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 146820 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 146820 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 158828 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 158828 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 4811396 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 4811396 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 5603747 # number of overall misses -system.cpu1.dcache.overall_misses::total 5603747 # number of overall misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 158909 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 158909 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 4811460 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 4811460 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 5603811 # number of overall misses +system.cpu1.dcache.overall_misses::total 5603811 # number of overall misses system.cpu1.dcache.ReadReq_accesses::cpu1.data 87055786 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 87055786 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 78443476 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::total 78443476 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 980205 # number of SoftPFReq accesses(hits+misses) system.cpu1.dcache.SoftPFReq_accesses::total 980205 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 490499 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::total 490499 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 490499 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 490499 # number of WriteLineReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2209076 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 2209076 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2207749 # number of StoreCondReq accesses(hits+misses) @@ -884,20 +895,20 @@ system.cpu1.dcache.overall_accesses::cpu1.data 166479467 system.cpu1.dcache.overall_accesses::total 166479467 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038576 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_miss_rate::total 0.038576 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018525 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.018525 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018526 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.018526 # miss rate for WriteReq accesses system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.808352 # miss rate for SoftPFReq accesses system.cpu1.dcache.SoftPFReq_miss_rate::total 0.808352 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.870666 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.870666 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.870662 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.870662 # miss rate for WriteLineReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066462 # miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066462 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.071941 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.071941 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.071978 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.071978 # miss rate for StoreCondReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029072 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total 0.029072 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033660 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.033660 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033661 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.033661 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -906,8 +917,8 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 4032690 # number of writebacks -system.cpu1.dcache.writebacks::total 4032690 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 4032489 # number of writebacks +system.cpu1.dcache.writebacks::total 4032489 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 4741297 # number of replacements system.cpu1.icache.tags.tagsinuse 496.426080 # Cycle average of tags in use @@ -964,133 +975,141 @@ system.cpu1.l2cache.prefetcher.pfBufferHit 0 # system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 2276750 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13455.535871 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 10863007 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2292767 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 4.737946 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9713557209000 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 5167.508425 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 66.262953 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 86.675159 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2849.798557 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 5285.290777 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.315400 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004044 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005290 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.173938 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.322589 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.821261 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 96 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15921 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id +system.cpu1.l2cache.tags.replacements 2278625 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13455.366056 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 17413486 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 2294680 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 7.588634 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 9726491516500 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 5192.867159 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 66.806245 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 99.441300 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2834.629918 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 5261.621433 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.316947 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004078 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.006069 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.173012 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.321144 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.821250 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 98 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15957 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 49 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 20 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 23 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 34 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1571 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5986 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4452 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3831 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005859 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.971741 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 254014080 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 254014080 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 324472 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 140015 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 4218186 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 3058286 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 7740959 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 4032690 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 4032690 # number of Writeback hits -system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 161150 # number of WriteInvalidateReq hits -system.cpu1.l2cache.WriteInvalidateReq_hits::total 161150 # number of WriteInvalidateReq hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 3831 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 3831 # number of UpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 614491 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 614491 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 324472 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 140015 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 4218186 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3672777 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 8355450 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 324472 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 140015 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 4218186 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3672777 # number of overall hits -system.cpu1.l2cache.overall_hits::total 8355450 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12267 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9705 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 523623 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 1239107 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 1784702 # number of ReadReq misses -system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 265696 # number of WriteInvalidateReq misses -system.cpu1.l2cache.WriteInvalidateReq_misses::total 265696 # number of WriteInvalidateReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 133668 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 133668 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 158828 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 158828 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 701399 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 701399 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12267 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9705 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 523623 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 1940506 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 2486101 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12267 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9705 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 523623 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 1940506 # number of overall misses -system.cpu1.l2cache.overall_misses::total 2486101 # number of overall misses -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 336739 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 149720 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 4741809 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 4297393 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 9525661 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 4032690 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 4032690 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 426846 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.l2cache.WriteInvalidateReq_accesses::total 426846 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 137499 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 137499 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 158828 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 158828 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1614 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5923 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4524 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3815 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005981 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.973938 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 360485676 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 360485676 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 324846 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 140054 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 464900 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 4032489 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 4032489 # number of Writeback hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 3822 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 3822 # number of UpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 614016 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 614016 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4217303 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 4217303 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3057649 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 3057649 # number of ReadSharedReq hits +system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 161208 # number of InvalidateReq hits +system.cpu1.l2cache.InvalidateReq_hits::total 161208 # number of InvalidateReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 324846 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 140054 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 4217303 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 3671665 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 8353868 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 324846 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 140054 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 4217303 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 3671665 # number of overall hits +system.cpu1.l2cache.overall_hits::total 8353868 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12306 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9777 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 22083 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 133739 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 133739 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 158909 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 158909 # number of SCUpgradeReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 701874 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 701874 # number of ReadExReq misses +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 524506 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadCleanReq_misses::total 524506 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1239744 # number of ReadSharedReq misses +system.cpu1.l2cache.ReadSharedReq_misses::total 1239744 # number of ReadSharedReq misses +system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 265638 # number of InvalidateReq misses +system.cpu1.l2cache.InvalidateReq_misses::total 265638 # number of InvalidateReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12306 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9777 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 524506 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 1941618 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 2488207 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12306 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9777 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 524506 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 1941618 # number of overall misses +system.cpu1.l2cache.overall_misses::total 2488207 # number of overall misses +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 337152 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 149831 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 486983 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 4032489 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 4032489 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 137561 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 137561 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 158909 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 158909 # number of SCUpgradeReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1315890 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::total 1315890 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 336739 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 149720 # number of demand (read+write) accesses +system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4741809 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::total 4741809 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4297393 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::total 4297393 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 426846 # number of InvalidateReq accesses(hits+misses) +system.cpu1.l2cache.InvalidateReq_accesses::total 426846 # number of InvalidateReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 337152 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 149831 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.inst 4741809 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.data 5613283 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 10841551 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 336739 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 149720 # number of overall (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 10842075 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 337152 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 149831 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.inst 4741809 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.data 5613283 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 10841551 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.036429 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.064821 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.110427 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.288339 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.187357 # miss rate for ReadReq accesses -system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.622463 # miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.622463 # miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.972138 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.972138 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.overall_accesses::total 10842075 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.036500 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.065254 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.045347 # miss rate for ReadReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.972216 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.972216 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.533023 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.533023 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.036429 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.064821 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.110427 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.345699 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.229312 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.036429 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.064821 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.110427 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.345699 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.229312 # miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.533383 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.533383 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.110613 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.110613 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.288487 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.288487 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.622327 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.622327 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.036500 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.065254 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.110613 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.345897 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.229495 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.036500 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.065254 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.110613 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.345897 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.229495 # miss rate for overall accesses system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1099,48 +1118,50 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 1183004 # number of writebacks -system.cpu1.l2cache.writebacks::total 1183004 # number of writebacks +system.cpu1.l2cache.writebacks::writebacks 1184748 # number of writebacks +system.cpu1.l2cache.writebacks::total 1184748 # number of writebacks system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 9645413 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadReq 606211 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadResp 9645413 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteReq 6383 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteResp 6383 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 4032690 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 426846 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 426846 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 137499 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 158828 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 296327 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 4032489 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 6653857 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 137561 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 158909 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 296470 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExReq 1315890 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExResp 1315890 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 9483878 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16731086 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4741809 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4297393 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 426846 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 426846 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14225175 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18643731 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 364008 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 835436 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 27414408 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 34068350 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 303476296 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 644698812 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 617367804 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1456032 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3341744 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 952972884 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 3837128 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 19395843 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 1.220254 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.414418 # Request fanout histogram +system.cpu1.toL2Bus.pkt_size::total 925641876 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 3842126 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 26053175 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 1.164109 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.370374 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 15123827 77.97% 77.97% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 4272016 22.03% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 21777626 83.59% 83.59% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 4275549 16.41% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 19395843 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 26053175 # Request fanout histogram system.iobus.trans_dist::ReadReq 40295 # Transaction distribution system.iobus.trans_dist::ReadResp 40295 # Transaction distribution system.iobus.trans_dist::WriteReq 136634 # Transaction distribution -system.iobus.trans_dist::WriteResp 29906 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution +system.iobus.trans_dist::WriteResp 136634 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47636 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -1204,8 +1225,8 @@ system.iocache.ReadReq_misses::realview.ide 8876 # system.iocache.ReadReq_misses::total 8913 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses system.iocache.demand_misses::realview.ide 8876 # number of demand (read+write) misses system.iocache.demand_misses::total 8916 # number of demand (read+write) misses @@ -1217,8 +1238,8 @@ system.iocache.ReadReq_accesses::realview.ide 8876 system.iocache.ReadReq_accesses::total 8913 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses system.iocache.demand_accesses::realview.ide 8876 # number of demand (read+write) accesses system.iocache.demand_accesses::total 8916 # number of demand (read+write) accesses @@ -1230,8 +1251,8 @@ system.iocache.ReadReq_miss_rate::realview.ide 1 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses @@ -1249,205 +1270,192 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 106694 # number of writebacks system.iocache.writebacks::total 106694 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1759191 # number of replacements -system.l2c.tags.tagsinuse 62867.167491 # Cycle average of tags in use -system.l2c.tags.total_refs 3704436 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1817948 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.037702 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 483416500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 35264.935108 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 45.422401 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 57.110376 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3318.609191 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6952.273283 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 314.594733 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 425.085194 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2976.403767 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 13512.733438 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.538100 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000693 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000871 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.050638 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.106083 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004800 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.006486 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.045416 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.206188 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.959277 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 227 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 58530 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 225 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 564 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3441 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5617 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 48852 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.003464 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.893097 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 66366738 # Number of tag accesses -system.l2c.tags.data_accesses 66366738 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 6239 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4535 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 509640 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 744526 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5366 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 3579 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 482377 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 691195 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2447457 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 2756140 # number of Writeback hits -system.l2c.Writeback_hits::total 2756140 # number of Writeback hits -system.l2c.WriteInvalidateReq_hits::cpu0.data 121071 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::cpu1.data 98425 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::total 219496 # number of WriteInvalidateReq hits -system.l2c.UpgradeReq_hits::cpu0.data 13420 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 10778 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 24198 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 1497 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 1278 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 2775 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 202220 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 170877 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 373097 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 6239 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4535 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 509640 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 946746 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5366 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 3579 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 482377 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 862072 # number of demand (read+write) hits -system.l2c.demand_hits::total 2820554 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 6239 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4535 # number of overall hits -system.l2c.overall_hits::cpu0.inst 509640 # number of overall hits -system.l2c.overall_hits::cpu0.data 946746 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5366 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 3579 # number of overall hits -system.l2c.overall_hits::cpu1.inst 482377 # number of overall hits -system.l2c.overall_hits::cpu1.data 862072 # number of overall hits -system.l2c.overall_hits::total 2820554 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 2380 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2011 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 58293 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 183599 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 3469 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 3462 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 41246 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 189649 # number of ReadReq misses -system.l2c.ReadReq_misses::total 484109 # number of ReadReq misses -system.l2c.WriteInvalidateReq_misses::cpu0.data 479323 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::cpu1.data 160634 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::total 639957 # number of WriteInvalidateReq misses -system.l2c.UpgradeReq_misses::cpu0.data 58449 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 54093 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 112542 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 7788 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 7462 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 15250 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 377640 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 418302 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 795942 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 2380 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2011 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 58293 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 561239 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 3469 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 3462 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 41246 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 607951 # number of demand (read+write) misses -system.l2c.demand_misses::total 1280051 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 2380 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 2011 # number of overall misses -system.l2c.overall_misses::cpu0.inst 58293 # number of overall misses -system.l2c.overall_misses::cpu0.data 561239 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 3469 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 3462 # number of overall misses -system.l2c.overall_misses::cpu1.inst 41246 # number of overall misses -system.l2c.overall_misses::cpu1.data 607951 # number of overall misses -system.l2c.overall_misses::total 1280051 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.dtb.walker 8619 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 6546 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 567933 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 928125 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 8835 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 7041 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 523623 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 880844 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2931566 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 2756140 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 2756140 # number of Writeback accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu0.data 600394 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu1.data 259059 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::total 859453 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 71869 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 64871 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 136740 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 9285 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 8740 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 18025 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 579860 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 589179 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 1169039 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 8619 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 6546 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 567933 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1507985 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 8835 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 7041 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 523623 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 1470023 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 4100605 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 8619 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 6546 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 567933 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1507985 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 8835 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 7041 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 523623 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 1470023 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 4100605 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.276134 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.307211 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.102641 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.197817 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.392643 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.491692 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.078770 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.215304 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.165137 # miss rate for ReadReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.798347 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.620067 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::total 0.744610 # miss rate for WriteInvalidateReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.813271 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.833855 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.823036 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.838772 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.853776 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.846047 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.651261 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.709974 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.680852 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.276134 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.307211 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.102641 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.372178 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.392643 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.491692 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.078770 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.413566 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.312161 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.276134 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.307211 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.102641 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.372178 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.392643 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.491692 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.078770 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.413566 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.312161 # miss rate for overall accesses +system.l2c.tags.replacements 1751385 # number of replacements +system.l2c.tags.tagsinuse 62313.380560 # Cycle average of tags in use +system.l2c.tags.total_refs 6017106 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1809468 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 3.325345 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 34286.931814 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 47.043983 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 59.106418 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3327.548165 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 6997.138223 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 309.986034 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 428.835942 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3021.438473 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 13835.351509 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.523177 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000718 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000902 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.050774 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.106768 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004730 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.006544 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.046103 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.211111 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.950827 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 220 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 57863 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 218 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 545 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3434 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5577 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 48241 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.003357 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.882919 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 85814440 # Number of tag accesses +system.l2c.tags.data_accesses 85814440 # Number of data accesses +system.l2c.Writeback_hits::writebacks 2758639 # number of Writeback hits +system.l2c.Writeback_hits::total 2758639 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 13259 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 10916 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 24175 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 1481 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 1240 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 2721 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 318588 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 264415 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 583003 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6289 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4561 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 514584 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 748348 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5382 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 3638 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 486810 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 695012 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 2464624 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 6289 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4561 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 514584 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 1066936 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 5382 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 3638 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 486810 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 959427 # number of demand (read+write) hits +system.l2c.demand_hits::total 3047627 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 6289 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 4561 # number of overall hits +system.l2c.overall_hits::cpu0.inst 514584 # number of overall hits +system.l2c.overall_hits::cpu0.data 1066936 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 5382 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 3638 # number of overall hits +system.l2c.overall_hits::cpu1.inst 486810 # number of overall hits +system.l2c.overall_hits::cpu1.data 959427 # number of overall hits +system.l2c.overall_hits::total 3047627 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 58599 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 54084 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 112683 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 7811 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 7438 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 15249 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 816245 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 547345 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 1363590 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2379 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1986 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.inst 54154 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 180703 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3463 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.itb.walker 3437 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 37696 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 186059 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 469877 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.dtb.walker 2379 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 1986 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 54154 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 996948 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 3463 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 3437 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 37696 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 733404 # number of demand (read+write) misses +system.l2c.demand_misses::total 1833467 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 2379 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 1986 # number of overall misses +system.l2c.overall_misses::cpu0.inst 54154 # number of overall misses +system.l2c.overall_misses::cpu0.data 996948 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 3463 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 3437 # number of overall misses +system.l2c.overall_misses::cpu1.inst 37696 # number of overall misses +system.l2c.overall_misses::cpu1.data 733404 # number of overall misses +system.l2c.overall_misses::total 1833467 # number of overall misses +system.l2c.Writeback_accesses::writebacks 2758639 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 2758639 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 71858 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 65000 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 136858 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 9292 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 8678 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 17970 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 1134833 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 811760 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 1946593 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 8668 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6547 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.inst 568738 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 929051 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8845 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7075 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.inst 524506 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 881071 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 2934501 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 8668 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 6547 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 568738 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 2063884 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 8845 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 7075 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 524506 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 1692831 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 4881094 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 8668 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 6547 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 568738 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 2063884 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 8845 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 7075 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 524506 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 1692831 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 4881094 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.815483 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.832062 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.823357 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.840616 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.857110 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.848581 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.719264 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.674269 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.700501 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.274458 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.303345 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.095218 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.194503 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.391521 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.485795 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.071870 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.211174 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.160122 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.274458 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.303345 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.095218 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.483045 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.391521 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.485795 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.071870 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.433241 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.375626 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.274458 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.303345 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.095218 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.483045 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.391521 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.485795 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.071870 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.433241 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.375626 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1456,49 +1464,51 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 1464224 # number of writebacks -system.l2c.writebacks::total 1464224 # number of writebacks +system.l2c.writebacks::writebacks 1472038 # number of writebacks +system.l2c.writebacks::total 1472038 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 575153 # Transaction distribution -system.membus.trans_dist::ReadResp 575153 # Transaction distribution +system.membus.trans_dist::ReadReq 82131 # Transaction distribution +system.membus.trans_dist::ReadResp 560921 # Transaction distribution system.membus.trans_dist::WriteReq 38802 # Transaction distribution system.membus.trans_dist::WriteResp 38802 # Transaction distribution -system.membus.trans_dist::Writeback 1570918 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 742110 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 742110 # Transaction distribution -system.membus.trans_dist::UpgradeReq 328170 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 314483 # Transaction distribution -system.membus.trans_dist::UpgradeResp 149857 # Transaction distribution -system.membus.trans_dist::ReadExReq 965890 # Transaction distribution -system.membus.trans_dist::ReadExResp 778455 # Transaction distribution +system.membus.trans_dist::Writeback 1578732 # Transaction distribution +system.membus.trans_dist::CleanEvict 418758 # Transaction distribution +system.membus.trans_dist::UpgradeReq 328366 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 314759 # Transaction distribution +system.membus.trans_dist::UpgradeResp 149960 # Transaction distribution +system.membus.trans_dist::ReadExReq 1611572 # Transaction distribution +system.membus.trans_dist::ReadExResp 1341565 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 478790 # Transaction distribution +system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution +system.membus.trans_dist::InvalidateResp 106728 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122570 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27558 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6331701 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 6481921 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337982 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 337982 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6819903 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6659521 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 6809741 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346873 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 346873 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7156614 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155677 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55116 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 215372636 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 215583633 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14229440 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14229440 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 229813073 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 210336476 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 210547473 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7398848 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7398848 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 217946321 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 4535526 # Request fanout histogram +system.membus.snoop_fanout::samples 4958638 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 4535526 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 4958638 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 4535526 # Request fanout histogram +system.membus.snoop_fanout::total 4958638 # Request fanout histogram system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1541,35 +1551,35 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 3711525 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 3711525 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 82133 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 3716153 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 38802 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 38802 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 2756140 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 859453 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 859453 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 330303 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 317258 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 647561 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1356474 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1356474 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8686436 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7297334 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 15983770 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 301115229 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 249782916 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 550898145 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 117325 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 9485599 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.012192 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.109740 # Request fanout histogram +system.toL2Bus.trans_dist::Writeback 2758639 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2438361 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 330513 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 317480 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 647993 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2216600 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2216600 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 3634020 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9937165 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8498931 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 18436096 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 301383709 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 250013636 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 551397345 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 117333 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 11932192 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.009692 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.097969 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 9369955 98.78% 98.78% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 115644 1.22% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 11816548 99.03% 99.03% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 115644 0.97% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 9485599 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 11932192 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt index a28434f3e..6f3d32b32 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt @@ -4,53 +4,53 @@ sim_seconds 51.111153 # Nu sim_ticks 51111152682000 # Number of ticks simulated final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1196191 # Simulator instruction rate (inst/s) -host_op_rate 1405721 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 62096813616 # Simulator tick rate (ticks/s) -host_mem_usage 713636 # Number of bytes of host memory used -host_seconds 823.09 # Real time elapsed on the host +host_inst_rate 1372139 # Simulator instruction rate (inst/s) +host_op_rate 1612489 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 71230678319 # Simulator tick rate (ticks/s) +host_mem_usage 718244 # Number of bytes of host memory used +host_seconds 717.54 # Real time elapsed on the host sim_insts 984570519 # Number of instructions simulated sim_ops 1157031967 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 412352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 376512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5562740 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 74833672 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 441792 # Number of bytes read from this memory -system.physmem.bytes_read::total 81627068 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5562740 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5562740 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 103042944 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.itb.walker 376704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5543028 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 110110088 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 442112 # Number of bytes read from this memory +system.physmem.bytes_read::total 116884284 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5543028 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5543028 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 103060480 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 103063524 # Number of bytes written to this memory +system.physmem.bytes_written::total 103081060 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 6443 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 5883 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 127325 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1169289 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6903 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1315843 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1610046 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 5886 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 127017 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1720483 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6908 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1866737 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1610320 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1612619 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1612893 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 8068 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 7367 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 108836 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1464136 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8644 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1597050 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 108836 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 108836 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2016056 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 7370 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 108450 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2154326 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8650 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2286865 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 108450 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 108450 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2016399 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 403 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2016459 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2016056 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2016802 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2016399 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 8068 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 7367 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 108836 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1464539 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8644 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3613509 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 7370 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 108450 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2154729 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8650 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4303666 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -294,8 +294,8 @@ system.cpu.dcache.WriteReq_hits::cpu.data 159522870 # n system.cpu.dcache.WriteReq_hits::total 159522870 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 424020 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 424020 # number of SoftPFReq hits -system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 337709 # number of WriteInvalidateReq hits -system.cpu.dcache.WriteInvalidateReq_hits::total 337709 # number of WriteInvalidateReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 337709 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 337709 # number of WriteLineReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 4310545 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 4310545 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 4562464 # number of StoreCondReq hits @@ -310,8 +310,8 @@ system.cpu.dcache.WriteReq_misses::cpu.data 2570257 # system.cpu.dcache.WriteReq_misses::total 2570257 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 1584397 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 1584397 # number of SoftPFReq misses -system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1245349 # number of WriteInvalidateReq misses -system.cpu.dcache.WriteInvalidateReq_misses::total 1245349 # number of WriteInvalidateReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1245349 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1245349 # number of WriteLineReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 253721 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 253721 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses @@ -326,8 +326,8 @@ system.cpu.dcache.WriteReq_accesses::cpu.data 162093127 system.cpu.dcache.WriteReq_accesses::total 162093127 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 2008417 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 2008417 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1583058 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::total 1583058 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::cpu.data 1583058 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 1583058 # number of WriteLineReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4564266 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 4564266 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 4562465 # number of StoreCondReq accesses(hits+misses) @@ -342,8 +342,8 @@ system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015857 system.cpu.dcache.WriteReq_miss_rate::total 0.015857 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788879 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.788879 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.786673 # miss rate for WriteInvalidateReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.786673 # miss rate for WriteInvalidateReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786673 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.786673 # miss rate for WriteLineReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055589 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055589 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses @@ -360,8 +360,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 8921315 # number of writebacks -system.cpu.dcache.writebacks::total 8921315 # number of writebacks +system.cpu.dcache.writebacks::writebacks 8921279 # number of writebacks +system.cpu.dcache.writebacks::total 8921279 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 14295641 # number of replacements system.cpu.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use @@ -412,96 +412,102 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1722692 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65341.862502 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 29983424 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1785989 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 16.788135 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 1722572 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65341.862554 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 46968482 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1785868 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 26.300086 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 37141.715219 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 310.196824 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 443.735041 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 6261.263092 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 21184.952326 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.566738 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 37098.596964 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 310.195568 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 443.733962 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 6290.976194 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 21198.359866 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.566080 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004733 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006771 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.095539 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.323257 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.095993 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.323461 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.997038 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1023 278 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 63019 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 63018 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1023::4 278 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 588 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2715 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4911 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54669 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2714 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4910 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54670 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004242 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.961594 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 290307620 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 290307620 # Number of data accesses +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.961578 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 426199223 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 426199223 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 506612 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 255623 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 14211921 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 7504232 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 22478388 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 8921315 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 8921315 # number of Writeback hits -system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data 694333 # number of WriteInvalidateReq hits -system.cpu.l2cache.WriteInvalidateReq_hits::total 694333 # number of WriteInvalidateReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 255620 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 762232 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 8921279 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 8921279 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 11223 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 11223 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1692610 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1692610 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1692559 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1692559 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14212229 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 14212229 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7504111 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 7504111 # number of ReadSharedReq hits +system.cpu.l2cache.InvalidateReq_hits::cpu.data 694322 # number of InvalidateReq hits +system.cpu.l2cache.InvalidateReq_hits::total 694322 # number of InvalidateReq hits system.cpu.l2cache.demand_hits::cpu.dtb.walker 506612 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 255623 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 14211921 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 9196842 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 24170998 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 255620 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 14212229 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 9196670 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 24171131 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.dtb.walker 506612 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 255623 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 14211921 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 9196842 # number of overall hits -system.cpu.l2cache.overall_hits::total 24170998 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 255620 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 14212229 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 9196670 # number of overall hits +system.cpu.l2cache.overall_hits::total 24171131 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6443 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5883 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 84237 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 343966 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 440529 # number of ReadReq misses -system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data 551016 # number of WriteInvalidateReq misses -system.cpu.l2cache.WriteInvalidateReq_misses::total 551016 # number of WriteInvalidateReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5886 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 12329 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 39917 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 39917 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 826507 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 826507 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 826558 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 826558 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 83929 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 83929 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 344087 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 344087 # number of ReadSharedReq misses +system.cpu.l2cache.InvalidateReq_misses::cpu.data 551027 # number of InvalidateReq misses +system.cpu.l2cache.InvalidateReq_misses::total 551027 # number of InvalidateReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 6443 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 5883 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 84237 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1170473 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1267036 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 5886 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 83929 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1170645 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1266903 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 6443 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 5883 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 84237 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1170473 # number of overall misses -system.cpu.l2cache.overall_misses::total 1267036 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 5886 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 83929 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1170645 # number of overall misses +system.cpu.l2cache.overall_misses::total 1266903 # number of overall misses system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 513055 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 261506 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 14296158 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7848198 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 22918917 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 8921315 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 8921315 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data 1245349 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.l2cache.WriteInvalidateReq_accesses::total 1245349 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 774561 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 8921279 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 8921279 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 51140 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 51140 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 2519117 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 2519117 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 14296158 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 14296158 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7848198 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 7848198 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1245349 # number of InvalidateReq accesses(hits+misses) +system.cpu.l2cache.InvalidateReq_accesses::total 1245349 # number of InvalidateReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.dtb.walker 513055 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 261506 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.inst 14296158 # number of demand (read+write) accesses @@ -513,28 +519,30 @@ system.cpu.l2cache.overall_accesses::cpu.inst 14296158 system.cpu.l2cache.overall_accesses::cpu.data 10367315 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 25438034 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.012558 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.022497 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.005892 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.043827 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.019221 # miss rate for ReadReq accesses -system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data 0.442459 # miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.442459 # miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.022508 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.015917 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.780544 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.780544 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.328094 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.328094 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.328114 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.328114 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005871 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005871 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043843 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043843 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.442468 # miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::total 0.442468 # miss rate for InvalidateReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.012558 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.022497 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005892 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.112900 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.049809 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.022508 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005871 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.112917 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.049803 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.012558 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.022497 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005892 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.112900 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.049809 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.022508 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005871 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.112917 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.049803 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -543,48 +551,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1503415 # number of writebacks -system.cpu.l2cache.writebacks::total 1503415 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1503689 # number of writebacks +system.cpu.l2cache.writebacks::total 1503689 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 23372119 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 1227763 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 23372119 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 8921315 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1245349 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1245349 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 8921279 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 16986503 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 51140 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 51141 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 2519117 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 2519117 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 28678566 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32383245 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 14296158 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7848198 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1245349 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1245349 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 42974207 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 35074071 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758224 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1543944 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 63363979 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 80350446 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 915126612 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1314364326 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1234659686 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3032896 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6175776 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2238699610 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2158994970 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 116338 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 36258168 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.034933 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.183610 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 53244635 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.023788 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.152389 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 34991563 96.51% 96.51% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 1266605 3.49% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 51978030 97.62% 97.62% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 1266605 2.38% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 36258168 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 53244635 # Request fanout histogram system.iobus.trans_dist::ReadReq 40246 # Transaction distribution system.iobus.trans_dist::ReadResp 40246 # Transaction distribution system.iobus.trans_dist::WriteReq 136515 # Transaction distribution -system.iobus.trans_dist::WriteResp 29851 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution +system.iobus.trans_dist::WriteResp 136515 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47598 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -648,8 +658,8 @@ system.iocache.ReadReq_misses::realview.ide 8817 # system.iocache.ReadReq_misses::total 8854 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses system.iocache.demand_misses::realview.ide 8817 # number of demand (read+write) misses system.iocache.demand_misses::total 8857 # number of demand (read+write) misses @@ -661,8 +671,8 @@ system.iocache.ReadReq_accesses::realview.ide 8817 system.iocache.ReadReq_accesses::total 8854 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses system.iocache.demand_accesses::realview.ide 8817 # number of demand (read+write) accesses system.iocache.demand_accesses::total 8857 # number of demand (read+write) accesses @@ -674,8 +684,8 @@ system.iocache.ReadReq_miss_rate::realview.ide 1 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses @@ -693,46 +703,48 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 526062 # Transaction distribution -system.membus.trans_dist::ReadResp 526062 # Transaction distribution +system.membus.trans_dist::ReadReq 76679 # Transaction distribution +system.membus.trans_dist::ReadResp 525878 # Transaction distribution system.membus.trans_dist::WriteReq 33606 # Transaction distribution system.membus.trans_dist::WriteResp 33606 # Transaction distribution -system.membus.trans_dist::Writeback 1610046 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 657675 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 657675 # Transaction distribution +system.membus.trans_dist::Writeback 1610320 # Transaction distribution +system.membus.trans_dist::CleanEvict 228940 # Transaction distribution system.membus.trans_dist::UpgradeReq 40484 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution system.membus.trans_dist::UpgradeResp 40485 # Transaction distribution -system.membus.trans_dist::ReadExReq 825948 # Transaction distribution -system.membus.trans_dist::ReadExResp 825948 # Transaction distribution +system.membus.trans_dist::ReadExReq 1377021 # Transaction distribution +system.membus.trans_dist::ReadExResp 1377021 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 449199 # Transaction distribution +system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution +system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5310733 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5439925 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337673 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 337673 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5777598 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5530871 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5660063 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346505 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 346505 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6006568 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 212730912 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 212899962 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14217536 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14217536 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 227117498 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 212740640 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 212909690 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7391040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7391040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 220300730 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3693822 # Request fanout histogram +system.membus.snoop_fanout::samples 3922914 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3693822 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3922914 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3693822 # Request fanout histogram +system.membus.snoop_fanout::total 3922914 # Request fanout histogram system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt index 5570b9a7c..0006790d0 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt @@ -1,168 +1,168 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.526955 # Number of seconds simulated -sim_ticks 47526954967000 # Number of ticks simulated -final_tick 47526954967000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.496387 # Number of seconds simulated +sim_ticks 47496386980500 # Number of ticks simulated +final_tick 47496386980500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 679404 # Simulator instruction rate (inst/s) -host_op_rate 799114 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36258651928 # Simulator tick rate (ticks/s) -host_mem_usage 756696 # Number of bytes of host memory used -host_seconds 1310.78 # Real time elapsed on the host -sim_insts 890546366 # Number of instructions simulated -sim_ops 1047459319 # Number of ops (including micro ops) simulated +host_inst_rate 708538 # Simulator instruction rate (inst/s) +host_op_rate 833484 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38555693115 # Simulator tick rate (ticks/s) +host_mem_usage 757988 # Number of bytes of host memory used +host_seconds 1231.89 # Real time elapsed on the host +sim_insts 872840522 # Number of instructions simulated +sim_ops 1026761155 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 120896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 123520 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3402100 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 13323656 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 13846976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 139776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 143808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3041464 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 11124432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 15361728 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 416704 # Number of bytes read from this memory -system.physmem.bytes_read::total 61045060 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3402100 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3041464 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6443564 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 78583104 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 77248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 78464 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 2962612 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 38823816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 12701504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 109824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 113728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2837560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 15245328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 12552128 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 438080 # Number of bytes read from this memory +system.physmem.bytes_read::total 85940292 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 2962612 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2837560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5800172 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 72817088 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 78603688 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1889 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1930 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 93565 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 208195 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 216359 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2184 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2247 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 47611 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 173832 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 240027 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6511 # Number of read requests responded to by this memory -system.physmem.num_reads::total 994350 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1227861 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 72837672 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1207 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1226 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 86698 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 606635 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 198461 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1716 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1777 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 44425 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 238221 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 196127 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6845 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1383338 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1137767 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1230435 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2544 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 71583 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 280339 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 291350 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 2941 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 3026 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 63995 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 234066 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 323221 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8768 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1284430 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 71583 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 63995 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 135577 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1653443 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1140341 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 1626 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 1652 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 62376 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 817406 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 267420 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2312 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2394 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 59743 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 320979 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 264275 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9223 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1809407 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 62376 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 59743 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 122118 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1533108 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1653876 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1653443 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2544 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2599 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 71583 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 280772 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 291350 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 2941 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 3026 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 63995 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 234066 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 323221 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8768 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2938306 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 994350 # Number of read requests accepted -system.physmem.writeReqs 1902822 # Number of write requests accepted -system.physmem.readBursts 994350 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1902822 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 63617152 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 21248 # Total number of bytes read from write queue -system.physmem.bytesWritten 118663680 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 61045060 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 121636456 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 332 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 48679 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 115330 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 57482 # Per bank write bursts -system.physmem.perBankRdBursts::1 61474 # Per bank write bursts -system.physmem.perBankRdBursts::2 58055 # Per bank write bursts -system.physmem.perBankRdBursts::3 62815 # Per bank write bursts -system.physmem.perBankRdBursts::4 61744 # Per bank write bursts -system.physmem.perBankRdBursts::5 72443 # Per bank write bursts -system.physmem.perBankRdBursts::6 62137 # Per bank write bursts -system.physmem.perBankRdBursts::7 62898 # Per bank write bursts -system.physmem.perBankRdBursts::8 53757 # Per bank write bursts -system.physmem.perBankRdBursts::9 98485 # Per bank write bursts -system.physmem.perBankRdBursts::10 53699 # Per bank write bursts -system.physmem.perBankRdBursts::11 61424 # Per bank write bursts -system.physmem.perBankRdBursts::12 50178 # Per bank write bursts -system.physmem.perBankRdBursts::13 60766 # Per bank write bursts -system.physmem.perBankRdBursts::14 57507 # Per bank write bursts -system.physmem.perBankRdBursts::15 59154 # Per bank write bursts -system.physmem.perBankWrBursts::0 114707 # Per bank write bursts -system.physmem.perBankWrBursts::1 119877 # Per bank write bursts -system.physmem.perBankWrBursts::2 118693 # Per bank write bursts -system.physmem.perBankWrBursts::3 118700 # Per bank write bursts -system.physmem.perBankWrBursts::4 118108 # Per bank write bursts -system.physmem.perBankWrBursts::5 125436 # Per bank write bursts -system.physmem.perBankWrBursts::6 113884 # Per bank write bursts -system.physmem.perBankWrBursts::7 116296 # Per bank write bursts -system.physmem.perBankWrBursts::8 112515 # Per bank write bursts -system.physmem.perBankWrBursts::9 116242 # Per bank write bursts -system.physmem.perBankWrBursts::10 112992 # Per bank write bursts -system.physmem.perBankWrBursts::11 118745 # Per bank write bursts -system.physmem.perBankWrBursts::12 107808 # Per bank write bursts -system.physmem.perBankWrBursts::13 111387 # Per bank write bursts -system.physmem.perBankWrBursts::14 114155 # Per bank write bursts -system.physmem.perBankWrBursts::15 114575 # Per bank write bursts +system.physmem.bw_write::total 1533541 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1533108 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 1626 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 1652 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 62376 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 817839 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 267420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2312 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2394 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 59743 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 320979 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 264275 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9223 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3342948 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1383338 # Number of read requests accepted +system.physmem.writeReqs 1140341 # Number of write requests accepted +system.physmem.readBursts 1383338 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1140341 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 88503808 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 29824 # Total number of bytes read from write queue +system.physmem.bytesWritten 72836864 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 85940292 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 72837672 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 466 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 218501 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 80378 # Per bank write bursts +system.physmem.perBankRdBursts::1 85683 # Per bank write bursts +system.physmem.perBankRdBursts::2 84533 # Per bank write bursts +system.physmem.perBankRdBursts::3 91641 # Per bank write bursts +system.physmem.perBankRdBursts::4 87506 # Per bank write bursts +system.physmem.perBankRdBursts::5 92565 # Per bank write bursts +system.physmem.perBankRdBursts::6 85373 # Per bank write bursts +system.physmem.perBankRdBursts::7 87361 # Per bank write bursts +system.physmem.perBankRdBursts::8 80689 # Per bank write bursts +system.physmem.perBankRdBursts::9 125890 # Per bank write bursts +system.physmem.perBankRdBursts::10 79879 # Per bank write bursts +system.physmem.perBankRdBursts::11 87722 # Per bank write bursts +system.physmem.perBankRdBursts::12 73371 # Per bank write bursts +system.physmem.perBankRdBursts::13 83748 # Per bank write bursts +system.physmem.perBankRdBursts::14 77275 # Per bank write bursts +system.physmem.perBankRdBursts::15 79258 # Per bank write bursts +system.physmem.perBankWrBursts::0 66779 # Per bank write bursts +system.physmem.perBankWrBursts::1 71701 # Per bank write bursts +system.physmem.perBankWrBursts::2 72134 # Per bank write bursts +system.physmem.perBankWrBursts::3 76164 # Per bank write bursts +system.physmem.perBankWrBursts::4 73824 # Per bank write bursts +system.physmem.perBankWrBursts::5 77776 # Per bank write bursts +system.physmem.perBankWrBursts::6 71735 # Per bank write bursts +system.physmem.perBankWrBursts::7 72120 # Per bank write bursts +system.physmem.perBankWrBursts::8 69346 # Per bank write bursts +system.physmem.perBankWrBursts::9 71851 # Per bank write bursts +system.physmem.perBankWrBursts::10 68226 # Per bank write bursts +system.physmem.perBankWrBursts::11 73306 # Per bank write bursts +system.physmem.perBankWrBursts::12 64374 # Per bank write bursts +system.physmem.perBankWrBursts::13 72179 # Per bank write bursts +system.physmem.perBankWrBursts::14 67114 # Per bank write bursts +system.physmem.perBankWrBursts::15 69447 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 406 # Number of times write queue was full causing retry -system.physmem.totGap 47526951912500 # Total gap between requests +system.physmem.numWrRetry 52 # Number of times write queue was full causing retry +system.physmem.totGap 47496383920000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43195 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 951125 # Read request sizes (log2) +system.physmem.readPktSize::6 1340113 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1900248 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 698116 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 83658 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 42191 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 36638 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 31495 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 28119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 24839 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 21358 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 17624 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4596 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1385 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1018 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 839 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 651 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 464 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 363 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 281 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 218 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 93 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 61 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1137767 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1131623 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 75605 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 35452 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 30271 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 26331 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 23289 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 20581 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 17115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 14732 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 3112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1389 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 848 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 676 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 510 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 378 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 327 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 250 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 202 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 68 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -188,169 +188,167 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 55966 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 69244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 86453 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 95710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 99723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 98450 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 98652 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 98653 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 101180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 101256 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 102685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 108850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 104999 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 104785 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 118151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 108223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 102687 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 99179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 6890 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 5415 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 5566 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 6838 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 6775 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 6308 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 6158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 7224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 5430 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 4899 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 4456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 5091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 4051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 3523 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 3763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2982 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 2416 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1572 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 928 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 818 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 686 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 630 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 505 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 480 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 450 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 474 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 421 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 1611 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1054851 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 172.802142 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 106.115345 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 242.100455 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 681651 64.62% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 201380 19.09% 83.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 48895 4.64% 88.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 24340 2.31% 90.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 17755 1.68% 92.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11649 1.10% 93.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8558 0.81% 94.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 7940 0.75% 95.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 52683 4.99% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1054851 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 92018 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 10.802300 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 106.341779 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 92015 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 92018 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 92018 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.149536 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.827281 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 17.009129 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 90131 97.95% 97.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 760 0.83% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 32 0.03% 98.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 41 0.04% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 142 0.15% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 182 0.20% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 347 0.38% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 116 0.13% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 35 0.04% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 12 0.01% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 63 0.07% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 31 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 15 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 6 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 1 0.00% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 4 0.00% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 5 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 6 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 11 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 16 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 8 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 24 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 5 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 4 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::400-415 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::416-431 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::432-447 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::448-463 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::464-479 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::560-575 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::576-591 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::736-751 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::848-863 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 92018 # Writes before turning the bus around for reads -system.physmem.totQLat 36585898476 # Total ticks spent queuing -system.physmem.totMemAccLat 55223735976 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4970090000 # Total ticks spent in databus transfers -system.physmem.avgQLat 36806.07 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 16550 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 19449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 48905 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 57076 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 61582 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 64173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 65524 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 69411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 70341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 73639 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 73241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 74463 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 72846 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 73821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 77361 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 71631 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 68870 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 66897 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1594 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 987 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 658 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 577 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 491 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 435 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 321 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 158 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 866706 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 186.153496 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 114.409994 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 244.608227 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 521785 60.20% 60.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 170596 19.68% 79.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 55940 6.45% 86.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 28866 3.33% 89.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 19331 2.23% 91.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 11894 1.37% 93.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 9595 1.11% 94.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 9879 1.14% 95.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 38820 4.48% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 866706 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 64746 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.358308 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 318.389928 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 64744 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::20480-24575 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::77824-81919 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 64746 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 64746 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.577549 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.073829 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 6.807966 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 61438 94.89% 94.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 935 1.44% 96.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 457 0.71% 97.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 214 0.33% 97.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 283 0.44% 97.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 509 0.79% 98.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 100 0.15% 98.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 37 0.06% 98.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 36 0.06% 98.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 29 0.04% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 34 0.05% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 27 0.04% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 442 0.68% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 39 0.06% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 47 0.07% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 53 0.08% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 11 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 4 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 3 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 16 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 6 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 5 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 64746 # Writes before turning the bus around for reads +system.physmem.totQLat 34994473123 # Total ticks spent queuing +system.physmem.totMemAccLat 60923323123 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6914360000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25305.65 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 55556.07 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.34 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.50 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.28 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.56 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 44055.65 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.86 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.53 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.81 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.53 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.94 # Average write queue length when enqueuing -system.physmem.readRowHits 744165 # Number of row buffer hits during reads -system.physmem.writeRowHits 1049121 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.86 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 56.58 # Row buffer hit rate for writes -system.physmem.avgGap 16404601.42 # Average gap between requests -system.physmem.pageHitRate 62.96 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4105851120 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2240295750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3892535400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 6128142480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3104229389040 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1214897373855 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27450471155250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31785964742895 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.798736 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45665609957576 # Time in different power states -system.physmem_0.memoryStateTime::REF 1587029340000 # Time in different power states +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.88 # Average write queue length when enqueuing +system.physmem.readRowHits 1113162 # Number of row buffer hits during reads +system.physmem.writeRowHits 541079 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.50 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 47.54 # Row buffer hit rate for writes +system.physmem.avgGap 18820295.26 # Average gap between requests +system.physmem.pageHitRate 65.62 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3392073720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1850833875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 5421273000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3772869840 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3102232782480 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1205451752805 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27440415505500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31762537091220 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.735925 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45648791331206 # Time in different power states +system.physmem_0.memoryStateTime::REF 1586008580000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 274315218424 # Time in different power states +system.physmem_0.memoryStateTime::ACT 261586624794 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3868822440 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2110964625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3860766000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5886555120 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3104229389040 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1202076105075 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27461717882250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31783750484550 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.752146 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45684364167822 # Time in different power states -system.physmem_1.memoryStateTime::REF 1587029340000 # Time in different power states +system.physmem_1.actEnergy 3160223640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1724328375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 5365089600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3601862640 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3102232782480 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1192319355510 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27451935144000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31760338786245 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.689642 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45667995849266 # Time in different power states +system.physmem_1.memoryStateTime::REF 1586008580000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 255557515928 # Time in different power states +system.physmem_1.memoryStateTime::ACT 242377776984 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -414,69 +412,67 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 101631 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 101631 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9048 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 76119 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 11 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 101620 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 0.113167 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 36.075158 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-1023 101619 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::11264-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 101620 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 85178 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 19101.889572 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 17045.635811 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 15664.933997 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 84047 98.67% 98.67% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 953 1.12% 99.79% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 46 0.05% 99.85% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 63 0.07% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 53 0.06% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 104839 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 104839 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10495 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 79742 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 104830 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 0.171707 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 55.594229 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-2047 104829 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::16384-18431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 104830 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 90246 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 19548.112936 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 18016.919113 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 12415.253011 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 89555 99.23% 99.23% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 591 0.65% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 29 0.03% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 30 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 26 0.03% 99.98% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::327680-393215 8 0.01% 99.99% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 85178 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 6479942056 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.123756 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 -801929896 -12.38% -12.38% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 7281871952 112.38% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 6479942056 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 76120 89.38% 89.38% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 9048 10.62% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 85168 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 101631 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 90246 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples -2134286464 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.271898 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 580308492 -27.19% -27.19% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 -2714594956 127.19% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total -2134286464 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 79742 88.37% 88.37% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 10495 11.63% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 90237 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 104839 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 101631 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 85168 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 104839 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 90237 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 85168 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 186799 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 90237 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 195076 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 83767358 # DTB read hits -system.cpu0.dtb.read_misses 74871 # DTB read misses -system.cpu0.dtb.write_hits 75914688 # DTB write hits -system.cpu0.dtb.write_misses 26760 # DTB write misses +system.cpu0.dtb.read_hits 85272873 # DTB read hits +system.cpu0.dtb.read_misses 78883 # DTB read misses +system.cpu0.dtb.write_hits 76479493 # DTB write hits +system.cpu0.dtb.write_misses 25956 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 42080 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1042 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 32159 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 40618 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1028 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 39585 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 3900 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 4176 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 8424 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 83842229 # DTB read accesses -system.cpu0.dtb.write_accesses 75941448 # DTB write accesses +system.cpu0.dtb.perms_faults 10186 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 85351756 # DTB read accesses +system.cpu0.dtb.write_accesses 76505449 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 159682046 # DTB hits -system.cpu0.dtb.misses 101631 # DTB misses -system.cpu0.dtb.accesses 159783677 # DTB accesses +system.cpu0.dtb.hits 161752366 # DTB hits +system.cpu0.dtb.misses 104839 # DTB misses +system.cpu0.dtb.accesses 161857205 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -506,235 +502,240 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 55722 # Table walker walks requested -system.cpu0.itb.walker.walksLong 55722 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 543 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 49598 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 55722 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 55722 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 55722 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 50141 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 22337.612912 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 19289.783493 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 21041.520478 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 48785 97.30% 97.30% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 1144 2.28% 99.58% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 57 0.11% 99.69% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 79 0.16% 99.85% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 56 0.11% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 13 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 3 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 50141 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples -241360296 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 -241360296 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total -241360296 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 49598 98.92% 98.92% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 543 1.08% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 50141 # Table walker page sizes translated +system.cpu0.itb.walker.walks 57460 # Table walker walks requested +system.cpu0.itb.walker.walksLong 57460 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 729 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 51308 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 57460 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 57460 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 57460 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 52037 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 22020.322079 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 19981.613647 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 15973.969343 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 48320 92.86% 92.86% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 2946 5.66% 98.52% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-98303 248 0.48% 98.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-131071 406 0.78% 99.78% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 23 0.04% 99.82% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-196607 9 0.02% 99.84% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-229375 33 0.06% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::229376-262143 6 0.01% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 15 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::294912-327679 16 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-360447 8 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::360448-393215 5 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 52037 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples -326738796 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -326738796 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total -326738796 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 51308 98.60% 98.60% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 729 1.40% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 52037 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 55722 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 55722 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 57460 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 57460 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 50141 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 50141 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 105863 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 444122432 # ITB inst hits -system.cpu0.itb.inst_misses 55722 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 52037 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 52037 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 109497 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 453477294 # ITB inst hits +system.cpu0.itb.inst_misses 57460 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 42080 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1042 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 22526 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 40618 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1028 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 27698 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 444178154 # ITB inst accesses -system.cpu0.itb.hits 444122432 # DTB hits -system.cpu0.itb.misses 55722 # DTB misses -system.cpu0.itb.accesses 444178154 # DTB accesses -system.cpu0.numCycles 95053909934 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 453534754 # ITB inst accesses +system.cpu0.itb.hits 453477294 # DTB hits +system.cpu0.itb.misses 57460 # DTB misses +system.cpu0.itb.accesses 453534754 # DTB accesses +system.cpu0.numCycles 94992773961 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 443872382 # Number of instructions committed -system.cpu0.committedOps 521690846 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 479475231 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 421225 # Number of float alu accesses -system.cpu0.num_func_calls 26535732 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 67239811 # number of instructions that are conditional controls -system.cpu0.num_int_insts 479475231 # number of integer instructions -system.cpu0.num_fp_insts 421225 # number of float instructions -system.cpu0.num_int_register_reads 693782505 # number of times the integer registers were read -system.cpu0.num_int_register_writes 380162379 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 701849 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 304628 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 115037577 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 114748059 # number of times the CC registers were written -system.cpu0.num_mem_refs 159672530 # number of memory refs -system.cpu0.num_load_insts 83761106 # Number of load instructions -system.cpu0.num_store_insts 75911424 # Number of store instructions -system.cpu0.num_idle_cycles 93959856753.206024 # Number of idle cycles -system.cpu0.num_busy_cycles 1094053180.793977 # Number of busy cycles -system.cpu0.not_idle_fraction 0.011510 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.988490 # Percentage of idle cycles -system.cpu0.Branches 99058393 # Number of branches fetched +system.cpu0.committedInsts 453209687 # Number of instructions committed +system.cpu0.committedOps 531499422 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 488089676 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 379595 # Number of float alu accesses +system.cpu0.num_func_calls 26785883 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 68737200 # number of instructions that are conditional controls +system.cpu0.num_int_insts 488089676 # number of integer instructions +system.cpu0.num_fp_insts 379595 # number of float instructions +system.cpu0.num_int_register_reads 710027821 # number of times the integer registers were read +system.cpu0.num_int_register_writes 387728381 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 639718 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 261592 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 118698555 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 118319526 # number of times the CC registers were written +system.cpu0.num_mem_refs 161743236 # number of memory refs +system.cpu0.num_load_insts 85268904 # Number of load instructions +system.cpu0.num_store_insts 76474332 # Number of store instructions +system.cpu0.num_idle_cycles 93849963781.964020 # Number of idle cycles +system.cpu0.num_busy_cycles 1142810179.035976 # Number of busy cycles +system.cpu0.not_idle_fraction 0.012030 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.987970 # Percentage of idle cycles +system.cpu0.Branches 100837041 # Number of branches fetched system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 361081858 69.17% 69.17% # Class of executed instruction -system.cpu0.op_class::IntMult 1125018 0.22% 69.39% # Class of executed instruction -system.cpu0.op_class::IntDiv 61306 0.01% 69.40% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 43308 0.01% 69.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction -system.cpu0.op_class::MemRead 83761106 16.05% 85.46% # Class of executed instruction -system.cpu0.op_class::MemWrite 75911424 14.54% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 368748107 69.34% 69.34% # Class of executed instruction +system.cpu0.op_class::IntMult 1224660 0.23% 69.57% # Class of executed instruction +system.cpu0.op_class::IntDiv 64156 0.01% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 29994 0.01% 69.59% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.59% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.59% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.59% # Class of executed instruction +system.cpu0.op_class::MemRead 85268904 16.03% 85.62% # Class of executed instruction +system.cpu0.op_class::MemWrite 76474332 14.38% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 521984020 # Class of executed instruction +system.cpu0.op_class::total 531810153 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 5106 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 5414405 # number of replacements -system.cpu0.dcache.tags.tagsinuse 480.206026 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 154030593 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5414914 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 28.445621 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 4071814500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.206026 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.937902 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.937902 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 344 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 324790756 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 324790756 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 77996551 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 77996551 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 71694037 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 71694037 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 187802 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 187802 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 131287 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 131287 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1831493 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1831493 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1787873 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1787873 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 149690588 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 149690588 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 149878390 # number of overall hits -system.cpu0.dcache.overall_hits::total 149878390 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 2964325 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 2964325 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1343066 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1343066 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 617580 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 617580 # number of SoftPFReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 739156 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 739156 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 153043 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 153043 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 195288 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 195288 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 4307391 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 4307391 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 4924971 # number of overall misses -system.cpu0.dcache.overall_misses::total 4924971 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 44154787210 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 44154787210 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 26046845450 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 26046845450 # number of WriteReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 30884044772 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 30884044772 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2257944026 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2257944026 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4202199390 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4202199390 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2186500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2186500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 70201632660 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 70201632660 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 70201632660 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 70201632660 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 80960876 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 80960876 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 73037103 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 73037103 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 805382 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 805382 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 870443 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 870443 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1984536 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 1984536 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1983161 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1983161 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 153997979 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 153997979 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 154803361 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 154803361 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036614 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.036614 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018389 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.018389 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.766816 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.766816 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.849172 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.849172 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.077118 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.077118 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.098473 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.098473 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027970 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.027970 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.031814 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.031814 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14895.393457 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14895.393457 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19393.570718 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 19393.570718 # average WriteReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 41782.850673 # average WriteInvalidateReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 41782.850673 # average WriteInvalidateReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14753.657639 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14753.657639 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21517.960090 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21517.960090 # average StoreCondReq miss latency +system.cpu0.kern.inst.quiesce 14069 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 5594005 # number of replacements +system.cpu0.dcache.tags.tagsinuse 472.878328 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 155905526 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5594517 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.867558 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 3986453000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 472.878328 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.923590 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.923590 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 337 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 329066714 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 329066714 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 79426163 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 79426163 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 72239104 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 72239104 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 186194 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 186194 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 137014 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 137014 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1774977 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1774977 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1742409 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1742409 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 151665267 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 151665267 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 151851461 # number of overall hits +system.cpu0.dcache.overall_hits::total 151851461 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3027243 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3027243 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1374655 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1374655 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 667737 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 667737 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 757348 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 757348 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 163489 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 163489 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 194173 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 194173 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 4401898 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 4401898 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 5069635 # number of overall misses +system.cpu0.dcache.overall_misses::total 5069635 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 43551375000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 43551375000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 25743175500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 25743175500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 46783649000 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 46783649000 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2342479000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2342479000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4171693500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4171693500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2590500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2590500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 69294550500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 69294550500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 69294550500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 69294550500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 82453406 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 82453406 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 73613759 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 73613759 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 853931 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 853931 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 894362 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 894362 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1938466 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 1938466 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1936582 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 1936582 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 156067165 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 156067165 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 156921096 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 156921096 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036715 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.036715 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018674 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.018674 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781957 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781957 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.846803 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.846803 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.084339 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.084339 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.100266 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.100266 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.028205 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.028205 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032307 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.032307 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14386.481363 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14386.481363 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18727.008231 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 18727.008231 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 61772.988111 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 61772.988111 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14328.052652 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14328.052652 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21484.415959 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21484.415959 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16297.947565 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 16297.947565 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14254.222545 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 14254.222545 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15741.970963 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 15741.970963 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13668.548229 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 13668.548229 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -743,157 +744,158 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 3655915 # number of writebacks -system.cpu0.dcache.writebacks::total 3655915 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 33290 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 33290 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21376 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 21376 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 42886 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 42886 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 54666 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 54666 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 54666 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 54666 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2931035 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 2931035 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1321690 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1321690 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 611921 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 611921 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 739156 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 739156 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 110157 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 110157 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 195288 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 195288 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 4252725 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 4252725 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 4864646 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 4864646 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16584 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 16584 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 18033 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 18033 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 34617 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 34617 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 38329059920 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 38329059920 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 23455096050 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 23455096050 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 13388812156 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 13388812156 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 29772038228 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 29772038228 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1440580476 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1440580476 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3899742610 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3899742610 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2117500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2117500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 61784155970 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 61784155970 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 75172968126 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 75172968126 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2701006250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2701006250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2792188500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2792188500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5493194750 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5493194750 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036203 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036203 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018096 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018096 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.759790 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.759790 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.849172 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.849172 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.055508 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.055508 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.098473 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.098473 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027615 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.027615 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031425 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.031425 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13076.971077 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13076.971077 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17746.291528 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17746.291528 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21879.968421 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 21879.968421 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 40278.423267 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 40278.423267 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13077.520956 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13077.520956 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19969.187098 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19969.187098 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 3814789 # number of writebacks +system.cpu0.dcache.writebacks::total 3814789 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 30828 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 30828 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21250 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 21250 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 41671 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 41671 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 52078 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 52078 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 52078 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 52078 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2996415 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 2996415 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1353405 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1353405 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 662134 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 662134 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 757348 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 757348 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 121818 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 121818 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 194173 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 194173 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4349820 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4349820 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5011954 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5011954 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 27090 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 27090 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 26689 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 26689 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 53779 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 53779 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 39330539500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 39330539500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 23857005000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 23857005000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 13760399000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 13760399000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 46026301000 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 46026301000 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1597973500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1597973500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3977579500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3977579500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2531500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2531500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 63187544500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 63187544500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 76947943500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 76947943500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4585847500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4585847500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4300128500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4300128500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 8885976000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 8885976000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036341 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036341 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018385 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018385 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.775395 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.775395 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.846803 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.846803 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062842 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062842 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.100266 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.100266 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027871 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.027871 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031939 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.031939 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13125.865242 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13125.865242 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17627.395347 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17627.395347 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 20781.894601 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 20781.894601 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 60772.988111 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 60772.988111 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13117.712489 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13117.712489 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20484.719812 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20484.719812 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14528.133366 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14528.133366 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15452.916435 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15452.916435 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 162868.201278 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162868.201278 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 154837.714191 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 154837.714191 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 158684.887483 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 158684.887483 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14526.473394 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14526.473394 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15352.883027 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15352.883027 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 169281.930602 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 169281.930602 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 161119.880850 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 161119.880850 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 165231.335651 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 165231.335651 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 5032307 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.899757 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 439089613 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 5032819 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 87.245262 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 33435686250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.899757 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999804 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999804 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 4817420 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.881006 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 448659362 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 4817932 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 93.122809 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 42527405000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.881006 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999768 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999768 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 217 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 121 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 229 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 893277683 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 893277683 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 439089613 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 439089613 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 439089613 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 439089613 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 439089613 # number of overall hits -system.cpu0.icache.overall_hits::total 439089613 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 5032819 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 5032819 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 5032819 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 5032819 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 5032819 # number of overall misses -system.cpu0.icache.overall_misses::total 5032819 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 52854361147 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 52854361147 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 52854361147 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 52854361147 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 52854361147 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 52854361147 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 444122432 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 444122432 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 444122432 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 444122432 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 444122432 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 444122432 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011332 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.011332 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011332 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.011332 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011332 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.011332 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10501.939598 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10501.939598 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10501.939598 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10501.939598 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10501.939598 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10501.939598 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 911772520 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 911772520 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 448659362 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 448659362 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 448659362 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 448659362 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 448659362 # number of overall hits +system.cpu0.icache.overall_hits::total 448659362 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 4817932 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 4817932 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 4817932 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 4817932 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 4817932 # number of overall misses +system.cpu0.icache.overall_misses::total 4817932 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 51018469500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 51018469500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 51018469500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 51018469500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 51018469500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 51018469500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 453477294 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 453477294 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 453477294 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 453477294 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 453477294 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 453477294 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010624 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.010624 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010624 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.010624 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010624 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.010624 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10589.287997 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10589.287997 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10589.287997 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10589.287997 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10589.287997 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10589.287997 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -902,239 +904,251 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5032819 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 5032819 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 5032819 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 5032819 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 5032819 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 5032819 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4817932 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 4817932 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 4817932 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 4817932 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 4817932 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 4817932 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 47804251855 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 47804251855 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 47804251855 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 47804251855 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 47804251855 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 47804251855 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3811870500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3811870500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 3811870500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 3811870500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011332 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011332 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011332 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.011332 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011332 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.011332 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9498.504090 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9498.504090 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9498.504090 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 9498.504090 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9498.504090 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 9498.504090 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88391.200000 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88391.200000 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88391.200000 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88391.200000 # average overall mshr uncacheable latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 48609503500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 48609503500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 48609503500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 48609503500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 48609503500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 48609503500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3777715000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3777715000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 3777715000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 3777715000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010624 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010624 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010624 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.010624 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010624 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.010624 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10089.287997 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10089.287997 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10089.287997 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10089.287997 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10089.287997 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10089.287997 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87599.188406 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 87599.188406 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87599.188406 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 87599.188406 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 7211191 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 7211221 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 21 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 7903007 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 7903048 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 35 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 945331 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 2374120 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16169.428044 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 10531211 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2389368 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 4.407530 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 5341335500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 8264.618229 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 69.150581 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 77.449352 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 3311.410043 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3382.587139 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1064.212699 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.504432 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004221 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004727 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.202112 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.206457 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.064954 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.986904 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1373 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 85 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 13790 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 173 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 780 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 417 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 54 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 15 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3709 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6679 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3275 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.083801 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005188 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.841675 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 244043620 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 244043620 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 211402 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 128647 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 4517111 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 2702351 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 7559511 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 3655914 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 3655914 # number of Writeback hits -system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 175642 # number of WriteInvalidateReq hits -system.cpu0.l2cache.WriteInvalidateReq_hits::total 175642 # number of WriteInvalidateReq hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 102383 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 102383 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 30801 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 30801 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 876779 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 876779 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 211402 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 128647 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 4517111 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 3579130 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 8436290 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 211402 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 128647 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 4517111 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 3579130 # number of overall hits -system.cpu0.l2cache.overall_hits::total 8436290 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 10881 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8892 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 515708 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 950762 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 1486243 # number of ReadReq misses -system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 562136 # number of WriteInvalidateReq misses -system.cpu0.l2cache.WriteInvalidateReq_misses::total 562136 # number of WriteInvalidateReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 120119 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 120119 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 164484 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 164484 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 3 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 240029 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 240029 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 10881 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8892 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 515708 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 1190791 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 1726272 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 10881 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8892 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 515708 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 1190791 # number of overall misses -system.cpu0.l2cache.overall_misses::total 1726272 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 393469249 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 355451999 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 15907969852 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 31938942740 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 48595833840 # number of ReadReq miss cycles -system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data 181717619 # number of WriteInvalidateReq miss cycles -system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total 181717619 # number of WriteInvalidateReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2563026586 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 2563026586 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3399427212 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3399427212 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2070498 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2070498 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 12166293140 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 12166293140 # number of ReadExReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 393469249 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 355451999 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 15907969852 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 44105235880 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 60762126980 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 393469249 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 355451999 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 15907969852 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 44105235880 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 60762126980 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 222283 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 137539 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 5032819 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 3653113 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 9045754 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 3655914 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 3655914 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 737778 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.l2cache.WriteInvalidateReq_accesses::total 737778 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 222502 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 222502 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 195285 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 195285 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 3 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1116808 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 1116808 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 222283 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 137539 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 5032819 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 4769921 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 10162562 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 222283 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 137539 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 5032819 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 4769921 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 10162562 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.048951 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.064651 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.102469 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.260261 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.164303 # miss rate for ReadReq accesses -system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.761931 # miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.761931 # miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.539856 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.539856 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.842277 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.842277 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.prefetcher.pfSpanPage 1031104 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 2447325 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 15787.482525 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 17072683 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2462926 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 6.931870 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 38930323500 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 7763.481265 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 64.845053 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 94.926815 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 3265.491531 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3523.056672 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1075.681189 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.473845 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003958 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.005794 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.199310 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.215030 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.065654 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.963591 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1662 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 82 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 13857 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 291 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 746 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 625 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 46 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 25 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 107 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2497 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5813 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 5388 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.101440 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005005 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.845764 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 352133802 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 352133802 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 213691 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 129371 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 343062 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 3814786 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 3814786 # number of Writeback hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 99833 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 99833 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 32914 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 32914 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 902621 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 902621 # number of ReadExReq hits +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4275985 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadCleanReq_hits::total 4275985 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2838458 # number of ReadSharedReq hits +system.cpu0.l2cache.ReadSharedReq_hits::total 2838458 # number of ReadSharedReq hits +system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 175241 # number of InvalidateReq hits +system.cpu0.l2cache.InvalidateReq_hits::total 175241 # number of InvalidateReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 213691 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 129371 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 4275985 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 3741079 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 8360126 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 213691 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 129371 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 4275985 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 3741079 # number of overall hits +system.cpu0.l2cache.overall_hits::total 8360126 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 9038 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 7286 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 16324 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 121358 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 121358 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 161252 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 161252 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 7 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 246467 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 246467 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 541947 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 541947 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 941909 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 941909 # number of ReadSharedReq misses +system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 580933 # number of InvalidateReq misses +system.cpu0.l2cache.InvalidateReq_misses::total 580933 # number of InvalidateReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 9038 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 7286 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 541947 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 1188376 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 1746647 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 9038 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 7286 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 541947 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 1188376 # number of overall misses +system.cpu0.l2cache.overall_misses::total 1746647 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 297968500 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 261413000 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 559381500 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2650604000 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 2650604000 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3370536000 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3370536000 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2441998 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2441998 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 11722428500 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 11722428500 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 15931119500 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::total 15931119500 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 30566703000 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::total 30566703000 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 43739049000 # number of InvalidateReq miss cycles +system.cpu0.l2cache.InvalidateReq_miss_latency::total 43739049000 # number of InvalidateReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 297968500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 261413000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 15931119500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 42289131500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 58779632500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 297968500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 261413000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 15931119500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 42289131500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 58779632500 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 222729 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 136657 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 359386 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 3814786 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 3814786 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 221191 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 221191 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 194166 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 194166 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 7 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1149088 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 1149088 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 4817932 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::total 4817932 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3780367 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::total 3780367 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 756174 # number of InvalidateReq accesses(hits+misses) +system.cpu0.l2cache.InvalidateReq_accesses::total 756174 # number of InvalidateReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 222729 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 136657 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 4817932 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 4929455 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 10106773 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 222729 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 136657 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 4817932 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 4929455 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 10106773 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.040578 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.053316 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.045422 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.548657 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.548657 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.830485 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.830485 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.214924 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.214924 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.048951 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.064651 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.102469 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.249646 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.169866 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.048951 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.064651 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.102469 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.249646 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.169866 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 36161.129400 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 39974.358862 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 30846.854910 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 33592.994609 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32697.098550 # average ReadReq miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.data 323.262732 # average WriteInvalidateReq miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total 323.262732 # average WriteInvalidateReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21337.395300 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21337.395300 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20667.221201 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20667.221201 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 690166 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 690166 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50686.763433 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50686.763433 # average ReadExReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 36161.129400 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 39974.358862 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 30846.854910 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 37038.603651 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 35198.466395 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 36161.129400 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 39974.358862 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 30846.854910 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 37038.603651 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 35198.466395 # average overall miss latency +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.214489 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.214489 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.112485 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.112485 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.249158 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.249158 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.768253 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.768253 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.040578 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.053316 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.112485 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.241077 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.172819 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.040578 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.053316 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.112485 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.241077 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.172819 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 32968.411153 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 35878.808674 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 34267.428326 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21841.197119 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21841.197119 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20902.289584 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20902.289584 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 348856.857143 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 348856.857143 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 47561.858180 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 47561.858180 # average ReadExReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 29396.083934 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 29396.083934 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 32451.864246 # average ReadSharedReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 32451.864246 # average ReadSharedReq miss latency +system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 75291.038726 # average InvalidateReq miss latency +system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 75291.038726 # average InvalidateReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 32968.411153 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 35878.808674 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 29396.083934 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35585.649239 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 33652.840271 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 32968.411153 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 35878.808674 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 29396.083934 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35585.649239 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 33652.840271 # average overall miss latency system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1143,201 +1157,218 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 1321734 # number of writebacks -system.cpu0.l2cache.writebacks::total 1321734 # number of writebacks -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 498 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::total 498 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 6011 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 6011 # number of ReadExReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6509 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 6509 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6509 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 6509 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 10881 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8892 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 515708 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 950264 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 1485745 # number of ReadReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 659076 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 659076 # number of HardPFReq MSHR misses -system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.data 562136 # number of WriteInvalidateReq MSHR misses -system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total 562136 # number of WriteInvalidateReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 120119 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 120119 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 164484 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 164484 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 3 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 234018 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 234018 # number of ReadExReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 10881 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8892 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 515708 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1184282 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 1719763 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 10881 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8892 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 515708 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1184282 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 659076 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 2378839 # number of overall MSHR misses +system.cpu0.l2cache.writebacks::writebacks 1370697 # number of writebacks +system.cpu0.l2cache.writebacks::total 1370697 # number of writebacks +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 4625 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 4625 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 320 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 320 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 4945 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 4945 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 4945 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 4945 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 9038 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 7286 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 16324 # number of ReadReq MSHR misses +system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 97439 # number of CleanEvict MSHR misses +system.cpu0.l2cache.CleanEvict_mshr_misses::total 97439 # number of CleanEvict MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 677798 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 677798 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 121358 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 121358 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 161252 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 161252 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 7 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 7 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 241842 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 241842 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 541947 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 541947 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 941589 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 941589 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 580933 # number of InvalidateReq MSHR misses +system.cpu0.l2cache.InvalidateReq_mshr_misses::total 580933 # number of InvalidateReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 9038 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 7286 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 541947 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1183431 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 1741702 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 9038 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 7286 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 541947 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1183431 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 677798 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 2419500 # number of overall MSHR misses system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 16584 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 59709 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 18033 # number of WriteReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 18033 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 27090 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 70215 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 26689 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 26689 # number of WriteReq MSHR uncacheable system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 34617 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 77742 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 322190251 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 297082001 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 12538366148 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 25676104173 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 38833742573 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 32139076466 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 32139076466 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 24223804784 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 24223804784 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2466827080 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2466827080 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2435399890 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2435399890 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1771498 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1771498 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 9980703954 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 9980703954 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 322190251 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 297082001 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 12538366148 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 35656808127 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 48814446527 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 322190251 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 297082001 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 12538366148 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 35656808127 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 32139076466 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 80953522993 # number of overall MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3468251000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2568327500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6036578500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2656940000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2656940000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 3468251000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5225267500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 8693518500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.048951 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.064651 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.102469 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.260124 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.164248 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 53779 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 96904 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 243740500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 217697000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 461437500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 28787351301 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 28787351301 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2500247000 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2500247000 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2505266500 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2505266500 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2087998 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2087998 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 9802286000 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 9802286000 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 12679437500 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 12679437500 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 24890887500 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 24890887500 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 40253451000 # number of InvalidateReq MSHR miss cycles +system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 40253451000 # number of InvalidateReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 243740500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 217697000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 12679437500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 34693173500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 47834048500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 243740500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 217697000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 12679437500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 34693173500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 28787351301 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 76621399801 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3454277500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4369127500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7823405000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 4099961000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4099961000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 3454277500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 8469088500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11923366000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.040578 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.053316 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.045422 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.761931 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.761931 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.539856 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.539856 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.842277 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.842277 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.548657 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.548657 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.830485 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.830485 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.209542 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.209542 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.048951 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.064651 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.102469 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.248281 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.169225 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.048951 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.064651 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.102469 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.248281 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.210464 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.210464 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.112485 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.112485 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.249073 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249073 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.768253 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.768253 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.040578 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.053316 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.112485 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.240073 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.172330 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.040578 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.053316 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.112485 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.240073 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.234079 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 29610.353001 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 33410.031601 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24312.917674 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 27019.969370 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26137.555619 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48763.839779 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 48763.839779 # average HardPFReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 43092.427427 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 43092.427427 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20536.526944 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20536.526944 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14806.302680 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14806.302680 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 590499.333333 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 590499.333333 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 42649.300285 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 42649.300285 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 29610.353001 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 33410.031601 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24312.917674 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 30108.376322 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 28384.403274 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 29610.353001 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 33410.031601 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24312.917674 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 30108.376322 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48763.839779 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34030.685975 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80423.211594 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 154867.794260 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 101099.976553 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 147337.658737 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 147337.658737 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80423.211594 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 150945.128116 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 111825.248900 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.239394 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 26968.411153 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 29878.808674 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28267.428326 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 42471.874070 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 42471.874070 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20602.242951 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20602.242951 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15536.343735 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15536.343735 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 298285.428571 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 298285.428571 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40531.776945 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40531.776945 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 23396.083934 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 23396.083934 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26434.981186 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26434.981186 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 69291.038726 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69291.038726 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26968.411153 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 29878.808674 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23396.083934 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29315.755207 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27463.968291 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 26968.411153 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 29878.808674 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23396.083934 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29315.755207 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 42471.874070 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 31668.278488 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80099.188406 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 161281.930602 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 111420.707826 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 153619.880850 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 153619.880850 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80099.188406 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 157479.471541 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 123043.073557 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 11389901 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 9301467 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 38146 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 18033 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 3655914 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 950949 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1103178 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 737778 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 440847 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 362789 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 484218 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 43 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 86 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1248974 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1125262 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 10151888 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 15745151 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 304033 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 517558 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 26718630 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 322272916 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 593126965 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1100312 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1778264 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 918278457 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 4307980 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 19190741 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 1.234424 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.423639 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 556196 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 9235290 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 37997 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 26689 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 7191964 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 8875110 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 964168 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 5 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 427001 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 350742 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 480184 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 44 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 96 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1494626 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1158048 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 4817932 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5665215 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 862902 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 756174 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 14539205 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18068890 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 308145 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 526057 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 33442297 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 308520148 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 566266158 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1093256 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1781832 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 877661394 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 9623929 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 31244724 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 1.314212 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.464201 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 14691964 76.56% 76.56% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 4498777 23.44% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 21427251 68.58% 68.58% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 9817473 31.42% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 19190741 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 11979643994 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 31244724 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 14779167493 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 187059488 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 183875487 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 7611089646 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 7270023000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 7824710310 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 8020770875 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 166780001 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 171488000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 295551751 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 303329497 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1368,68 +1399,74 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 115983 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 115983 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11170 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 89969 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 19 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 115964 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 0.064675 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 22.024176 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-511 115963 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::7168-7679 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 115964 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 101158 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 19050.238172 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 17171.563979 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 14858.973019 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 99918 98.77% 98.77% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1061 1.05% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 33 0.03% 99.86% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 72 0.07% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 53 0.05% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 11 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 101158 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 3223072220 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.344065 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.475063 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 2114124352 65.59% 65.59% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 1108947868 34.41% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 3223072220 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 89969 88.96% 88.96% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 11170 11.04% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 101139 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 115983 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 102079 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 102079 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8198 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 78187 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 17 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 102062 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.078384 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 25.041362 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-511 102061 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::7680-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 102062 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 86402 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 20584.963311 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 18803.464379 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 14594.922091 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 82288 95.24% 95.24% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 3069 3.55% 98.79% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 485 0.56% 99.35% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 417 0.48% 99.83% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-163839 20 0.02% 99.86% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-196607 14 0.02% 99.87% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-229375 31 0.04% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::229376-262143 11 0.01% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 20 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::294912-327679 27 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-360447 7 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::360448-393215 6 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-425983 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 86402 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -6989065760 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.774297 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.418044 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -1577450036 22.57% 22.57% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 -5411615724 77.43% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -6989065760 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 78188 90.51% 90.51% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 8198 9.49% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 86386 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 102079 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 115983 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 101139 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 102079 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 86386 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 101139 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 217122 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 86386 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 188465 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 83993689 # DTB read hits -system.cpu1.dtb.read_misses 86321 # DTB read misses -system.cpu1.dtb.write_hits 76478778 # DTB write hits -system.cpu1.dtb.write_misses 29662 # DTB write misses +system.cpu1.dtb.read_hits 79156855 # DTB read hits +system.cpu1.dtb.read_misses 74074 # DTB read misses +system.cpu1.dtb.write_hits 72945567 # DTB write hits +system.cpu1.dtb.write_misses 28005 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 42080 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1042 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 42752 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 40618 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1028 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 34474 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4958 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4171 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 11385 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 84080010 # DTB read accesses -system.cpu1.dtb.write_accesses 76508440 # DTB write accesses +system.cpu1.dtb.perms_faults 9254 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 79230929 # DTB read accesses +system.cpu1.dtb.write_accesses 72973572 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 160472467 # DTB hits -system.cpu1.dtb.misses 115983 # DTB misses -system.cpu1.dtb.accesses 160588450 # DTB accesses +system.cpu1.dtb.hits 152102422 # DTB hits +system.cpu1.dtb.misses 102079 # DTB misses +system.cpu1.dtb.accesses 152204501 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1459,236 +1496,241 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 60651 # Table walker walks requested -system.cpu1.itb.walker.walksLong 60651 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 616 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 54731 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 60651 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 60651 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 60651 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 55347 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 21982.528123 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 19135.216139 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 20466.687075 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 53969 97.51% 97.51% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 1178 2.13% 99.64% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 42 0.08% 99.71% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 68 0.12% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 60 0.11% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 20 0.04% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 5 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 3 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 55347 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 2053569352 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 2053569352 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 2053569352 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 54731 98.89% 98.89% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 616 1.11% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 55347 # Table walker page sizes translated +system.cpu1.itb.walker.walks 60277 # Table walker walks requested +system.cpu1.itb.walker.walksLong 60277 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 437 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 54558 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 60277 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 60277 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 60277 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 54995 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 23406.355123 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 21056.017834 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 18686.344458 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 50855 92.47% 92.47% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 2976 5.41% 97.88% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 347 0.63% 98.51% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 645 1.17% 99.69% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 26 0.05% 99.73% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 14 0.03% 99.76% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 61 0.11% 99.87% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 8 0.01% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 27 0.05% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 12 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 10 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 6 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-425983 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-491519 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::491520-524287 4 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 54995 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -1687858036 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1687858036 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1687858036 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 54558 99.21% 99.21% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 437 0.79% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 54995 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60651 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60651 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60277 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60277 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55347 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55347 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 115998 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 446979774 # ITB inst hits -system.cpu1.itb.inst_misses 60651 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 54995 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 54995 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 115272 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 419908062 # ITB inst hits +system.cpu1.itb.inst_misses 60277 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 42080 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1042 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 29800 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 40618 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1028 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 24325 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 447040425 # ITB inst accesses -system.cpu1.itb.hits 446979774 # DTB hits -system.cpu1.itb.misses 60651 # DTB misses -system.cpu1.itb.accesses 447040425 # DTB accesses -system.cpu1.numCycles 95053909934 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 419968339 # ITB inst accesses +system.cpu1.itb.hits 419908062 # DTB hits +system.cpu1.itb.misses 60277 # DTB misses +system.cpu1.itb.accesses 419968339 # DTB accesses +system.cpu1.numCycles 94992773961 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 446673984 # Number of instructions committed -system.cpu1.committedOps 525768473 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 482657433 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 472663 # Number of float alu accesses -system.cpu1.num_func_calls 26533376 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 68272280 # number of instructions that are conditional controls -system.cpu1.num_int_insts 482657433 # number of integer instructions -system.cpu1.num_fp_insts 472663 # number of float instructions -system.cpu1.num_int_register_reads 706740468 # number of times the integer registers were read -system.cpu1.num_int_register_writes 383340050 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 750974 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 430296 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 118015071 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 117677935 # number of times the CC registers were written -system.cpu1.num_mem_refs 160465117 # number of memory refs -system.cpu1.num_load_insts 83993061 # Number of load instructions -system.cpu1.num_store_insts 76472056 # Number of store instructions -system.cpu1.num_idle_cycles 93999959015.450027 # Number of idle cycles -system.cpu1.num_busy_cycles 1053950918.549978 # Number of busy cycles -system.cpu1.not_idle_fraction 0.011088 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.988912 # Percentage of idle cycles -system.cpu1.Branches 99666047 # Number of branches fetched +system.cpu1.committedInsts 419630835 # Number of instructions committed +system.cpu1.committedOps 495261733 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 455389756 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 523939 # Number of float alu accesses +system.cpu1.num_func_calls 25402387 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 63797614 # number of instructions that are conditional controls +system.cpu1.num_int_insts 455389756 # number of integer instructions +system.cpu1.num_fp_insts 523939 # number of float instructions +system.cpu1.num_int_register_reads 660733277 # number of times the integer registers were read +system.cpu1.num_int_register_writes 360799808 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 826391 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 485612 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 108763380 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 108525865 # number of times the CC registers were written +system.cpu1.num_mem_refs 152092816 # number of memory refs +system.cpu1.num_load_insts 79152639 # Number of load instructions +system.cpu1.num_store_insts 72940177 # Number of store instructions +system.cpu1.num_idle_cycles 94000482737.518021 # Number of idle cycles +system.cpu1.num_busy_cycles 992291223.481979 # Number of busy cycles +system.cpu1.not_idle_fraction 0.010446 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.989554 # Percentage of idle cycles +system.cpu1.Branches 93826575 # Number of branches fetched system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 364374913 69.26% 69.26% # Class of executed instruction -system.cpu1.op_class::IntMult 1108574 0.21% 69.47% # Class of executed instruction -system.cpu1.op_class::IntDiv 57501 0.01% 69.48% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 68224 0.01% 69.50% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::MemRead 83993061 15.97% 85.46% # Class of executed instruction -system.cpu1.op_class::MemWrite 76472056 14.54% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 342323632 69.08% 69.08% # Class of executed instruction +system.cpu1.op_class::IntMult 986133 0.20% 69.28% # Class of executed instruction +system.cpu1.op_class::IntDiv 54444 0.01% 69.29% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 82001 0.02% 69.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.31% # Class of executed instruction +system.cpu1.op_class::MemRead 79152639 15.97% 85.28% # Class of executed instruction +system.cpu1.op_class::MemWrite 72940177 14.72% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 526074372 # Class of executed instruction +system.cpu1.op_class::total 495539069 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 14059 # number of quiesce instructions executed -system.cpu1.dcache.tags.replacements 5413042 # number of replacements -system.cpu1.dcache.tags.tagsinuse 455.092206 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 154856630 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5413554 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 28.605354 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8382280704500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 455.092206 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.888852 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.888852 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 419 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 326337345 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 326337345 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 78172197 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 78172197 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 72471418 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 72471418 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 183858 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 183858 # number of SoftPFReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 197039 # number of WriteInvalidateReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::total 197039 # number of WriteInvalidateReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1730902 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1730902 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1704111 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1704111 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 150643615 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 150643615 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 150827473 # number of overall hits -system.cpu1.dcache.overall_hits::total 150827473 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 3026410 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 3026410 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1374450 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1374450 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 681215 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 681215 # number of SoftPFReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 497314 # number of WriteInvalidateReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::total 497314 # number of WriteInvalidateReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 177400 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 177400 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 202765 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 202765 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 4400860 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 4400860 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 5082075 # number of overall misses -system.cpu1.dcache.overall_misses::total 5082075 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 44105582717 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 44105582717 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 23281173553 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 23281173553 # number of WriteReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 13579881027 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 13579881027 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2688373759 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2688373759 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4348203540 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4348203540 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1867000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1867000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 67386756270 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 67386756270 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 67386756270 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 67386756270 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 81198607 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 81198607 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 73845868 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 73845868 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 865073 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 865073 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 694353 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::total 694353 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1908302 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1908302 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1906876 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1906876 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 155044475 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 155044475 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 155909548 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 155909548 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037272 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.037272 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018612 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.018612 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.787465 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.787465 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.716226 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.716226 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.092962 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.092962 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106334 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106334 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.028385 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.028385 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.032596 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.032596 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14573.564956 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14573.564956 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16938.537999 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 16938.537999 # average WriteReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 27306.452316 # average WriteInvalidateReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 27306.452316 # average WriteInvalidateReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15154.305293 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15154.305293 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21444.546840 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21444.546840 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 5086 # number of quiesce instructions executed +system.cpu1.dcache.tags.replacements 4879882 # number of replacements +system.cpu1.dcache.tags.tagsinuse 454.664905 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 147036928 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 4880392 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 30.128098 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8391455352000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 454.664905 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.888017 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.888017 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 414 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 309114667 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 309114667 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 73769374 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 73769374 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 69164773 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 69164773 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 181014 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 181014 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 188653 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 188653 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1698614 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1698614 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1666903 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1666903 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 142934147 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 142934147 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 143115161 # number of overall hits +system.cpu1.dcache.overall_hits::total 143115161 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 2759570 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 2759570 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1240940 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1240940 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 581228 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 581228 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 477261 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 477261 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 156018 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 156018 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 186042 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 186042 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 4000510 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 4000510 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 4581738 # number of overall misses +system.cpu1.dcache.overall_misses::total 4581738 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 39233003500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 39233003500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 20835462500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 20835462500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 14509055000 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 14509055000 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2381741000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2381741000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3985246000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 3985246000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1637000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1637000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 60068466000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 60068466000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 60068466000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 60068466000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 76528944 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 76528944 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 70405713 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 70405713 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 762242 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 762242 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 665914 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 665914 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1854632 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1854632 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1852945 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1852945 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 146934657 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 146934657 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 147696899 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 147696899 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036059 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.036059 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.017626 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.017626 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.762524 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.762524 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.716701 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.716701 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.084123 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.084123 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100403 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100403 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027226 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.027226 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.031021 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.031021 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14217.071319 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14217.071319 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16790.064387 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 16790.064387 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 30400.671750 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 30400.671750 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15265.809073 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15265.809073 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21421.216715 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21421.216715 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15312.179045 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 15312.179045 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13259.693387 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 13259.693387 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15015.202062 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 15015.202062 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13110.410504 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 13110.410504 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1697,158 +1739,157 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 3550271 # number of writebacks -system.cpu1.dcache.writebacks::total 3550271 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 18006 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 18006 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 425 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 425 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44886 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 44886 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 18431 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 18431 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 18431 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 18431 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3008404 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 3008404 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1374025 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1374025 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 681215 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 681215 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 497314 # number of WriteInvalidateReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 497314 # number of WriteInvalidateReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 132514 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 132514 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 202765 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 202765 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4382429 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4382429 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 5063644 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 5063644 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 21725 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 21725 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 20113 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 20113 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 41838 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 41838 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 38446720676 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 38446720676 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 21137642197 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 21137642197 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13605784836 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13605784836 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 12830642973 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 12830642973 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1690394742 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1690394742 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4033173960 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4033173960 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1807000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1807000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 59584362873 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 59584362873 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 73190147709 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 73190147709 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3727466501 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3727466501 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3465674500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3465674500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 7193141001 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 7193141001 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037050 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037050 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018607 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018607 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.787465 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.787465 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.716226 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.716226 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.069441 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.069441 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106334 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106334 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028266 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.028266 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032478 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.032478 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12779.773154 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12779.773154 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15383.739158 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15383.739158 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19972.820381 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 19972.820381 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 25799.882917 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25799.882917 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12756.348325 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12756.348325 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19890.878406 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19890.878406 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 3169454 # number of writebacks +system.cpu1.dcache.writebacks::total 3169454 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 14967 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 14967 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 437 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 437 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44200 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 44200 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 15404 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 15404 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 15404 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 15404 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2744603 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2744603 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1240503 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1240503 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 581228 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 581228 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 477261 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 477261 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 111818 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 111818 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 186042 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 186042 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 3985106 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 3985106 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 4566334 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 4566334 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 11055 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 11055 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11308 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11308 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 22363 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 22363 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 35762824500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 35762824500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 19580379500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 19580379500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 11426394500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 11426394500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 14031794000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 14031794000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1521108000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1521108000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3799241000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3799241000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1600000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1600000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 55343204000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 55343204000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 66769598500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 66769598500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1911574500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1911574500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2027224500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2027224500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 3938799000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 3938799000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035864 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035864 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017619 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017619 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.762524 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.762524 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.716701 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.716701 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060291 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.060291 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100403 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100403 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027122 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027122 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030917 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.030917 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13030.235885 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13030.235885 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15784.225834 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15784.225834 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19659.057203 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 19659.057203 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 29400.671750 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 29400.671750 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13603.426997 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13603.426997 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20421.415594 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20421.415594 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13596.195825 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13596.195825 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14454.046870 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14454.046870 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171574.982785 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171574.982785 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 172310.172525 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172310.172525 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 171928.414384 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 171928.414384 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13887.511148 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13887.511148 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14622.145139 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14622.145139 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172914.925373 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172914.925373 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 179273.478953 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 179273.478953 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 176130.170371 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 176130.170371 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 4892397 # number of replacements -system.cpu1.icache.tags.tagsinuse 496.394395 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 442086860 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 4892909 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 90.352561 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8382252985250 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.394395 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969520 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.969520 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 5061942 # number of replacements +system.cpu1.icache.tags.tagsinuse 496.285809 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 414845603 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 5062454 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 81.945555 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8391427807000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.285809 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969308 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.969308 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 283 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 151 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 327 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 126 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 898852462 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 898852462 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 442086860 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 442086860 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 442086860 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 442086860 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 442086860 # number of overall hits -system.cpu1.icache.overall_hits::total 442086860 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 4892914 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 4892914 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 4892914 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 4892914 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 4892914 # number of overall misses -system.cpu1.icache.overall_misses::total 4892914 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 51771462698 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 51771462698 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 51771462698 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 51771462698 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 51771462698 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 51771462698 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 446979774 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 446979774 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 446979774 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 446979774 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 446979774 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 446979774 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.010947 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.010947 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.010947 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.010947 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.010947 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.010947 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10580.905918 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 10580.905918 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10580.905918 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10580.905918 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10580.905918 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10580.905918 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 844878583 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 844878583 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 414845603 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 414845603 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 414845603 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 414845603 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 414845603 # number of overall hits +system.cpu1.icache.overall_hits::total 414845603 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 5062459 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 5062459 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 5062459 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 5062459 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 5062459 # number of overall misses +system.cpu1.icache.overall_misses::total 5062459 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 51775886000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 51775886000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 51775886000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 51775886000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 51775886000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 51775886000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 419908062 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 419908062 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 419908062 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 419908062 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 419908062 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 419908062 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.012056 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.012056 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.012056 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.012056 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.012056 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.012056 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10227.418336 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 10227.418336 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10227.418336 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10227.418336 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10227.418336 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10227.418336 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1857,243 +1898,256 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 4892914 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 4892914 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 4892914 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 4892914 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 4892914 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 4892914 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5062459 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 5062459 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 5062459 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 5062459 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 5062459 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 5062459 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 110 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 46862593334 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 46862593334 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 46862593334 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 46862593334 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 46862593334 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 46862593334 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10105750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10105750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10105750 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 10105750 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.010947 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.010947 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.010947 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.010947 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.010947 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.010947 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9577.645005 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9577.645005 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9577.645005 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 9577.645005 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9577.645005 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 9577.645005 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 91870.454545 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 91870.454545 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 91870.454545 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 91870.454545 # average overall mshr uncacheable latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 49244656500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 49244656500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 49244656500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 49244656500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 49244656500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 49244656500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9661500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9661500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9661500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 9661500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.012056 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.012056 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.012056 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.012056 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.012056 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.012056 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9727.418336 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9727.418336 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9727.418336 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 9727.418336 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9727.418336 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 9727.418336 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 87831.818182 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 87831.818182 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 87831.818182 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 87831.818182 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 7631682 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 7631760 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 35 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 6553328 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 6553344 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 935080 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 2142260 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13497.078408 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 10799538 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2158371 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 5.003560 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9893608612000 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 5297.531895 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 78.016993 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 87.104378 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3470.735386 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3768.987855 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 794.701900 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.323336 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004762 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005316 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.211837 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.230041 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.048505 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.823796 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1633 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 75 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14403 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 31 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 128 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 713 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 761 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 32 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 43 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 926 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1571 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5509 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 6302 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.099670 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004578 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.879089 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 240281832 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 240281832 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 248777 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 141659 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 4360207 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 2869888 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 7620531 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 3550270 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 3550270 # number of Writeback hits -system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 228063 # number of WriteInvalidateReq hits -system.cpu1.l2cache.WriteInvalidateReq_hits::total 228063 # number of WriteInvalidateReq hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 73786 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 73786 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 35221 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 35221 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 953536 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 953536 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 248777 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 141659 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 4360207 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3823424 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 8574067 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 248777 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 141659 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 4360207 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3823424 # number of overall hits -system.cpu1.l2cache.overall_hits::total 8574067 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 9961 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 7958 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 532707 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 952245 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 1502871 # number of ReadReq misses +system.cpu1.l2cache.prefetcher.pfSpanPage 818232 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 1797985 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13499.130791 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 17098114 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 1814056 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 9.425351 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 10027287971500 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 5261.606925 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 74.626364 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 80.602782 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3547.198081 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3740.075738 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 795.020901 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.321143 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004555 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004920 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.216504 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.228276 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.048524 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.823922 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1537 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 61 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14473 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 17 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 338 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 619 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 563 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 23 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 24 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 884 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4486 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5048 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3979 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.093811 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003723 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.883362 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 335653129 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 335653129 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 217635 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 143511 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 361146 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 3169452 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 3169452 # number of Writeback hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 61375 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 61375 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 29429 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 29429 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 854276 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 854276 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4594945 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 4594945 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2597133 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 2597133 # number of ReadSharedReq hits +system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 245829 # number of InvalidateReq hits +system.cpu1.l2cache.InvalidateReq_hits::total 245829 # number of InvalidateReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 217635 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 143511 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 4594945 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 3451409 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 8407500 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 217635 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 143511 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 4594945 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 3451409 # number of overall hits +system.cpu1.l2cache.overall_hits::total 8407500 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 9790 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8267 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 18057 # number of ReadReq misses system.cpu1.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses system.cpu1.l2cache.Writeback_misses::total 1 # number of Writeback misses -system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 267701 # number of WriteInvalidateReq misses -system.cpu1.l2cache.WriteInvalidateReq_misses::total 267701 # number of WriteInvalidateReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 120750 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 120750 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 167539 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 167539 # number of SCUpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 120456 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 120456 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 156608 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 156608 # number of SCUpgradeReq misses system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 5 # number of SCUpgradeFailReq misses system.cpu1.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 227703 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 227703 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 9961 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 7958 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 532707 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 1179948 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 1730574 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 9961 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 7958 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 532707 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 1179948 # number of overall misses -system.cpu1.l2cache.overall_misses::total 1730574 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 394640977 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 358915726 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 16056528318 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 31264991014 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 48075076035 # number of ReadReq miss cycles -system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data 240883663 # number of WriteInvalidateReq miss cycles -system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 240883663 # number of WriteInvalidateReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2642176746 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 2642176746 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3519293594 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3519293594 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1767000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1767000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 9869071556 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 9869071556 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 394640977 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 358915726 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 16056528318 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 41134062570 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 57944147591 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 394640977 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 358915726 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 16056528318 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 41134062570 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 57944147591 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 258738 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 149617 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 4892914 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 3822133 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 9123402 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 3550271 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 3550271 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 495764 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.l2cache.WriteInvalidateReq_accesses::total 495764 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 194536 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 194536 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 202760 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 202760 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 206111 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 206111 # number of ReadExReq misses +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 467514 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadCleanReq_misses::total 467514 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 840516 # number of ReadSharedReq misses +system.cpu1.l2cache.ReadSharedReq_misses::total 840516 # number of ReadSharedReq misses +system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 229973 # number of InvalidateReq misses +system.cpu1.l2cache.InvalidateReq_misses::total 229973 # number of InvalidateReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 9790 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8267 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 467514 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 1046627 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 1532198 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 9790 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8267 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 467514 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 1046627 # number of overall misses +system.cpu1.l2cache.overall_misses::total 1532198 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 350581000 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 322699500 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 673280500 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2589720500 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 2589720500 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3249045500 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3249045500 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1543999 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1543999 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 8558602000 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 8558602000 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 14244872000 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::total 14244872000 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 26670955500 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::total 26670955500 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 11700893500 # number of InvalidateReq miss cycles +system.cpu1.l2cache.InvalidateReq_miss_latency::total 11700893500 # number of InvalidateReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 350581000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 322699500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 14244872000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 35229557500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 50147710000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 350581000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 322699500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 14244872000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 35229557500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 50147710000 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 227425 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 151778 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 379203 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 3169453 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 3169453 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 181831 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 181831 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 186037 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 186037 # number of SCUpgradeReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 5 # number of SCUpgradeFailReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1181239 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 1181239 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 258738 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 149617 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 4892914 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 5003372 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 10304641 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 258738 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 149617 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 4892914 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 5003372 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 10304641 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.038498 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.053189 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.108873 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.249140 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.164727 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1060387 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 1060387 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5062459 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::total 5062459 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3437649 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::total 3437649 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 475802 # number of InvalidateReq accesses(hits+misses) +system.cpu1.l2cache.InvalidateReq_accesses::total 475802 # number of InvalidateReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 227425 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 151778 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 5062459 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 4498036 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 9939698 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 227425 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 151778 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 5062459 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 4498036 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 9939698 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.043047 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.054468 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.047618 # miss rate for ReadReq accesses system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000000 # miss rate for Writeback accesses system.cpu1.l2cache.Writeback_miss_rate::total 0.000000 # miss rate for Writeback accesses -system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.539977 # miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.539977 # miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.620708 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.620708 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.826292 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.826292 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.662461 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.662461 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.841811 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.841811 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.192766 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.192766 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.038498 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.053189 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.108873 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.235831 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.167941 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.038498 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.053189 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.108873 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.235831 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.167941 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 39618.610280 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 45101.247298 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 30141.387889 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 32832.927465 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 31988.824081 # average ReadReq miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data 899.823546 # average WriteInvalidateReq miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 899.823546 # average WriteInvalidateReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21881.380919 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21881.380919 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 21005.817117 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 21005.817117 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 353400 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 353400 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 43341.860037 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 43341.860037 # average ReadExReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 39618.610280 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 45101.247298 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 30141.387889 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34860.911303 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 33482.617670 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 39618.610280 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 45101.247298 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 30141.387889 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34860.911303 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 33482.617670 # average overall miss latency +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.194373 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.194373 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.092349 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.092349 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.244503 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.244503 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.483338 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.483338 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.043047 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.054468 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.092349 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.232685 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.154149 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.043047 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.054468 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.092349 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.232685 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.154149 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 35810.112360 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 39034.655861 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 37286.398627 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21499.306801 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21499.306801 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20746.357147 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20746.357147 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 308799.800000 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 308799.800000 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 41524.236940 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 41524.236940 # average ReadExReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 30469.401986 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 30469.401986 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 31731.645204 # average ReadSharedReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 31731.645204 # average ReadSharedReq miss latency +system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 50879.422802 # average InvalidateReq miss latency +system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 50879.422802 # average InvalidateReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 35810.112360 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 39034.655861 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 30469.401986 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 33660.088551 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 32729.262145 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 35810.112360 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 39034.655861 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 30469.401986 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33660.088551 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 32729.262145 # average overall miss latency system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2102,214 +2156,229 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 1053113 # number of writebacks -system.cpu1.l2cache.writebacks::total 1053113 # number of writebacks -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 432 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::total 432 # number of ReadReq MSHR hits -system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.data 1 # number of WriteInvalidateReq MSHR hits -system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total 1 # number of WriteInvalidateReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 7197 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 7197 # number of ReadExReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 7629 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 7629 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 7629 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 7629 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 9961 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 7958 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 532707 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 951813 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 1502439 # number of ReadReq MSHR misses +system.cpu1.l2cache.writebacks::writebacks 868662 # number of writebacks +system.cpu1.l2cache.writebacks::total 868662 # number of writebacks +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 5194 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 5194 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 348 # number of ReadSharedReq MSHR hits +system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 348 # number of ReadSharedReq MSHR hits +system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 2 # number of InvalidateReq MSHR hits +system.cpu1.l2cache.InvalidateReq_mshr_hits::total 2 # number of InvalidateReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 5542 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 5542 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 5542 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 5542 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 9790 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8267 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 18057 # number of ReadReq MSHR misses system.cpu1.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses system.cpu1.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 707306 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 707306 # number of HardPFReq MSHR misses -system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.data 267700 # number of WriteInvalidateReq MSHR misses -system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total 267700 # number of WriteInvalidateReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 120750 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 120750 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 167539 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 167539 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 85466 # number of CleanEvict MSHR misses +system.cpu1.l2cache.CleanEvict_mshr_misses::total 85466 # number of CleanEvict MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 604026 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 604026 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 120456 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 120456 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 156608 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 156608 # number of SCUpgradeReq MSHR misses system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 5 # number of SCUpgradeFailReq MSHR misses system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 220506 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 220506 # number of ReadExReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 9961 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 7958 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 532707 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1172319 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 1722945 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 9961 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 7958 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 532707 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1172319 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 707306 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 2430251 # number of overall MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 200917 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 200917 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 467514 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 467514 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 840168 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 840168 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 229971 # number of InvalidateReq MSHR misses +system.cpu1.l2cache.InvalidateReq_mshr_misses::total 229971 # number of InvalidateReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 9790 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8267 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 467514 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1041085 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 1526656 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 9790 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8267 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 467514 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1041085 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 604026 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 2130682 # number of overall MSHR misses system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 21725 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 21835 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 20113 # number of WriteReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 20113 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 11055 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 11165 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 11308 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 11308 # number of WriteReq MSHR uncacheable system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 41838 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 41948 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 329233523 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 306561274 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 12577785182 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 24989286886 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 38202866865 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 35407537019 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 35407537019 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 9092223824 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 9092223824 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2448079564 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2448079564 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2512705540 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2512705540 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1507000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1507000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 7591763498 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 7591763498 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 329233523 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 306561274 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 12577785182 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 32581050384 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 45794630363 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 329233523 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 306561274 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 12577785182 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 32581050384 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 35407537019 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 81202167382 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9241250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3553660750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3562902000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 3314826000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 3314826000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9241250 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 6868486750 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 6877728000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.038498 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.053189 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.108873 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.249027 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.164680 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 22363 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 22473 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 291841000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 273097500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 564938500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 27533861444 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 27533861444 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2500623000 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2500623000 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2389472000 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2389472000 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1321999 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1321999 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 6820721500 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 6820721500 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 11439788000 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 11439788000 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 21593362000 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 21593362000 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 10321018000 # number of InvalidateReq MSHR miss cycles +system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 10321018000 # number of InvalidateReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 291841000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 273097500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 11439788000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 28414083500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 40418810000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 291841000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 273097500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 11439788000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 28414083500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 27533861444 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 67952671444 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8836500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 1823134500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 1831971000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1942414500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1942414500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8836500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3765549000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3774385500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.043047 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.054468 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.047618 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for Writeback accesses system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000000 # mshr miss rate for Writeback accesses +system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.539975 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.539975 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.620708 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.620708 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.826292 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.826292 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.662461 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.662461 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.841811 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.841811 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.186673 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.186673 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.038498 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.053189 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.108873 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.234306 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.167201 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.038498 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.053189 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.108873 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.234306 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.189475 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.189475 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.092349 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.092349 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.244402 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.244402 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.483333 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.483333 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.043047 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.054468 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.092349 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.231453 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.153592 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.043047 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.054468 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.092349 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.231453 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.235840 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 33052.256099 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 38522.401860 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23611.075473 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 26254.408047 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25427.233229 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50059.715341 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 50059.715341 # average HardPFReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 33964.227957 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 33964.227957 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20273.950841 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20273.950841 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14997.735095 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14997.735095 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 301400 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 301400 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34428.829592 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34428.829592 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 33052.256099 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 38522.401860 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 23611.075473 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27791.966507 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26579.275811 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 33052.256099 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 38522.401860 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 23611.075473 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27791.966507 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50059.715341 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33413.078477 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 84011.363636 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163574.718067 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163173.895123 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 164810.122806 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 164810.122806 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 84011.363636 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 164168.620632 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 163958.424716 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.214361 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 29810.112360 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 33034.655861 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 31286.398627 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45583.901097 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 45583.901097 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20759.638374 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20759.638374 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15257.662444 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15257.662444 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 264399.800000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 264399.800000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33947.956121 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33947.956121 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 24469.401986 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 24469.401986 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 25701.243085 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 25701.243085 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 44879.650043 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 44879.650043 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 29810.112360 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 33034.655861 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 24469.401986 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27292.760437 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26475.388038 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 29810.112360 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 33034.655861 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 24469.401986 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27292.760437 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45583.901097 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 31892.451076 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 80331.818182 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164914.925373 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164081.594268 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 171773.478953 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 171773.478953 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 80331.818182 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 168382.998703 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 167952.009078 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 11407818 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 9339972 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 38146 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 20113 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 3550271 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 1013669 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1157980 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 495764 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 395206 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 367201 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 457834 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 51 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 86 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1341582 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1187599 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 9786048 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15579584 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 330806 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 594855 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 26291293 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 313146936 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 585201818 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1196936 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 2069904 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 901615594 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 4634762 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 19271924 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 1.253755 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.435159 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 559173 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 9082723 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 37997 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 11308 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 6546630 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 9047745 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 872762 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 38 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 399618 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 347237 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 434764 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 64 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 96 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1786739 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1070352 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5062459 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 5562594 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 582530 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 475802 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 15186455 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15778247 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 332058 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 524938 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 31821698 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 323997816 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 497415771 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1214224 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1819400 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 824447211 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 10229580 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 30806602 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 1.338828 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.473311 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 14381570 74.62% 74.62% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 4890354 25.38% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 20368466 66.12% 66.12% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 10438136 33.88% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 19271924 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 11505600998 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 30806602 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 13598256460 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 168563993 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 189037985 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 7347478432 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 7593798500 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 8042476622 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7185863072 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 181503274 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 180280000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 336447522 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 297513000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40366 # Transaction distribution -system.iobus.trans_dist::ReadResp 40366 # Transaction distribution -system.iobus.trans_dist::WriteReq 136641 # Transaction distribution -system.iobus.trans_dist::WriteResp 29913 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47782 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 40323 # Transaction distribution +system.iobus.trans_dist::ReadResp 40323 # Transaction distribution +system.iobus.trans_dist::WriteReq 136623 # Transaction distribution +system.iobus.trans_dist::WriteResp 136623 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47688 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -2324,13 +2393,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122716 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231218 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231218 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122622 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231190 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231190 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354014 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47802 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353892 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47708 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2345,13 +2414,13 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155823 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338888 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155729 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338776 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338776 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496797 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36274000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496591 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36209000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2379,781 +2448,754 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 607607215 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 569692377 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92806000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92730000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 148515621 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147886000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 170500 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115613 # number of replacements -system.iocache.tags.tagsinuse 11.298152 # Cycle average of tags in use +system.iocache.tags.replacements 115590 # number of replacements +system.iocache.tags.tagsinuse 11.304878 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115629 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115606 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9179138787000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 7.392909 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 3.905243 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.462057 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.244078 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.706135 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9148728954000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 7.397645 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 3.907233 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.462353 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.244202 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.706555 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040838 # Number of tag accesses -system.iocache.tags.data_accesses 1040838 # Number of data accesses +system.iocache.tags.tag_accesses 1040712 # Number of tag accesses +system.iocache.tags.data_accesses 1040712 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8881 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8918 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8867 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8904 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8881 # number of demand (read+write) misses -system.iocache.demand_misses::total 8921 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8867 # number of demand (read+write) misses +system.iocache.demand_misses::total 8907 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8881 # number of overall misses -system.iocache.overall_misses::total 8921 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5195500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1629816861 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1635012361 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8867 # number of overall misses +system.iocache.overall_misses::total 8907 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5195000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1652925028 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1658120028 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19901379733 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 19901379733 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5564500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1629816861 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1635381361 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5564500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1629816861 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1635381361 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12636024349 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12636024349 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5564000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1652925028 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1658489028 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5564000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1652925028 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1658489028 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8881 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8918 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8867 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8904 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8881 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8921 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8867 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8907 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8881 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8921 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8867 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8907 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140418.918919 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 183517.268438 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 183338.457165 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 186413.107928 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 186221.925876 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186468.215773 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 186468.215773 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 183517.268438 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 183318.166237 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 183517.268438 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 183318.166237 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 110961 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118394.651347 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118394.651347 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139100 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 186413.107928 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 186200.631863 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139100 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 186413.107928 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 186200.631863 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 32852 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 16203 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3487 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.848176 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.421279 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106702 # number of writebacks -system.iocache.writebacks::total 106702 # number of writebacks +system.iocache.writebacks::writebacks 106693 # number of writebacks +system.iocache.writebacks::total 106693 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8881 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8918 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8867 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8904 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106728 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 106728 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8881 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8921 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8867 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8907 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8881 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8921 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3270500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1166890035 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1170160535 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 213000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 213000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14351455801 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14351455801 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3483500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1166890035 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1170373535 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3483500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1166890035 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1170373535 # number of overall MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8867 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8907 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3345000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1209575028 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1212920028 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7299624349 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7299624349 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3564000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1209575028 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1213139028 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3564000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1209575028 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1213139028 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 88391.891892 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 131391.739106 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 131213.336510 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 71000 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 71000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134467.579276 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134467.579276 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 131391.739106 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 131193.087658 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 131391.739106 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 131193.087658 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136413.107928 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 136221.925876 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68394.651347 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68394.651347 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 136413.107928 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 136200.631863 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 136413.107928 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 136200.631863 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1448041 # number of replacements -system.l2c.tags.tagsinuse 64131.287175 # Cycle average of tags in use -system.l2c.tags.total_refs 4245095 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1507106 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.816720 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 11172879000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 19347.050639 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 116.894544 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 154.865125 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3200.431152 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 7856.746302 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 9704.320174 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 227.109782 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 297.906768 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3324.337079 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 8639.334854 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 11262.290757 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.295213 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001784 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.002363 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.048835 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.119884 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.148076 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.003465 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.004546 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.050725 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.131826 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.171849 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.978566 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 10716 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 318 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 48031 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 38 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 439 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 10237 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 318 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1326 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4887 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 41702 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.163513 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.004852 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.732895 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 58352089 # Number of tag accesses -system.l2c.tags.data_accesses 58352089 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 5485 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4305 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 465111 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 536784 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 265347 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5257 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 3875 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 485070 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 556488 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 285641 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2613363 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 2374848 # number of Writeback hits -system.l2c.Writeback_hits::total 2374848 # number of Writeback hits -system.l2c.WriteInvalidateReq_hits::cpu0.data 123464 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::cpu1.data 121626 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::total 245090 # number of WriteInvalidateReq hits -system.l2c.UpgradeReq_hits::cpu0.data 24332 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 31013 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 55345 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 5518 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 6203 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 11721 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 54595 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 49708 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 104303 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 5485 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4305 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 465111 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 591379 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 265347 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5257 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 3875 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 485070 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 606196 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 285641 # number of demand (read+write) hits -system.l2c.demand_hits::total 2717666 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 5485 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4305 # number of overall hits -system.l2c.overall_hits::cpu0.inst 465111 # number of overall hits -system.l2c.overall_hits::cpu0.data 591379 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 265347 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5257 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 3875 # number of overall hits -system.l2c.overall_hits::cpu1.inst 485070 # number of overall hits -system.l2c.overall_hits::cpu1.data 606196 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 285641 # number of overall hits -system.l2c.overall_hits::total 2717666 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 1889 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1930 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 50597 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 131294 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 216525 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 2185 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 2247 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 47637 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 122248 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 240093 # number of ReadReq misses -system.l2c.ReadReq_misses::total 816645 # number of ReadReq misses -system.l2c.WriteInvalidateReq_misses::cpu0.data 431801 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::cpu1.data 136823 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::total 568624 # number of WriteInvalidateReq misses -system.l2c.UpgradeReq_misses::cpu0.data 44180 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 43907 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 88087 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 9646 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 11002 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 20648 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 78703 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 53921 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 132624 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 1889 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1930 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 50597 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 209997 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 216525 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 2185 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 2247 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 47637 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 176169 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 240093 # number of demand (read+write) misses -system.l2c.demand_misses::total 949269 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 1889 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1930 # number of overall misses -system.l2c.overall_misses::cpu0.inst 50597 # number of overall misses -system.l2c.overall_misses::cpu0.data 209997 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 216525 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 2185 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 2247 # number of overall misses -system.l2c.overall_misses::cpu1.inst 47637 # number of overall misses -system.l2c.overall_misses::cpu1.data 176169 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 240093 # number of overall misses -system.l2c.overall_misses::total 949269 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 170785750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 176668500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 4301026862 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 11907133634 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 27854403488 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 192678771 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 202084771 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 4020493910 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 11059922872 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 30832642419 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 90717840977 # number of ReadReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::cpu0.data 51822854 # number of WriteInvalidateReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 41218687 # number of WriteInvalidateReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::total 93041541 # number of WriteInvalidateReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 233428095 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 271641854 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 505069949 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 51474876 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 56093222 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 107568098 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 6900295884 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 4492674608 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 11392970492 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 170785750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 176668500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 4301026862 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 18807429518 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 27854403488 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 192678771 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 202084771 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 4020493910 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 15552597480 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 30832642419 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 102110811469 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 170785750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 176668500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 4301026862 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 18807429518 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 27854403488 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 192678771 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 202084771 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 4020493910 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 15552597480 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 30832642419 # number of overall miss cycles -system.l2c.overall_miss_latency::total 102110811469 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 7374 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 6235 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 515708 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 668078 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 481872 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 7442 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 6122 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 532707 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 678736 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 525734 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 3430008 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 2374848 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 2374848 # number of Writeback accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu0.data 555265 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu1.data 258449 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::total 813714 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 68512 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 74920 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 143432 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 15164 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 17205 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 32369 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 133298 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 103629 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 236927 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 7374 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 6235 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 515708 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 801376 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 481872 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 7442 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 6122 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 532707 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 782365 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 525734 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 3666935 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 7374 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 6235 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 515708 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 801376 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 481872 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 7442 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 6122 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 532707 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 782365 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 525734 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 3666935 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.256170 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.309543 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.098112 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.196525 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.449341 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.293604 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.367037 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.089424 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.180111 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.456682 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.238088 # miss rate for ReadReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.777649 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.529400 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::total 0.698801 # miss rate for WriteInvalidateReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.644851 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.586052 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.614138 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.636112 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.639465 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.637894 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.590429 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.520327 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.559767 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.256170 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.309543 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.098112 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.262046 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.449341 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.293604 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.367037 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.089424 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.225175 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.456682 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.258873 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.256170 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.309543 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.098112 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.262046 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.449341 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.293604 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.367037 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.089424 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.225175 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.456682 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.258873 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 90410.667020 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 91538.082902 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 85005.570726 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 90690.615215 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 128642.897993 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 88182.503890 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 89935.367601 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 84398.553855 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 90471.196846 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 128419.580825 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 111086.017764 # average ReadReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data 120.015595 # average WriteInvalidateReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data 301.255542 # average WriteInvalidateReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::total 163.625772 # average WriteInvalidateReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 5283.569375 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6186.755050 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 5733.762632 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5336.396019 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5098.456826 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 5209.613425 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 87675.131621 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83319.571373 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 85904.289510 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 90410.667020 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 91538.082902 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 85005.570726 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 89560.467616 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 128642.897993 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 88182.503890 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89935.367601 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 84398.553855 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 88282.260103 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 128419.580825 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 107567.835323 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 90410.667020 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 91538.082902 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 85005.570726 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 89560.467616 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 128642.897993 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 88182.503890 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89935.367601 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 84398.553855 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 88282.260103 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 128419.580825 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 107567.835323 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 328 # number of cycles access was blocked +system.l2c.tags.replacements 1309168 # number of replacements +system.l2c.tags.tagsinuse 63754.864014 # Cycle average of tags in use +system.l2c.tags.total_refs 4916621 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1368931 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 3.591577 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 19091.859701 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 105.912894 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 155.127533 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3615.637235 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 7840.243629 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 8325.501182 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 220.931545 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 308.618632 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3602.401841 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 8895.404165 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 11593.225658 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.291319 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001616 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.002367 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.055170 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.119633 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.127037 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.003371 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.004709 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.054968 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.135733 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.176899 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.972822 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 11100 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 278 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 48385 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 212 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 379 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 10509 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 277 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 85 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1364 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4701 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 42219 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.169373 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.004242 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.738297 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 62372649 # Number of tag accesses +system.l2c.tags.data_accesses 62372649 # Number of data accesses +system.l2c.Writeback_hits::writebacks 2239360 # number of Writeback hits +system.l2c.Writeback_hits::total 2239360 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 30980 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 24512 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 55492 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 6081 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 5027 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 11108 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 167543 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 144880 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 312423 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 5175 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4181 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 498211 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 558223 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 295485 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 4952 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4009 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 423075 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 457635 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 236791 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 2487737 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 5175 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4181 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 498211 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 725766 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 295485 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 4952 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 4009 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 423075 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 602515 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 236791 # number of demand (read+write) hits +system.l2c.demand_hits::total 2800160 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 5175 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 4181 # number of overall hits +system.l2c.overall_hits::cpu0.inst 498211 # number of overall hits +system.l2c.overall_hits::cpu0.data 725766 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 295485 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 4952 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 4009 # number of overall hits +system.l2c.overall_hits::cpu1.inst 423075 # number of overall hits +system.l2c.overall_hits::cpu1.data 602515 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 236791 # number of overall hits +system.l2c.overall_hits::total 2800160 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 43560 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 41893 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 85453 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 11005 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 9001 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 20006 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 491114 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 139826 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 630940 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1207 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1226 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.inst 43736 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 119131 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 198612 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1716 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1777 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 44439 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 101598 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 196208 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 709650 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.dtb.walker 1207 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 1226 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 43736 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 610245 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 198612 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 1716 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 1777 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 44439 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 241424 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 196208 # number of demand (read+write) misses +system.l2c.demand_misses::total 1340590 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 1207 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 1226 # number of overall misses +system.l2c.overall_misses::cpu0.inst 43736 # number of overall misses +system.l2c.overall_misses::cpu0.data 610245 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 198612 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 1716 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 1777 # number of overall misses +system.l2c.overall_misses::cpu1.inst 44439 # number of overall misses +system.l2c.overall_misses::cpu1.data 241424 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 196208 # number of overall misses +system.l2c.overall_misses::total 1340590 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0.data 242100000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 225831000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 467931000 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 53618000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 45210000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 98828000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 41035187500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 11309941500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 52345129000 # number of ReadExReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 108698500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 110530000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.inst 3653235500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 10597934000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 23810682130 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 150819000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 156924500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.inst 3723508500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 8959752500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 23335976587 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 74608061217 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 108698500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 110530000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 3653235500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 51633121500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 23810682130 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 150819000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 156924500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 3723508500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 20269694000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 23335976587 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 126953190217 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 108698500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 110530000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 3653235500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 51633121500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 23810682130 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 150819000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 156924500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 3723508500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 20269694000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 23335976587 # number of overall miss cycles +system.l2c.overall_miss_latency::total 126953190217 # number of overall miss cycles +system.l2c.Writeback_accesses::writebacks 2239360 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 2239360 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 74540 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 66405 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 140945 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 17086 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 14028 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 31114 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 658657 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 284706 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 943363 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 6382 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 5407 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.inst 541947 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 677354 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 494097 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 6668 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 5786 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.inst 467514 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 559233 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 432999 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 3197387 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 6382 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 5407 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 541947 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1336011 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 494097 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 6668 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 5786 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 467514 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 843939 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 432999 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 4140750 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 6382 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 5407 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 541947 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1336011 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 494097 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 6668 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 5786 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 467514 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 843939 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 432999 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 4140750 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.584384 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.630871 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.606286 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.644095 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.641645 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.642990 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.745629 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.491124 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.668820 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.189126 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.226743 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.080702 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.175877 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.401970 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.257349 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.307121 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.095054 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.181674 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.453137 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.221947 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.189126 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.226743 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.080702 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.456766 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.401970 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.257349 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.307121 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.095054 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.286068 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.453137 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.323755 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.189126 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.226743 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.080702 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.456766 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.401970 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.257349 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.307121 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.095054 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.286068 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.453137 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.323755 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 5557.851240 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5390.661924 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 5475.887330 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4872.149023 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5022.775247 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 4939.918025 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 83555.320150 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 80885.825955 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 82963.719213 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 90056.752278 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 90154.975530 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 83529.255076 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 88960.337779 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 119885.415433 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 87889.860140 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 88308.666292 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 83789.205428 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 88188.276344 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 118934.888419 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 105133.602786 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 90056.752278 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 90154.975530 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 83529.255076 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 84610.478578 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 119885.415433 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 87889.860140 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 88308.666292 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 83789.205428 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 83958.902180 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 118934.888419 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 94699.490685 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 90056.752278 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 90154.975530 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 83529.255076 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 84610.478578 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 119885.415433 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 87889.860140 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 88308.666292 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 83789.205428 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 83958.902180 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 118934.888419 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 94699.490685 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 67 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 14 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 1 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 23.428571 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 67 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 1121159 # number of writebacks -system.l2c.writebacks::total 1121159 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 120 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.data 25 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 120 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.data 30 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 296 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 120 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 25 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 120 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 30 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 296 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 120 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 25 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 120 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 30 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 296 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1889 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1930 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 50477 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 131269 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 216525 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 2184 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 2247 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 47517 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 122218 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 240093 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 816349 # number of ReadReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::cpu0.data 431801 # number of WriteInvalidateReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data 136823 # number of WriteInvalidateReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::total 568624 # number of WriteInvalidateReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 44180 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 43907 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 88087 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 9646 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 11002 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 20648 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 78703 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 53921 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 132624 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 1889 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 1930 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 50477 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 209972 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 216525 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 2184 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 2247 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 47517 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 176139 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 240093 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 948973 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 1889 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 1930 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 50477 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 209972 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 216525 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 2184 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 2247 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 47517 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 176139 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 240093 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 948973 # number of overall MSHR misses +system.l2c.writebacks::writebacks 1031074 # number of writebacks +system.l2c.writebacks::total 1031074 # number of writebacks +system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 126 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu0.data 17 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 108 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.data 18 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 269 # number of ReadSharedReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 126 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 17 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 108 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 18 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 269 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 126 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 17 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 108 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 18 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 269 # number of overall MSHR hits +system.l2c.CleanEvict_mshr_misses::writebacks 39567 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 39567 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 43560 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 41893 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 85453 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 11005 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 9001 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 20006 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 491114 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 139826 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 630940 # number of ReadExReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1207 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1226 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 43610 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 119114 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 198612 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1716 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1777 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 44331 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 101580 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 196208 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 709381 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 1207 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 1226 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 43610 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 610228 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 198612 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 1716 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 1777 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 44331 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 241406 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 196208 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 1340321 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 1207 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 1226 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 43610 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 610228 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 198612 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 1716 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 1777 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 44331 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 241406 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 196208 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 1340321 # number of overall MSHR misses system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 16584 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 27090 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 21723 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 81542 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 18033 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 20113 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 38146 # number of WriteReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 11053 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 81378 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 26689 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 11308 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 37997 # number of WriteReq MSHR uncacheable system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 34617 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 53779 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 41836 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 119688 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 146937750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 152273500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 3658828888 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 10259837116 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 25193281260 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 165099729 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 173733729 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 3415229090 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 9525126628 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 27878676483 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 80569024173 # number of ReadReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data 13996588148 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 4310102313 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::total 18306690461 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 786063539 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 780665261 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 1566728800 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 172133111 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 196209961 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 368343072 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5916837616 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3817995892 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 9734833508 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 146937750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 152273500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 3658828888 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 16176674732 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 25193281260 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 165099729 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 173733729 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 3415229090 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 13343122520 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 27878676483 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 90303857681 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 146937750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 152273500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 3658828888 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 16176674732 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 25193281260 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 165099729 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 173733729 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 3415229090 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 13343122520 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 27878676483 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 90303857681 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 2605759500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2243809000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7049250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3129187250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 7985805000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2322501000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2942063000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 5264564000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2605759500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4566310000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7049250 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 6071250250 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 13250369000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.256170 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.309543 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.097879 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.196488 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.449341 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.293469 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.367037 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.089199 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.180067 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.456682 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.238002 # mshr miss rate for ReadReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.777649 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.529400 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.698801 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.644851 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.586052 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.614138 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.636112 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.639465 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.637894 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.590429 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.520327 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.559767 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.256170 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.309543 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.097879 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.262014 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.449341 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.293469 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.367037 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.089199 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.225137 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.456682 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.258792 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.256170 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.309543 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.097879 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.262014 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.449341 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.293469 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.367037 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.089199 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.225137 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.456682 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.258792 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 77785.997882 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 78898.186528 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 72485.070190 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 78158.873123 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116352.759543 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 75595.114011 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 77318.081442 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71873.836522 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 77935.546548 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 116116.157002 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 98694.338050 # average ReadReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 32414.441254 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 31501.299584 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 32194.719992 # average WriteInvalidateReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17792.293775 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17779.972692 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17786.152327 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17845.024984 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17834.026632 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17839.164665 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 75179.314842 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 70807.215964 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 73401.748613 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 77785.997882 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78898.186528 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72485.070190 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77042.056712 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116352.759543 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 75595.114011 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 77318.081442 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71873.836522 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75753.368192 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 116116.157002 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 95159.564794 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 77785.997882 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78898.186528 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72485.070190 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77042.056712 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116352.759543 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 75595.114011 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 77318.081442 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71873.836522 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75753.368192 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 116116.157002 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 95159.564794 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60423.408696 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 135299.626146 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 64084.090909 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 144049.498228 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 97934.867921 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 128791.715189 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 146276.686720 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 138010.905468 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60423.408696 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 131909.466447 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 64084.090909 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 145120.237355 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 110707.581378 # average overall mshr uncacheable latency +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 22361 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 119375 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 904276500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 870415500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 1774692000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 228388000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 186718499 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 415106499 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 36124047500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 9911681500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 46035729000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 96628500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 98270000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 3207900500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 9405362000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 21824562130 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 133659000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 139154500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 3272125000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 7942788500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 21373896587 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 67494346717 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 96628500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 98270000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 3207900500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 45529409500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 21824562130 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 133659000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 139154500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 3272125000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 17854470000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 21373896587 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 113530075717 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 96628500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 98270000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 3207900500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 45529409500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 21824562130 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 133659000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 139154500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 3272125000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 17854470000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 21373896587 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 113530075717 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 2678027000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3881489500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6856500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1624141500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 8190514500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3646235000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1750167000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 5396402000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2678027000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 7527724500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6856500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3374308500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 13586916500 # number of overall MSHR uncacheable cycles +system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.584384 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.630871 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.606286 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.644095 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.641645 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.642990 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.745629 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.491124 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.668820 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.189126 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.226743 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.080469 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.175852 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.401970 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.257349 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.307121 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.094823 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.181642 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.453137 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.221863 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.189126 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.226743 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.080469 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.456754 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.401970 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.257349 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.307121 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.094823 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.286047 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.453137 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.323690 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.189126 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.226743 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.080469 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.456754 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.401970 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.257349 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.307121 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.094823 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.286047 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.453137 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.323690 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20759.331956 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20777.110734 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20768.047933 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20753.112222 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20744.194978 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20749.100220 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 73555.320150 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 70885.825955 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 72963.719213 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 80056.752278 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 80154.975530 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 73558.828250 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78961.012140 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109885.415433 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 77889.860140 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 78308.666292 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 73811.215628 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 78192.444379 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108934.888419 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 95145.410882 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 80056.752278 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80154.975530 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73558.828250 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 74610.489030 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109885.415433 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 77889.860140 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 78308.666292 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73811.215628 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73960.340671 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108934.888419 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 84703.646154 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 80056.752278 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80154.975530 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73558.828250 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 74610.489030 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109885.415433 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77889.860140 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 78308.666292 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73811.215628 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73960.340671 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108934.888419 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 84703.646154 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62099.176812 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 143281.266150 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 62331.818182 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146941.237673 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 100647.773354 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 136619.393758 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 154772.461974 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 142021.791194 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62099.176812 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 139975.166887 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 62331.818182 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 150901.502616 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 113817.101571 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 906809 # Transaction distribution -system.membus.trans_dist::ReadResp 906809 # Transaction distribution -system.membus.trans_dist::WriteReq 38146 # Transaction distribution -system.membus.trans_dist::WriteResp 38146 # Transaction distribution -system.membus.trans_dist::Writeback 1227861 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 672387 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 672387 # Transaction distribution -system.membus.trans_dist::UpgradeReq 370275 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 320224 # Transaction distribution -system.membus.trans_dist::UpgradeResp 115346 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 24 # Transaction distribution -system.membus.trans_dist::ReadExReq 145002 # Transaction distribution -system.membus.trans_dist::ReadExResp 128981 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122716 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 81378 # Transaction distribution +system.membus.trans_dist::ReadResp 799663 # Transaction distribution +system.membus.trans_dist::WriteReq 37997 # Transaction distribution +system.membus.trans_dist::WriteResp 37997 # Transaction distribution +system.membus.trans_dist::Writeback 1137767 # Transaction distribution +system.membus.trans_dist::CleanEvict 200903 # Transaction distribution +system.membus.trans_dist::UpgradeReq 374437 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 306668 # Transaction distribution +system.membus.trans_dist::UpgradeResp 111797 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution +system.membus.trans_dist::ReadExReq 646745 # Transaction distribution +system.membus.trans_dist::ReadExResp 624605 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 718285 # Transaction distribution +system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution +system.membus.trans_dist::InvalidateResp 106728 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122622 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24970 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5055890 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5203668 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335590 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 335590 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5539258 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155823 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24438 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4799197 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4946349 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342551 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 342551 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5288900 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155729 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49940 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 168605292 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 168811259 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14076224 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14076224 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 182887483 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 594337 # Total snoops (count) -system.membus.snoop_fanout::samples 3681134 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 48876 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 151511532 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 151716341 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7266432 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7266432 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 158982773 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 594252 # Total snoops (count) +system.membus.snoop_fanout::samples 3613210 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3681134 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3613210 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3681134 # Request fanout histogram -system.membus.reqLayer0.occupancy 100790999 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3613210 # Request fanout histogram +system.membus.reqLayer0.occupancy 101221000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 55000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 21573500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 21240500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 11112792344 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 7773596350 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 5991933811 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 7468178118 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 151912879 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 229090524 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -3197,45 +3239,46 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 4327568 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4320333 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38146 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38146 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 2374848 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 920665 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 813714 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 419012 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 331945 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 750957 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 86 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 86 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 292509 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 292509 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7096014 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6270717 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 13366731 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 236480377 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 202778754 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 439259131 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1555479 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 8704899 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.013311 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.114603 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 81380 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4075375 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 37997 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 37997 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 3377178 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1228761 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 423594 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 317776 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 741370 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 96 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 96 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1071890 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1071890 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 4001246 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 106728 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7774731 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5765311 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 13540042 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 240674354 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 168156931 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 408831285 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 3034988 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 11680683 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.131880 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.338360 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 8589027 98.67% 98.67% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 115872 1.33% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 10140239 86.81% 86.81% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 1540444 13.19% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 8704899 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 7795939791 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 11680683 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 7606203373 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2526000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2481000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3978610795 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4538781481 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3846379763 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3532073491 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt index 7790849b2..61b2291b6 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt @@ -1,138 +1,138 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.824462 # Number of seconds simulated -sim_ticks 51824462100500 # Number of ticks simulated -final_tick 51824462100500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.832459 # Number of seconds simulated +sim_ticks 51832458543500 # Number of ticks simulated +final_tick 51832458543500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 684695 # Simulator instruction rate (inst/s) -host_op_rate 804548 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39714246392 # Simulator tick rate (ticks/s) -host_mem_usage 713112 # Number of bytes of host memory used -host_seconds 1304.93 # Real time elapsed on the host -sim_insts 893481288 # Number of instructions simulated -sim_ops 1049881338 # Number of ops (including micro ops) simulated +host_inst_rate 757890 # Simulator instruction rate (inst/s) +host_op_rate 890582 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44493723118 # Simulator tick rate (ticks/s) +host_mem_usage 717728 # Number of bytes of host memory used +host_seconds 1164.94 # Real time elapsed on the host +sim_insts 882895003 # Number of instructions simulated +sim_ops 1037473525 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 266048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 259456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5261620 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 50351624 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 398272 # Number of bytes read from this memory -system.physmem.bytes_read::total 56537020 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5261620 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5261620 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 77705792 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 255168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 250176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5270964 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 81048392 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 390144 # Number of bytes read from this memory +system.physmem.bytes_read::total 87214844 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5270964 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5270964 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 75813760 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 77726372 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 4157 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 4054 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 122620 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 786757 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6223 # Number of read requests responded to by this memory -system.physmem.num_reads::total 923811 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1214153 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 75834340 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 3987 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3909 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 122766 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1266394 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6096 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1403152 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1184590 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1216726 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 5134 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 5006 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 101528 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 971580 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7685 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1090933 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 101528 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 101528 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1499404 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1187163 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 4923 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 4827 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 101692 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1563661 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7527 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1682630 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 101692 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 101692 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1462670 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 397 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1499801 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1499404 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 5134 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 5006 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 101528 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 971977 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7685 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2590734 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 923811 # Number of read requests accepted -system.physmem.writeReqs 1833124 # Number of write requests accepted -system.physmem.readBursts 923811 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1833124 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 59092736 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 31168 # Total number of bytes read from write queue -system.physmem.bytesWritten 114062016 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 56537020 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 117175844 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 487 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 50880 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 36215 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 57129 # Per bank write bursts -system.physmem.perBankRdBursts::1 60965 # Per bank write bursts -system.physmem.perBankRdBursts::2 52485 # Per bank write bursts -system.physmem.perBankRdBursts::3 50413 # Per bank write bursts -system.physmem.perBankRdBursts::4 54002 # Per bank write bursts -system.physmem.perBankRdBursts::5 59718 # Per bank write bursts -system.physmem.perBankRdBursts::6 51713 # Per bank write bursts -system.physmem.perBankRdBursts::7 51669 # Per bank write bursts -system.physmem.perBankRdBursts::8 50247 # Per bank write bursts -system.physmem.perBankRdBursts::9 101235 # Per bank write bursts -system.physmem.perBankRdBursts::10 59848 # Per bank write bursts -system.physmem.perBankRdBursts::11 58323 # Per bank write bursts -system.physmem.perBankRdBursts::12 55369 # Per bank write bursts -system.physmem.perBankRdBursts::13 55988 # Per bank write bursts -system.physmem.perBankRdBursts::14 51743 # Per bank write bursts -system.physmem.perBankRdBursts::15 52477 # Per bank write bursts -system.physmem.perBankWrBursts::0 110630 # Per bank write bursts -system.physmem.perBankWrBursts::1 112240 # Per bank write bursts -system.physmem.perBankWrBursts::2 108805 # Per bank write bursts -system.physmem.perBankWrBursts::3 108103 # Per bank write bursts -system.physmem.perBankWrBursts::4 111102 # Per bank write bursts -system.physmem.perBankWrBursts::5 113339 # Per bank write bursts -system.physmem.perBankWrBursts::6 105567 # Per bank write bursts -system.physmem.perBankWrBursts::7 107723 # Per bank write bursts -system.physmem.perBankWrBursts::8 108849 # Per bank write bursts -system.physmem.perBankWrBursts::9 115780 # Per bank write bursts -system.physmem.perBankWrBursts::10 115663 # Per bank write bursts -system.physmem.perBankWrBursts::11 113049 # Per bank write bursts -system.physmem.perBankWrBursts::12 112494 # Per bank write bursts -system.physmem.perBankWrBursts::13 116984 # Per bank write bursts -system.physmem.perBankWrBursts::14 111502 # Per bank write bursts -system.physmem.perBankWrBursts::15 110389 # Per bank write bursts +system.physmem.bw_write::total 1463067 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1462670 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 4923 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 4827 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 101692 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1564058 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7527 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3145697 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1403152 # Number of read requests accepted +system.physmem.writeReqs 1187163 # Number of write requests accepted +system.physmem.readBursts 1403152 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1187163 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 89743360 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 58368 # Total number of bytes read from write queue +system.physmem.bytesWritten 75832768 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 87214844 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 75834340 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 912 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2250 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 142509 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 84707 # Per bank write bursts +system.physmem.perBankRdBursts::1 87220 # Per bank write bursts +system.physmem.perBankRdBursts::2 81347 # Per bank write bursts +system.physmem.perBankRdBursts::3 82774 # Per bank write bursts +system.physmem.perBankRdBursts::4 86841 # Per bank write bursts +system.physmem.perBankRdBursts::5 98270 # Per bank write bursts +system.physmem.perBankRdBursts::6 81495 # Per bank write bursts +system.physmem.perBankRdBursts::7 83122 # Per bank write bursts +system.physmem.perBankRdBursts::8 79285 # Per bank write bursts +system.physmem.perBankRdBursts::9 129613 # Per bank write bursts +system.physmem.perBankRdBursts::10 85444 # Per bank write bursts +system.physmem.perBankRdBursts::11 88159 # Per bank write bursts +system.physmem.perBankRdBursts::12 83519 # Per bank write bursts +system.physmem.perBankRdBursts::13 84779 # Per bank write bursts +system.physmem.perBankRdBursts::14 82284 # Per bank write bursts +system.physmem.perBankRdBursts::15 83381 # Per bank write bursts +system.physmem.perBankWrBursts::0 72521 # Per bank write bursts +system.physmem.perBankWrBursts::1 74576 # Per bank write bursts +system.physmem.perBankWrBursts::2 72526 # Per bank write bursts +system.physmem.perBankWrBursts::3 74694 # Per bank write bursts +system.physmem.perBankWrBursts::4 74615 # Per bank write bursts +system.physmem.perBankWrBursts::5 83452 # Per bank write bursts +system.physmem.perBankWrBursts::6 71356 # Per bank write bursts +system.physmem.perBankWrBursts::7 73404 # Per bank write bursts +system.physmem.perBankWrBursts::8 69434 # Per bank write bursts +system.physmem.perBankWrBursts::9 76014 # Per bank write bursts +system.physmem.perBankWrBursts::10 73389 # Per bank write bursts +system.physmem.perBankWrBursts::11 75855 # Per bank write bursts +system.physmem.perBankWrBursts::12 72723 # Per bank write bursts +system.physmem.perBankWrBursts::13 74909 # Per bank write bursts +system.physmem.perBankWrBursts::14 71861 # Per bank write bursts +system.physmem.perBankWrBursts::15 73558 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 145 # Number of times write queue was full causing retry -system.physmem.totGap 51824459475500 # Total gap between requests +system.physmem.numWrRetry 15 # Number of times write queue was full causing retry +system.physmem.totGap 51832455911500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43101 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 880695 # Read request sizes (log2) +system.physmem.readPktSize::6 1360036 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1830551 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 889155 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 28186 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 257 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 284 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 462 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 528 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 455 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 746 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 480 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1765 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 152 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 105 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 102 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 92 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 72 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 55 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1184590 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1369724 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 26989 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 402 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 311 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 465 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 443 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 479 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 493 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 784 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 854 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 363 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 161 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 142 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 120 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 110 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 91 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 88 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 68 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 47 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -159,165 +159,162 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 57524 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 60978 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 91825 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 117209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 106855 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 97040 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 98714 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 93369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 94185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 92986 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 93402 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 98737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 96397 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 94916 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 105152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 97025 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 94048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 92817 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 5441 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 5084 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 5738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 7709 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 7730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 6924 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 6738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 7452 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 5737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 5138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 4676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 5004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 4547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 3838 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 3903 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 3022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 2209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1452 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 643 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 513 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 524 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 510 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 329 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 603787 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 286.780656 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 164.845955 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 326.273004 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 251324 41.62% 41.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 149673 24.79% 66.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 51779 8.58% 74.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 28017 4.64% 79.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 19714 3.27% 82.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 13055 2.16% 85.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 9885 1.64% 86.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 8959 1.48% 88.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 71381 11.82% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 603787 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 89136 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 10.358104 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 107.922360 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 89134 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 89136 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 89136 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.994379 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.728374 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 17.051434 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 87330 97.97% 97.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 694 0.78% 98.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 23 0.03% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 47 0.05% 98.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 149 0.17% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 187 0.21% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 322 0.36% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 118 0.13% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 42 0.05% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 12 0.01% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 62 0.07% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 32 0.04% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 11 0.01% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 9 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 3 0.00% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 1 0.00% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 2 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 6 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 11 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 10 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 8 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 26 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 5 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::400-415 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::416-431 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::432-447 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::464-479 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 5 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 4 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::640-655 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::672-687 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::688-703 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::704-719 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 89136 # Writes before turning the bus around for reads -system.physmem.totQLat 12043609520 # Total ticks spent queuing -system.physmem.totMemAccLat 29355934520 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4616620000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13043.75 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 15525 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 18184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 68862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 70049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 70008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 69966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 69777 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 72690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 73075 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 75585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 74412 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 74484 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 71661 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 71703 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 72226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 69733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 69498 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 68867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 570 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 560 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 431 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 399 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 395 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 361 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 270 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 47 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 564142 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 293.500232 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 169.709934 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 326.462784 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 227896 40.40% 40.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 137874 24.44% 64.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 50148 8.89% 73.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 27962 4.96% 78.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 20021 3.55% 82.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 14110 2.50% 84.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 11549 2.05% 86.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 10920 1.94% 88.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 63662 11.28% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 564142 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 68197 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 20.561359 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 299.455370 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 68195 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::20480-24575 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::73728-77823 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 68197 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 68197 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.374474 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.924162 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 6.358180 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 65696 96.33% 96.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 133 0.20% 96.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 441 0.65% 97.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 195 0.29% 97.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 359 0.53% 97.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 498 0.73% 98.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 123 0.18% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 30 0.04% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 34 0.05% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 28 0.04% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 38 0.06% 99.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 22 0.03% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 434 0.64% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 35 0.05% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 41 0.06% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 27 0.04% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 6 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 4 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 4 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 26 0.04% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 5 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 5 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 68197 # Writes before turning the bus around for reads +system.physmem.totQLat 16916842552 # Total ticks spent queuing +system.physmem.totMemAccLat 43208842552 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 7011200000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12064.16 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31793.75 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.14 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.20 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.09 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.26 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30814.16 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.73 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.46 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.68 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.46 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.03 # Data bus utilization in percentage +system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.36 # Average write queue length when enqueuing -system.physmem.readRowHits 694872 # Number of row buffer hits during reads -system.physmem.writeRowHits 1406883 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.26 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.94 # Row buffer hit rate for writes -system.physmem.avgGap 18797853.22 # Average gap between requests -system.physmem.pageHitRate 77.68 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2251693080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1228602375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3417133200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5686258320 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3384921452640 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1307306510865 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29947912845000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34652724495480 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.655841 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49820369752426 # Time in different power states -system.physmem_0.memoryStateTime::REF 1730532440000 # Time in different power states +system.physmem.avgWrQLen 22.64 # Average write queue length when enqueuing +system.physmem.readRowHits 1132918 # Number of row buffer hits during reads +system.physmem.writeRowHits 890066 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.79 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.12 # Row buffer hit rate for writes +system.physmem.avgGap 20010097.58 # Average gap between requests +system.physmem.pageHitRate 78.19 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2149066080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1172605500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 5349013800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3869493120 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3385443743760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1308122393760 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29951995045500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34658101361520 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.656420 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49827055945457 # Time in different power states +system.physmem_0.memoryStateTime::REF 1730799460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 273552725074 # Time in different power states +system.physmem_0.memoryStateTime::ACT 274602731543 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2312936640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1262019000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3784755000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5862520800 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3384921452640 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1309001038785 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29946426417000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34653571139865 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.672178 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49817859630672 # Time in different power states -system.physmem_1.memoryStateTime::REF 1730532440000 # Time in different power states +system.physmem_1.actEnergy 2115847440 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1154480250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 5588419200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3808574640 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3385443743760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1306419956235 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29953488411750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34658019433275 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.654839 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49829529145116 # Time in different power states +system.physmem_1.memoryStateTime::REF 1730799460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 276069619328 # Time in different power states +system.physmem_1.memoryStateTime::ACT 272122791134 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory @@ -371,68 +368,76 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 211321 # Table walker walks requested -system.cpu.dtb.walker.walksLong 211321 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15784 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 163511 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 14 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 211307 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 0.170368 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 58.877055 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-2047 211305 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walks 207675 # Table walker walks requested +system.cpu.dtb.walker.walksLong 207675 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15981 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 160171 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 22 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 207653 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 0.182998 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 62.840123 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-2047 207651 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::22528-24575 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 211307 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 179309 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 23338.389317 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 19372.996771 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 15325.519359 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 177365 98.92% 98.92% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 1663 0.93% 99.84% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 114 0.06% 99.91% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 88 0.05% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 58 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 14 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 179309 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples -200578036 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean -2.729096 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 -747974796 372.91% 372.91% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::1 547396760 -272.91% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total -200578036 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 163512 91.20% 91.20% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 15784 8.80% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 179296 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 211321 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 207653 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 176174 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 24712.505818 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 21157.403643 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 15094.851220 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-32767 111064 63.04% 63.04% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::32768-65535 63199 35.87% 98.92% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-98303 999 0.57% 99.48% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::98304-131071 662 0.38% 99.86% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-163839 15 0.01% 99.87% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::163840-196607 88 0.05% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-229375 11 0.01% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::229376-262143 50 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-294911 52 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::294912-327679 13 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-360447 8 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::360448-393215 7 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-491519 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 176174 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples -781821628 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.029012 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.167839 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 -759139796 97.10% 97.10% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::1 -22681832 2.90% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total -781821628 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 160172 90.93% 90.93% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 15981 9.07% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 176153 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 207675 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 211321 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 179296 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 207675 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 176153 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 179296 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 390617 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 176153 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 383828 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 167775531 # DTB read hits -system.cpu.dtb.read_misses 155743 # DTB read misses -system.cpu.dtb.write_hits 152648275 # DTB write hits -system.cpu.dtb.write_misses 55578 # DTB write misses +system.cpu.dtb.read_hits 165829611 # DTB read hits +system.cpu.dtb.read_misses 153241 # DTB read misses +system.cpu.dtb.write_hits 150793131 # DTB write hits +system.cpu.dtb.write_misses 54434 # DTB write misses system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 42687 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 75520 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb_mva_asid 42000 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1055 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 75015 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 8371 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 8164 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 19881 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 167931274 # DTB read accesses -system.cpu.dtb.write_accesses 152703853 # DTB write accesses +system.cpu.dtb.perms_faults 19719 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 165982852 # DTB read accesses +system.cpu.dtb.write_accesses 150847565 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 320423806 # DTB hits -system.cpu.dtb.misses 211321 # DTB misses -system.cpu.dtb.accesses 320635127 # DTB accesses +system.cpu.dtb.hits 316622742 # DTB hits +system.cpu.dtb.misses 207675 # DTB misses +system.cpu.dtb.accesses 316830417 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -462,97 +467,91 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 122916 # Table walker walks requested -system.cpu.itb.walker.walksLong 122916 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1122 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 110644 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 122916 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 122916 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 122916 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 111766 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 26583.507059 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 22687.613632 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 18325.329143 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-32767 56090 50.19% 50.19% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::32768-65535 53429 47.80% 97.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-98303 753 0.67% 98.66% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::98304-131071 1184 1.06% 99.72% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-163839 19 0.02% 99.74% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::163840-196607 105 0.09% 99.83% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-229375 43 0.04% 99.87% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::229376-262143 54 0.05% 99.92% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-294911 30 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::294912-327679 11 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-360447 20 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::360448-393215 11 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-425983 8 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::425984-458751 2 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-491519 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::491520-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 111766 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples -853761296 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 -853761296 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total -853761296 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 110644 99.00% 99.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1122 1.00% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 111766 # Table walker page sizes translated +system.cpu.itb.walker.walks 122431 # Table walker walks requested +system.cpu.itb.walker.walksLong 122431 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1128 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 110257 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 122431 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 122431 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 122431 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 111385 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 28118.386677 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 24591.122191 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 17995.361080 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 109197 98.04% 98.04% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 1895 1.70% 99.74% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 129 0.12% 99.85% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 78 0.07% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 51 0.05% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 19 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 8 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 111385 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples -887504296 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 -887504296 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total -887504296 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 110257 98.99% 98.99% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1128 1.01% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 111385 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 122916 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 122916 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 122431 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 122431 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 111766 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 111766 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 234682 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 894030670 # ITB inst hits -system.cpu.itb.inst_misses 122916 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 111385 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 111385 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 233816 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 883439249 # ITB inst hits +system.cpu.itb.inst_misses 122431 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 42687 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 53866 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 42000 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1055 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 53485 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 894153586 # ITB inst accesses -system.cpu.itb.hits 894030670 # DTB hits -system.cpu.itb.misses 122916 # DTB misses -system.cpu.itb.accesses 894153586 # DTB accesses -system.cpu.numCycles 103648924201 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 883561680 # ITB inst accesses +system.cpu.itb.hits 883439249 # DTB hits +system.cpu.itb.misses 122431 # DTB misses +system.cpu.itb.accesses 883561680 # DTB accesses +system.cpu.numCycles 103664917087 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 893481288 # Number of instructions committed -system.cpu.committedOps 1049881338 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 963989017 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 895873 # Number of float alu accesses -system.cpu.num_func_calls 52999943 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 136446519 # number of instructions that are conditional controls -system.cpu.num_int_insts 963989017 # number of integer instructions -system.cpu.num_fp_insts 895873 # number of float instructions -system.cpu.num_int_register_reads 1405913792 # number of times the integer registers were read -system.cpu.num_int_register_writes 764688301 # number of times the integer registers were written -system.cpu.num_fp_register_reads 1443674 # number of times the floating registers were read -system.cpu.num_fp_register_writes 760516 # number of times the floating registers were written -system.cpu.num_cc_register_reads 234750393 # number of times the CC registers were read -system.cpu.num_cc_register_writes 234155899 # number of times the CC registers were written -system.cpu.num_mem_refs 320407593 # number of memory refs -system.cpu.num_load_insts 167768846 # Number of load instructions -system.cpu.num_store_insts 152638747 # Number of store instructions -system.cpu.num_idle_cycles 100474792122.552063 # Number of idle cycles -system.cpu.num_busy_cycles 3174132078.447939 # Number of busy cycles -system.cpu.not_idle_fraction 0.030624 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.969376 # Percentage of idle cycles -system.cpu.Branches 199584978 # Number of branches fetched +system.cpu.committedInsts 882895003 # Number of instructions committed +system.cpu.committedOps 1037473525 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 952709754 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 896425 # Number of float alu accesses +system.cpu.num_func_calls 52419949 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 134729686 # number of instructions that are conditional controls +system.cpu.num_int_insts 952709754 # number of integer instructions +system.cpu.num_fp_insts 896425 # number of float instructions +system.cpu.num_int_register_reads 1388360502 # number of times the integer registers were read +system.cpu.num_int_register_writes 755717952 # number of times the integer registers were written +system.cpu.num_fp_register_reads 1444442 # number of times the floating registers were read +system.cpu.num_fp_register_writes 761348 # number of times the floating registers were written +system.cpu.num_cc_register_reads 231664947 # number of times the CC registers were read +system.cpu.num_cc_register_writes 231068644 # number of times the CC registers were written +system.cpu.num_mem_refs 316605789 # number of memory refs +system.cpu.num_load_insts 165822487 # Number of load instructions +system.cpu.num_store_insts 150783302 # Number of store instructions +system.cpu.num_idle_cycles 100487560505.254059 # Number of idle cycles +system.cpu.num_busy_cycles 3177356581.745939 # Number of busy cycles +system.cpu.not_idle_fraction 0.030650 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.969350 # Percentage of idle cycles +system.cpu.Branches 197184546 # Number of branches fetched system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 727639004 69.27% 69.27% # Class of executed instruction -system.cpu.op_class::IntMult 2217476 0.21% 69.48% # Class of executed instruction -system.cpu.op_class::IntDiv 99175 0.01% 69.49% # Class of executed instruction +system.cpu.op_class::IntAlu 719043510 69.27% 69.27% # Class of executed instruction +system.cpu.op_class::IntMult 2202813 0.21% 69.48% # Class of executed instruction +system.cpu.op_class::IntDiv 97927 0.01% 69.49% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 69.49% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 69.49% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 69.49% # Class of executed instruction @@ -575,126 +574,126 @@ system.cpu.op_class::SimdFloatAlu 0 0.00% 69.49% # Cl system.cpu.op_class::SimdFloatCmp 13 0.00% 69.49% # Class of executed instruction system.cpu.op_class::SimdFloatCvt 21 0.00% 69.49% # Class of executed instruction system.cpu.op_class::SimdFloatDiv 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 110553 0.01% 69.50% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 110813 0.01% 69.50% # Class of executed instruction system.cpu.op_class::SimdFloatMult 0 0.00% 69.50% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.50% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::MemRead 167768846 15.97% 85.47% # Class of executed instruction -system.cpu.op_class::MemWrite 152638747 14.53% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 165822487 15.97% 85.47% # Class of executed instruction +system.cpu.op_class::MemWrite 150783302 14.53% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1050473844 # Class of executed instruction +system.cpu.op_class::total 1038060895 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16327 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 10213653 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.965664 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 310015199 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 10214165 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 30.351497 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 3500615250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.965664 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999933 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999933 # Average percentage of cache occupancy +system.cpu.kern.inst.quiesce 16280 # number of quiesce instructions executed +system.cpu.dcache.tags.replacements 10067650 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.966034 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 306351638 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 10068162 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 30.427762 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 3466781500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.966034 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999934 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999934 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 401 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1291569953 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1291569953 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 156758765 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 156758765 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 144836105 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 144836105 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 393576 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 393576 # number of SoftPFReq hits -system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 334400 # number of WriteInvalidateReq hits -system.cpu.dcache.WriteInvalidateReq_hits::total 334400 # number of WriteInvalidateReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3672090 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3672090 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 3974747 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3974747 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 301594870 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 301594870 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 301988446 # number of overall hits -system.cpu.dcache.overall_hits::total 301988446 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 5315823 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 5315823 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2219045 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2219045 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1297249 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1297249 # number of SoftPFReq misses -system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1232796 # number of WriteInvalidateReq misses -system.cpu.dcache.WriteInvalidateReq_misses::total 1232796 # number of WriteInvalidateReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 304342 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 304342 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 7534868 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7534868 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 8832117 # number of overall misses -system.cpu.dcache.overall_misses::total 8832117 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 84066704475 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 84066704475 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 66382286210 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 66382286210 # number of WriteReq miss cycles -system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 32849513005 # number of WriteInvalidateReq miss cycles -system.cpu.dcache.WriteInvalidateReq_miss_latency::total 32849513005 # number of WriteInvalidateReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4463810234 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 4463810234 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 164000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 164000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 150448990685 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 150448990685 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 150448990685 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 150448990685 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 162074588 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 162074588 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 147055150 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 147055150 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1690825 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1690825 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1567196 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::total 1567196 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3976432 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3976432 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 3974749 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 3974749 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 309129738 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 309129738 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 310820563 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 310820563 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032799 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.032799 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015090 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015090 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.767228 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.767228 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.786625 # miss rate for WriteInvalidateReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.786625 # miss rate for WriteInvalidateReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.076536 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.076536 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.024374 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.024374 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.028415 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.028415 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15814.428824 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15814.428824 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29914.799479 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29914.799479 # average WriteReq miss latency -system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 26646.349441 # average WriteInvalidateReq miss latency -system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 26646.349441 # average WriteInvalidateReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14667.085825 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14667.085825 # average LoadLockedReq miss latency +system.cpu.dcache.tags.tag_accesses 1276220350 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1276220350 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 154968992 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 154968992 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 143085243 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 143085243 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 390390 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 390390 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 335374 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 335374 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3613361 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3613361 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 3913213 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 3913213 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 298054235 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 298054235 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 298444625 # number of overall hits +system.cpu.dcache.overall_hits::total 298444625 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 5249224 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 5249224 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2178798 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2178798 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1272425 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1272425 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1229487 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1229487 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 301533 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 301533 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 7428022 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7428022 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 8700447 # number of overall misses +system.cpu.dcache.overall_misses::total 8700447 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 82824595500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 82824595500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 63552242000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 63552242000 # number of WriteReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 50841662000 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 50841662000 # number of WriteLineReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4423231500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 4423231500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 82000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 82000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 146376837500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 146376837500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 146376837500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 146376837500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 160218216 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 160218216 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 145264041 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 145264041 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1662815 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1662815 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::cpu.data 1564861 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 1564861 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3914894 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3914894 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 3913214 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 3913214 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 305482257 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 305482257 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 307145072 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 307145072 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032763 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.032763 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.014999 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.014999 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.765223 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.765223 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.785684 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.785684 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.077022 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.077022 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.024316 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.024316 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.028327 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.028327 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15778.445633 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15778.445633 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29168.487395 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29168.487395 # average WriteReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 41351.931334 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 41351.931334 # average WriteLineReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14669.145666 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14669.145666 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19967.037337 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19967.037337 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17034.306802 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17034.306802 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19706.031767 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19706.031767 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16824.059442 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16824.059442 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -703,154 +702,154 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 7878976 # number of writebacks -system.cpu.dcache.writebacks::total 7878976 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 16016 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 16016 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21118 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 21118 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 70685 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 70685 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 37134 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 37134 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 37134 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 37134 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5299807 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5299807 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2197927 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2197927 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1295520 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1295520 # number of SoftPFReq MSHR misses -system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data 1232796 # number of WriteInvalidateReq MSHR misses -system.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1232796 # number of WriteInvalidateReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 233657 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 233657 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 7497734 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 7497734 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 8793254 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 8793254 # number of overall MSHR misses +system.cpu.dcache.writebacks::writebacks 7760504 # number of writebacks +system.cpu.dcache.writebacks::total 7760504 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 23609 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 23609 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21261 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 21261 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 71576 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 71576 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 44870 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 44870 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 44870 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 44870 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5225615 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5225615 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2157537 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2157537 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1270654 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1270654 # number of SoftPFReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1229487 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 1229487 # number of WriteLineReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 229957 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 229957 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 7383152 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 7383152 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 8653806 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 8653806 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33706 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 33706 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33710 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 33710 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67416 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 67416 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75489557525 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 75489557525 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 62224351540 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 62224351540 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 20153084274 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 20153084274 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 31000318995 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 31000318995 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2998156750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2998156750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 161000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 161000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 137713909065 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 137713909065 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 157866993339 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 157866993339 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5751194250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5751194250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5618584250 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5618584250 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11369778500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 11369778500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032700 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032700 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014946 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014946 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.766206 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.766206 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.786625 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.786625 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.058760 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.058760 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024254 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.024254 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028290 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.028290 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14243.831431 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14243.831431 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28310.472341 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28310.472341 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15555.980822 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15555.980822 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 25146.349433 # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25146.349433 # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12831.444168 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12831.444168 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 80500 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 80500 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18367.403947 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18367.403947 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17953.193816 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17953.193816 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 170628.204177 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 170628.204177 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 166674.110056 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 166674.110056 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 168651.039813 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 168651.039813 # average overall mshr uncacheable latency +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 77028808000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 77028808000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 60744856000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 60744856000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 20507265000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 20507265000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 49612175000 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 49612175000 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3074046500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3074046500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 81000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 81000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 137773664000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 137773664000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 158280929000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 158280929000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5831352000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5831352000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5695270000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5695270000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11526622000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 11526622000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032616 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032616 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014853 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014853 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.764158 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.764158 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.785684 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.785684 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.058739 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.058739 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024169 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.024169 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028175 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.028175 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14740.620578 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14740.620578 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28154.722723 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28154.722723 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16139.141733 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16139.141733 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 40351.931334 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 40351.931334 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13367.918785 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13367.918785 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18660.548232 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18660.548232 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18290.325552 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18290.325552 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173006.349018 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173006.349018 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 168948.976565 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 168948.976565 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 170977.542423 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 170977.542423 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 13753173 # number of replacements -system.cpu.icache.tags.tagsinuse 511.880059 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 880276980 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 13753685 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 64.002991 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 35133104250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.880059 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999766 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999766 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 13898073 # number of replacements +system.cpu.icache.tags.tagsinuse 511.854844 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 869540659 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 13898585 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 62.563251 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 43284980500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.854844 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999716 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999716 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 191 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 248 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 195 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 907784360 # Number of tag accesses -system.cpu.icache.tags.data_accesses 907784360 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 880276980 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 880276980 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 880276980 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 880276980 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 880276980 # number of overall hits -system.cpu.icache.overall_hits::total 880276980 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 13753690 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 13753690 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 13753690 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 13753690 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 13753690 # number of overall misses -system.cpu.icache.overall_misses::total 13753690 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 184520052183 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 184520052183 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 184520052183 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 184520052183 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 184520052183 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 184520052183 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 894030670 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 894030670 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 894030670 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 894030670 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 894030670 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 894030670 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015384 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.015384 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.015384 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.015384 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.015384 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.015384 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13416.039782 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13416.039782 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13416.039782 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13416.039782 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13416.039782 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13416.039782 # average overall miss latency +system.cpu.icache.tags.tag_accesses 897337839 # Number of tag accesses +system.cpu.icache.tags.data_accesses 897337839 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 869540659 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 869540659 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 869540659 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 869540659 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 869540659 # number of overall hits +system.cpu.icache.overall_hits::total 869540659 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 13898590 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 13898590 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 13898590 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 13898590 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 13898590 # number of overall misses +system.cpu.icache.overall_misses::total 13898590 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 186400133500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 186400133500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 186400133500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 186400133500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 186400133500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 186400133500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 883439249 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 883439249 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 883439249 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 883439249 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 883439249 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 883439249 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015732 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.015732 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.015732 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.015732 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.015732 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.015732 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13411.441988 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13411.441988 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13411.441988 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13411.441988 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13411.441988 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13411.441988 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -859,213 +858,224 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13753690 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 13753690 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 13753690 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 13753690 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 13753690 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 13753690 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13898590 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 13898590 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 13898590 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 13898590 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 13898590 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 13898590 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable system.cpu.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 163860958817 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 163860958817 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 163860958817 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 163860958817 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 163860958817 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 163860958817 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 3211087000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 3211087000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 3211087000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 3211087000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015384 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015384 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015384 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.015384 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015384 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.015384 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11913.963367 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11913.963367 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11913.963367 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11913.963367 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11913.963367 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11913.963367 # average overall mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 74459.988406 # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 74459.988406 # average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 74459.988406 # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 74459.988406 # average overall mshr uncacheable latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 172501543500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 172501543500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 172501543500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 172501543500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 172501543500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 172501543500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 3229158000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 3229158000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 3229158000 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 3229158000 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015732 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015732 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015732 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.015732 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015732 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.015732 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12411.441988 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12411.441988 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12411.441988 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12411.441988 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12411.441988 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12411.441988 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 74879.026087 # average ReadReq mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 74879.026087 # average ReadReq mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 74879.026087 # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 74879.026087 # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1292250 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65291.754390 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 27666738 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1355280 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 20.414038 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 7588597000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 38342.781923 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 308.197317 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 420.773838 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 6468.758735 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 19751.242576 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.585064 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004703 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006420 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.098705 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.301380 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996273 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 297 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 62733 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 292 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 391 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2458 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5452 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54401 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004532 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.957230 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 264471216 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 264471216 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 371629 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 250715 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 13674158 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 6553954 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 20850456 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 7878976 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 7878976 # number of Writeback hits -system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data 723057 # number of WriteInvalidateReq hits -system.cpu.l2cache.WriteInvalidateReq_hits::total 723057 # number of WriteInvalidateReq hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 9863 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 9863 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1639498 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1639498 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 371629 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 250715 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 13674158 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 8193452 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 22489954 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 371629 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 250715 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 13674158 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 8193452 # number of overall hits -system.cpu.l2cache.overall_hits::total 22489954 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 4157 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 4054 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 79532 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 275030 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 362773 # number of ReadReq misses -system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data 509738 # number of WriteInvalidateReq misses -system.cpu.l2cache.WriteInvalidateReq_misses::total 509738 # number of WriteInvalidateReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 35651 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 35651 # number of UpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 512916 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 512916 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 4157 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 4054 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 79532 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 787946 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 875689 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 4157 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 4054 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 79532 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 787946 # number of overall misses -system.cpu.l2cache.overall_misses::total 875689 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 357827500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 356872250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 6528298780 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22994549799 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 30237548329 # number of ReadReq miss cycles -system.cpu.l2cache.WriteInvalidateReq_miss_latency::cpu.data 123996 # number of WriteInvalidateReq miss cycles -system.cpu.l2cache.WriteInvalidateReq_miss_latency::total 123996 # number of WriteInvalidateReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 554901623 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 554901623 # number of UpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 159000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41601774937 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 41601774937 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 357827500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 356872250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 6528298780 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 64596324736 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 71839323266 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 357827500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 356872250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 6528298780 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 64596324736 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 71839323266 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 375786 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 254769 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 13753690 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 6828984 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 21213229 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 7878976 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 7878976 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data 1232795 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.l2cache.WriteInvalidateReq_accesses::total 1232795 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 45514 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 45514 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2152414 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2152414 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 375786 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 254769 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 13753690 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 8981398 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 23365643 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 375786 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 254769 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 13753690 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 8981398 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 23365643 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.011062 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.015912 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.005783 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.040274 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.017101 # miss rate for ReadReq accesses -system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data 0.413482 # miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.413482 # miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.783297 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.783297 # miss rate for UpgradeReq accesses +system.cpu.l2cache.tags.replacements 1262077 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65231.896667 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 43818011 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1325564 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 33.056126 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 38337641500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 38267.922304 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 322.380584 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 465.537699 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 6521.520612 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 19654.535467 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.583922 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004919 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007104 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.099511 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.299904 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.995360 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 334 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 63153 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 334 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 404 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2433 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5488 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54788 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.005096 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.963638 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 393503422 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 393503422 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 363149 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 250594 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 613743 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 7760504 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 7760504 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 9779 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 9779 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1625617 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1625617 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 13818912 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 13818912 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6453062 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 6453062 # number of ReadSharedReq hits +system.cpu.l2cache.InvalidateReq_hits::cpu.data 721925 # number of InvalidateReq hits +system.cpu.l2cache.InvalidateReq_hits::total 721925 # number of InvalidateReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 363149 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 250594 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 13818912 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 8078679 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 22511334 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 363149 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 250594 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 13818912 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 8078679 # number of overall hits +system.cpu.l2cache.overall_hits::total 22511334 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 3987 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3909 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 7896 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 35285 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 35285 # number of UpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 486856 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 486856 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 79678 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 79678 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 273164 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 273164 # number of ReadSharedReq misses +system.cpu.l2cache.InvalidateReq_misses::cpu.data 507562 # number of InvalidateReq misses +system.cpu.l2cache.InvalidateReq_misses::total 507562 # number of InvalidateReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 3987 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 3909 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 79678 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 760020 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 847594 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 3987 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 3909 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 79678 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 760020 # number of overall misses +system.cpu.l2cache.overall_misses::total 847594 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 341850000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 340742500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 682592500 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 544841000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 544841000 # number of UpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 79500 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::total 79500 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 39254870000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 39254870000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 6511661500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 6511661500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 22761554500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 22761554500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 40187730500 # number of InvalidateReq miss cycles +system.cpu.l2cache.InvalidateReq_miss_latency::total 40187730500 # number of InvalidateReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 341850000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 340742500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 6511661500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 62016424500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 69210678500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 341850000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 340742500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 6511661500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 62016424500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 69210678500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 367136 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 254503 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 621639 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 7760504 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 7760504 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 45064 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 45064 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2112473 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2112473 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 13898590 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 13898590 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 6726226 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 6726226 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1229487 # number of InvalidateReq accesses(hits+misses) +system.cpu.l2cache.InvalidateReq_accesses::total 1229487 # number of InvalidateReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 367136 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 254503 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 13898590 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 8838699 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 23358928 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 367136 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 254503 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 13898590 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 8838699 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 23358928 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.010860 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.015359 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.012702 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.782998 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.782998 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.238298 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.238298 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.011062 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.015912 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005783 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.087731 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.037478 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.011062 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.015912 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005783 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.087731 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.037478 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 86078.301660 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 88029.662062 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 82083.925715 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83607.423914 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 83351.154383 # average ReadReq miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::cpu.data 0.243254 # average WriteInvalidateReq miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::total 0.243254 # average WriteInvalidateReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15564.826316 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15564.826316 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.230467 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.230467 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005733 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005733 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.040612 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.040612 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.412824 # miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::total 0.412824 # miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.010860 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.015359 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005733 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.085988 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.036286 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.010860 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.015359 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005733 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.085988 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.036286 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 85741.158766 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 87168.713226 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 86447.885005 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15441.150631 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15441.150631 # average UpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500 # average SCUpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81108.358751 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81108.358751 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 86078.301660 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 88029.662062 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82083.925715 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81980.649354 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 82037.485073 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 86078.301660 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 88029.662062 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82083.925715 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81980.649354 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 82037.485073 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80629.323660 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80629.323660 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81724.710711 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81724.710711 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83325.601104 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83325.601104 # average ReadSharedReq miss latency +system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 79177.973331 # average InvalidateReq miss latency +system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 79177.973331 # average InvalidateReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 85741.158766 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 87168.713226 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81724.710711 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81598.411226 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 81655.460633 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 85741.158766 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 87168.713226 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81724.710711 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81598.411226 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 81655.460633 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1074,31 +1084,35 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1107523 # number of writebacks -system.cpu.l2cache.writebacks::total 1107523 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 4157 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 4054 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 79532 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 275030 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 362773 # number of ReadReq MSHR misses -system.cpu.l2cache.WriteInvalidateReq_mshr_misses::cpu.data 509738 # number of WriteInvalidateReq MSHR misses -system.cpu.l2cache.WriteInvalidateReq_mshr_misses::total 509738 # number of WriteInvalidateReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 35651 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 35651 # number of UpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 512916 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 512916 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 4157 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 4054 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 79532 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 787946 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 875689 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 4157 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 4054 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 79532 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 787946 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 875689 # number of overall MSHR misses +system.cpu.l2cache.writebacks::writebacks 1077959 # number of writebacks +system.cpu.l2cache.writebacks::total 1077959 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 3987 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3909 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 7896 # number of ReadReq MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1116 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 1116 # number of CleanEvict MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 35285 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 35285 # number of UpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 486856 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 486856 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 79678 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 79678 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 273164 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 273164 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 507562 # number of InvalidateReq MSHR misses +system.cpu.l2cache.InvalidateReq_mshr_misses::total 507562 # number of InvalidateReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 3987 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3909 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 79678 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 760020 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 847594 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 3987 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3909 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 79678 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 760020 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 847594 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33706 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::total 76831 # number of ReadReq MSHR uncacheable @@ -1107,143 +1121,153 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33710 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67416 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::total 110541 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 305614500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 305848750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 5531016720 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19548409701 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25690889671 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data 16058529504 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total 16058529504 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 625079648 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 625079648 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 135000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 135000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 35188398563 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 35188398563 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 305614500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 305848750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 5531016720 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 54736808264 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 60879288234 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 305614500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 305848750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 5531016720 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 54736808264 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 60879288234 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 2585776000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5279091500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 7864867500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5180093000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5180093000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 2585776000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10459184500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 13044960500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.011062 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.015912 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.005783 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.040274 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.017101 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.413482 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.413482 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.783297 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.783297 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 301980000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 301652500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 603632500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 728816500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 728816500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 69500 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 69500 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 34386310000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 34386310000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 5714881500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 5714881500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 20029914500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 20029914500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 35112110500 # number of InvalidateReq MSHR miss cycles +system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 35112110500 # number of InvalidateReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 301980000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 301652500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 5714881500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 54416224500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 60734738500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 301980000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 301652500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 5714881500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 54416224500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 60734738500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 2690095500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5410027000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 8100122500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5307605000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5307605000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 2690095500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10717632000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 13407727500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.010860 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.015359 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.012702 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.782998 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.782998 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.238298 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.238298 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.011062 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.015912 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005783 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087731 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.037478 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.011062 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.015912 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005783 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087731 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.037478 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73518.041857 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 75443.697583 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69544.544586 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71077.372290 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70818.086437 # average ReadReq mshr miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 31503.496902 # average WriteInvalidateReq mshr miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 31503.496902 # average WriteInvalidateReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17533.299150 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17533.299150 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 67500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 67500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68604.603021 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68604.603021 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73518.041857 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 75443.697583 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69544.544586 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69467.715128 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69521.586127 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73518.041857 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 75443.697583 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69544.544586 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69467.715128 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69521.586127 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 59960.023188 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 156621.714235 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 102365.809374 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 153666.360131 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 153666.360131 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 59960.023188 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 155143.949508 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 118010.154603 # average overall mshr uncacheable latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.230467 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.230467 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005733 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005733 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.040612 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.040612 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.412824 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.412824 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.010860 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.015359 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005733 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.085988 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.036286 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.010860 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.015359 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005733 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.085988 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.036286 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 75741.158766 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 77168.713226 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 76447.885005 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20655.136744 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20655.136744 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70629.323660 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70629.323660 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71724.710711 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71724.710711 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73325.601104 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73325.601104 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 69177.973331 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69177.973331 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75741.158766 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 77168.713226 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71724.710711 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71598.411226 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71655.460633 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75741.158766 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 77168.713226 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71724.710711 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71598.411226 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71655.460633 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 62379.026087 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160506.349018 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 105427.789564 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 157448.976565 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157448.976565 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 62379.026087 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 158977.572090 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 121291.896220 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 21652739 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 21644705 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 1048560 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 21674258 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33710 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33710 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 7878976 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1339565 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1232795 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 45517 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 45519 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2152414 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2152414 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 27593630 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 28534080 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 622119 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 992785 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 57742614 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 880408660 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1158207750 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2038152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3006288 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2043660850 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 470306 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 33102923 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.033230 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.179236 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::Writeback 8945109 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 16396444 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 45067 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 45068 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2112473 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2112473 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 13898590 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 6735107 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1336151 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1229487 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41779933 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 30429687 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 620392 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 972976 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 73802988 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 889682260 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1062595910 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2036024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2937088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1957251282 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1844105 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 50552964 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.048758 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.215362 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 32002916 96.68% 96.68% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 1100007 3.32% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 48088105 95.12% 95.12% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 2464859 4.88% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 33102923 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 25622352750 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1278000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 50552964 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 32307276000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 1324500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 20698021683 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 20891010000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14320653166 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13945928913 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 367823750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 365889000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 617486750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 605840000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40333 # Transaction distribution -system.iobus.trans_dist::ReadResp 40333 # Transaction distribution +system.iobus.trans_dist::ReadReq 40329 # Transaction distribution +system.iobus.trans_dist::ReadResp 40329 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution -system.iobus.trans_dist::WriteResp 29907 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution +system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -1260,11 +1284,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231024 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231024 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231016 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231016 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353808 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353800 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1281,11 +1305,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334496 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334496 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492448 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7492416 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) @@ -1314,211 +1338,213 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 606968921 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 568778648 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 148463571 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147776000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 174500 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115493 # number of replacements -system.iocache.tags.tagsinuse 10.456626 # Cycle average of tags in use +system.iocache.tags.replacements 115490 # number of replacements +system.iocache.tags.tagsinuse 10.455215 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115509 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115506 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13157260299000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.510556 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.946069 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.219410 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.434129 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.653539 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13165278431000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.510021 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.945193 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.219376 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.434075 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.653451 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039965 # Number of tag accesses -system.iocache.tags.data_accesses 1039965 # Number of data accesses +system.iocache.tags.tag_accesses 1039929 # Number of tag accesses +system.iocache.tags.data_accesses 1039929 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8848 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8885 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8844 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8881 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8848 # number of demand (read+write) misses -system.iocache.demand_misses::total 8888 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8844 # number of demand (read+write) misses +system.iocache.demand_misses::total 8884 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8848 # number of overall misses -system.iocache.overall_misses::total 8888 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5072000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1591055254 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1596127254 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::realview.ethernet 352500 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 352500 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19834612096 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 19834612096 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5424500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1591055254 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1596479754 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5424500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1591055254 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1596479754 # number of overall miss cycles +system.iocache.overall_misses::realview.ide 8844 # number of overall misses +system.iocache.overall_misses::total 8884 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5069000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1566099238 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1571168238 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12612607410 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12612607410 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5420000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1566099238 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1571519238 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5420000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1566099238 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1571519238 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8848 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8885 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8844 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8881 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8848 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8888 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8844 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8884 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8848 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8888 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8844 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8884 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 179820.892179 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 179642.909848 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117500 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 117500 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 185954.137253 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 185954.137253 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 179820.892179 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 179621.934518 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 179820.892179 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 179621.934518 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 109316 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137000 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 177080.420398 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 176913.437451 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118246.150623 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118246.150623 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135500 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 177080.420398 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 176893.205538 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135500 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 177080.420398 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 176893.205538 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 29516 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 16121 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3281 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.780969 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.996038 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106630 # number of writebacks -system.iocache.writebacks::total 106630 # number of writebacks +system.iocache.writebacks::writebacks 106631 # number of writebacks +system.iocache.writebacks::total 106631 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8848 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8885 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8844 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8881 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8848 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8888 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8844 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8884 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8848 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8888 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3142000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1129796362 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1132938362 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 193500 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 193500 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14288050130 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14288050130 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3335500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1129796362 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1133131862 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3335500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1129796362 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1133131862 # number of overall MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8844 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8884 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1123899238 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1127118238 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7279407410 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7279407410 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3420000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1123899238 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1127319238 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3420000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1123899238 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1127319238 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 84918.918919 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 127689.462251 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 127511.351941 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 64500 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 64500 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133953.818814 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133953.818814 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 127689.462251 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 127490.083483 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 127689.462251 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 127490.083483 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87000 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 127080.420398 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 126913.437451 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68246.150623 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68246.150623 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 127080.420398 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 126893.205538 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 127080.420398 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 126893.205538 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 448489 # Transaction distribution -system.membus.trans_dist::ReadResp 448489 # Transaction distribution +system.membus.trans_dist::ReadReq 76831 # Transaction distribution +system.membus.trans_dist::ReadResp 446450 # Transaction distribution system.membus.trans_dist::WriteReq 33710 # Transaction distribution system.membus.trans_dist::WriteResp 33710 # Transaction distribution -system.membus.trans_dist::Writeback 1214153 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 616398 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 616398 # Transaction distribution -system.membus.trans_dist::UpgradeReq 36221 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 36223 # Transaction distribution -system.membus.trans_dist::ReadExReq 512353 # Transaction distribution -system.membus.trans_dist::ReadExResp 512353 # Transaction distribution +system.membus.trans_dist::Writeback 1184590 # Transaction distribution +system.membus.trans_dist::CleanEvict 190005 # Transaction distribution +system.membus.trans_dist::UpgradeReq 35851 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.membus.trans_dist::UpgradeResp 35852 # Transaction distribution +system.membus.trans_dist::ReadExReq 993855 # Transaction distribution +system.membus.trans_dist::ReadExResp 993855 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 369619 # Transaction distribution +system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution +system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6942 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4040402 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4170106 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335069 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 335069 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4505175 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4133679 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4263383 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 340829 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 340829 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4604212 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13884 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 159663776 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 159833626 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14049088 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14049088 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 173882714 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3324 # Total snoops (count) -system.membus.snoop_fanout::samples 2861471 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 155834656 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 156004506 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7214528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7214528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 163219034 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3445 # Total snoops (count) +system.membus.snoop_fanout::samples 2994110 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2861471 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2994110 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2861471 # Request fanout histogram -system.membus.reqLayer0.occupancy 107107000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2994110 # Request fanout histogram +system.membus.reqLayer0.occupancy 107330000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5171500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5385500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 10418059043 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 7724756059 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 5433894864 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 7445249237 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 151694929 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 228975298 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt index 1bcf52f34..0afb21efb 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt @@ -4,71 +4,71 @@ sim_seconds 51.111153 # Nu sim_ticks 51111152682000 # Number of ticks simulated final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1028340 # Simulator instruction rate (inst/s) -host_op_rate 1208468 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53383325140 # Simulator tick rate (ticks/s) -host_mem_usage 714148 # Number of bytes of host memory used -host_seconds 957.44 # Real time elapsed on the host +host_inst_rate 1174774 # Simulator instruction rate (inst/s) +host_op_rate 1380553 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 60985034894 # Simulator tick rate (ticks/s) +host_mem_usage 718504 # Number of bytes of host memory used +host_seconds 838.09 # Real time elapsed on the host sim_insts 984570519 # Number of instructions simulated sim_ops 1157031967 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 203392 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 187968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3328564 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 37865864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3317876 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 64750152 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 208384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 188288 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2234176 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 36967936 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 441792 # Number of bytes read from this memory -system.physmem.bytes_read::total 81626364 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3328564 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2234176 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5562740 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 103043072 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.itb.walker 188480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2225152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 45360128 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 442112 # Number of bytes read from this memory +system.physmem.bytes_read::total 116883644 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3317876 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2225152 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5543028 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 103060608 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 103063652 # Number of bytes written to this memory +system.physmem.bytes_written::total 103081188 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 3178 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2937 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 92416 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 591667 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 92249 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 1011734 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 3256 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2942 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 34909 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 577624 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6903 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1315832 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1610048 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2945 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 34768 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 708752 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6908 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1866727 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1610322 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1612621 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1612895 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 3979 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 3678 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 65124 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 740853 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 64915 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1266850 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 4077 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 3684 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 43712 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 723285 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8644 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1597036 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 65124 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 43712 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 108836 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2016058 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 3688 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 43536 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 887480 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8650 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2286852 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 64915 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 43536 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 108450 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2016402 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 403 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2016461 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2016058 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2016804 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2016402 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 3979 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 3678 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 65124 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 741256 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 64915 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1267252 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 4077 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 3684 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 43712 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 723285 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8644 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3613497 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 3688 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 43536 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 887480 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8650 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4303656 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -317,9 +317,9 @@ system.cpu0.dcache.WriteReq_hits::total 159522868 # nu system.cpu0.dcache.SoftPFReq_hits::cpu0.data 208530 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::cpu1.data 215328 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::total 423858 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 146037 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data 191672 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 337709 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 146037 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu1.data 191672 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 337709 # number of WriteLineReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2127418 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 2183031 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 4310449 # number of LoadLockedReq hits @@ -341,9 +341,9 @@ system.cpu0.dcache.WriteReq_misses::total 2570259 # n system.cpu0.dcache.SoftPFReq_misses::cpu0.data 792908 # number of SoftPFReq misses system.cpu0.dcache.SoftPFReq_misses::cpu1.data 791180 # number of SoftPFReq misses system.cpu0.dcache.SoftPFReq_misses::total 1584088 # number of SoftPFReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 765143 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu1.data 480206 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 1245349 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 765143 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu1.data 480206 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 1245349 # number of WriteLineReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 123898 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 129919 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 253817 # number of LoadLockedReq misses @@ -364,9 +364,9 @@ system.cpu0.dcache.WriteReq_accesses::total 162093127 # system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 1001438 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 1006508 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::total 2007946 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 911180 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu1.data 671878 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 1583058 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 911180 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu1.data 671878 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 1583058 # number of WriteLineReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2251316 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 2312950 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 4564266 # number of LoadLockedReq accesses(hits+misses) @@ -388,9 +388,9 @@ system.cpu0.dcache.WriteReq_miss_rate::total 0.015857 system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.791769 # miss rate for SoftPFReq accesses system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.786064 # miss rate for SoftPFReq accesses system.cpu0.dcache.SoftPFReq_miss_rate::total 0.788910 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.839728 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.714722 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.786673 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.839728 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.714722 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.786673 # miss rate for WriteLineReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055034 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.056170 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055610 # miss rate for LoadLockedReq accesses @@ -410,8 +410,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 8921315 # number of writebacks -system.cpu0.dcache.writebacks::total 8921315 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 8921279 # number of writebacks +system.cpu0.dcache.writebacks::total 8921279 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 14295641 # number of replacements system.cpu0.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use @@ -677,8 +677,7 @@ system.cpu1.kern.inst.quiesce 0 # nu system.iobus.trans_dist::ReadReq 40246 # Transaction distribution system.iobus.trans_dist::ReadResp 40246 # Transaction distribution system.iobus.trans_dist::WriteReq 136515 # Transaction distribution -system.iobus.trans_dist::WriteResp 29851 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution +system.iobus.trans_dist::WriteResp 136515 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47598 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -742,8 +741,8 @@ system.iocache.ReadReq_misses::realview.ide 8817 # system.iocache.ReadReq_misses::total 8854 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses system.iocache.demand_misses::realview.ide 8817 # number of demand (read+write) misses system.iocache.demand_misses::total 8857 # number of demand (read+write) misses @@ -755,8 +754,8 @@ system.iocache.ReadReq_accesses::realview.ide 8817 system.iocache.ReadReq_accesses::total 8854 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses system.iocache.demand_accesses::realview.ide 8817 # number of demand (read+write) accesses system.iocache.demand_accesses::total 8857 # number of demand (read+write) accesses @@ -768,8 +767,8 @@ system.iocache.ReadReq_miss_rate::realview.ide 1 system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses @@ -787,133 +786,130 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1722682 # number of replacements -system.l2c.tags.tagsinuse 65341.862498 # Cycle average of tags in use -system.l2c.tags.total_refs 30065488 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1785979 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 16.834178 # Average number of references to valid blocks. +system.l2c.tags.replacements 1722562 # number of replacements +system.l2c.tags.tagsinuse 65341.862549 # Cycle average of tags in use +system.l2c.tags.total_refs 47050546 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1785858 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 26.346185 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 37141.097811 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 156.460660 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 243.495240 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3601.604762 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 9619.799415 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 151.654107 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 201.240500 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2659.657984 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 11566.852019 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.566728 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 37097.979539 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 156.460552 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 243.494258 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3630.477879 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 9618.607320 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 151.652985 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 201.240388 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2660.497968 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 11581.451661 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.566070 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002387 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.003715 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.054956 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.146786 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.055397 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.146768 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002314 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.003071 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.040583 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.176496 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.040596 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.176719 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.997038 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 276 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 63021 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 63020 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 276 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 588 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2715 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4911 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 54671 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2714 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4910 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 54672 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.004211 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.961624 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 290964090 # Number of tag accesses -system.l2c.tags.data_accesses 290964090 # Number of data accesses +system.l2c.tags.occ_task_id_percent::1024 0.961609 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 426855693 # Number of tag accesses +system.l2c.tags.data_accesses 426855693 # Number of data accesses system.l2c.ReadReq_hits::cpu0.dtb.walker 279435 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 145257 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 7107195 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 3754972 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.dtb.walker 276854 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 142760 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 7104726 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 3749259 # number of ReadReq hits -system.l2c.ReadReq_hits::total 22560458 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 8921315 # number of Writeback hits -system.l2c.Writeback_hits::total 8921315 # number of Writeback hits -system.l2c.WriteInvalidateReq_hits::cpu0.data 345123 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::cpu1.data 349209 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::total 694332 # number of WriteInvalidateReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 142757 # number of ReadReq hits +system.l2c.ReadReq_hits::total 844303 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 8921279 # number of Writeback hits +system.l2c.Writeback_hits::total 8921279 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 5687 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 5536 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 11223 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 864873 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 827736 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 1692609 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu0.data 864866 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 827692 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 1692558 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 7107362 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 7104867 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 14212229 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 3754928 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 3749182 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 7504110 # number of ReadSharedReq hits +system.l2c.InvalidateReq_hits::cpu0.data 345122 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::cpu1.data 349199 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::total 694321 # number of InvalidateReq hits system.l2c.demand_hits::cpu0.dtb.walker 279435 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.itb.walker 145257 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 7107195 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 4619845 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 7107362 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 4619794 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.dtb.walker 276854 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 142760 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 7104726 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 4576995 # number of demand (read+write) hits -system.l2c.demand_hits::total 24253067 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 142757 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 7104867 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 4576874 # number of demand (read+write) hits +system.l2c.demand_hits::total 24253200 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.dtb.walker 279435 # number of overall hits system.l2c.overall_hits::cpu0.itb.walker 145257 # number of overall hits -system.l2c.overall_hits::cpu0.inst 7107195 # number of overall hits -system.l2c.overall_hits::cpu0.data 4619845 # number of overall hits +system.l2c.overall_hits::cpu0.inst 7107362 # number of overall hits +system.l2c.overall_hits::cpu0.data 4619794 # number of overall hits system.l2c.overall_hits::cpu1.dtb.walker 276854 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 142760 # number of overall hits -system.l2c.overall_hits::cpu1.inst 7104726 # number of overall hits -system.l2c.overall_hits::cpu1.data 4576995 # number of overall hits -system.l2c.overall_hits::total 24253067 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 142757 # number of overall hits +system.l2c.overall_hits::cpu1.inst 7104867 # number of overall hits +system.l2c.overall_hits::cpu1.data 4576874 # number of overall hits +system.l2c.overall_hits::total 24253200 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 3178 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2937 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 49315 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 177059 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 3256 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 2942 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 34922 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 166908 # number of ReadReq misses -system.l2c.ReadReq_misses::total 440517 # number of ReadReq misses -system.l2c.WriteInvalidateReq_misses::cpu0.data 420020 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::cpu1.data 130997 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::total 551017 # number of WriteInvalidateReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 2945 # number of ReadReq misses +system.l2c.ReadReq_misses::total 12316 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 19994 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 19925 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 39919 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 415064 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 411444 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 826508 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu0.data 415071 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 411488 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 826559 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 49148 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 34781 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 83929 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 177103 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 166985 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 344088 # number of ReadSharedReq misses +system.l2c.InvalidateReq_misses::cpu0.data 420021 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::cpu1.data 131007 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::total 551028 # number of InvalidateReq misses system.l2c.demand_misses::cpu0.dtb.walker 3178 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2937 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 49315 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 592123 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 49148 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 592174 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 3256 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 2942 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 34922 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 578352 # number of demand (read+write) misses -system.l2c.demand_misses::total 1267025 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 2945 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 34781 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 578473 # number of demand (read+write) misses +system.l2c.demand_misses::total 1266892 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 3178 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2937 # number of overall misses -system.l2c.overall_misses::cpu0.inst 49315 # number of overall misses -system.l2c.overall_misses::cpu0.data 592123 # number of overall misses +system.l2c.overall_misses::cpu0.inst 49148 # number of overall misses +system.l2c.overall_misses::cpu0.data 592174 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 3256 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 2942 # number of overall misses -system.l2c.overall_misses::cpu1.inst 34922 # number of overall misses -system.l2c.overall_misses::cpu1.data 578352 # number of overall misses -system.l2c.overall_misses::total 1267025 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 2945 # number of overall misses +system.l2c.overall_misses::cpu1.inst 34781 # number of overall misses +system.l2c.overall_misses::cpu1.data 578473 # number of overall misses +system.l2c.overall_misses::total 1266892 # number of overall misses system.l2c.ReadReq_accesses::cpu0.dtb.walker 282613 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.itb.walker 148194 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 7156510 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 3932031 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.dtb.walker 280110 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.itb.walker 145702 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 7139648 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 3916167 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 23000975 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 8921315 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 8921315 # number of Writeback accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu0.data 765143 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu1.data 480206 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::total 1245349 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 856619 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 8921279 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 8921279 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 25681 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 25461 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 51142 # number of UpgradeReq accesses(hits+misses) @@ -922,6 +918,15 @@ system.l2c.SCUpgradeReq_accesses::total 1 # nu system.l2c.ReadExReq_accesses::cpu0.data 1279937 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 1239180 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 2519117 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 7156510 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 7139648 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 14296158 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 3932031 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 3916167 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 7848198 # number of ReadSharedReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::cpu0.data 765143 # number of InvalidateReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::cpu1.data 480206 # number of InvalidateReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::total 1245349 # number of InvalidateReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.dtb.walker 282613 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.itb.walker 148194 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.inst 7156510 # number of demand (read+write) accesses @@ -942,42 +947,44 @@ system.l2c.overall_accesses::cpu1.data 5155347 # nu system.l2c.overall_accesses::total 25520092 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.011245 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.019819 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.006891 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.045030 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.011624 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.020192 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.004891 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.042620 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.019152 # miss rate for ReadReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.548943 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.272793 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::total 0.442460 # miss rate for WriteInvalidateReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.020212 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.014377 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.778552 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.782569 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.780552 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.324285 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.332029 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.328094 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.324290 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.332065 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.328115 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.006868 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004872 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.005871 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.045041 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.042640 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.043843 # miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_miss_rate::cpu0.data 0.548944 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::cpu1.data 0.272814 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::total 0.442469 # miss rate for InvalidateReq accesses system.l2c.demand_miss_rate::cpu0.dtb.walker 0.011245 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.019819 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.006891 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.113608 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.006868 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.113618 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.dtb.walker 0.011624 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.020192 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.004891 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.112185 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.049648 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.020212 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.004872 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.112208 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.049643 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.011245 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.019819 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.006891 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.113608 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.006868 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.113618 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.dtb.walker 0.011624 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.020192 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.004891 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.112185 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.049648 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.020212 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.004872 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.112208 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.049643 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -986,49 +993,51 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 1503417 # number of writebacks -system.l2c.writebacks::total 1503417 # number of writebacks +system.l2c.writebacks::writebacks 1503691 # number of writebacks +system.l2c.writebacks::total 1503691 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 526050 # Transaction distribution -system.membus.trans_dist::ReadResp 526050 # Transaction distribution +system.membus.trans_dist::ReadReq 76679 # Transaction distribution +system.membus.trans_dist::ReadResp 525866 # Transaction distribution system.membus.trans_dist::WriteReq 33606 # Transaction distribution system.membus.trans_dist::WriteResp 33606 # Transaction distribution -system.membus.trans_dist::Writeback 1610048 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 657676 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 657676 # Transaction distribution +system.membus.trans_dist::Writeback 1610322 # Transaction distribution +system.membus.trans_dist::CleanEvict 228928 # Transaction distribution system.membus.trans_dist::UpgradeReq 40486 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution system.membus.trans_dist::UpgradeResp 40487 # Transaction distribution -system.membus.trans_dist::ReadExReq 825949 # Transaction distribution -system.membus.trans_dist::ReadExResp 825949 # Transaction distribution +system.membus.trans_dist::ReadExReq 1377023 # Transaction distribution +system.membus.trans_dist::ReadExResp 1377023 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 449187 # Transaction distribution +system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution +system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5310719 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5439911 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337673 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 337673 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5777584 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5530845 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5660037 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346505 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 346505 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6006542 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 212730400 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 212899450 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14217536 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14217536 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 227116986 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 212740128 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 212909178 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7391040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7391040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 220300218 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3693816 # Request fanout histogram +system.membus.snoop_fanout::samples 3922896 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3693816 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3922896 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3693816 # Request fanout histogram +system.membus.snoop_fanout::total 3922896 # Request fanout histogram system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1071,39 +1080,42 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 18 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 23464706 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 1320350 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 23464706 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 8921315 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 1245349 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 1245349 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 8921279 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 16986503 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 51142 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 51143 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 2519117 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 2519117 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 28678566 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 32383249 # Packet count per connected master and slave (bytes) +system.toL2Bus.trans_dist::ReadCleanReq 14296158 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 7848198 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 1245349 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 1245349 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 42974207 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 35074075 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 832126 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1655216 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 63549157 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 80535624 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 915126612 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1314364326 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1234659686 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3328504 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6620864 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 2239440306 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 2159735666 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 116338 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 36350757 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.037391 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.189718 # Request fanout histogram +system.toL2Bus.snoop_fanout::samples 53337224 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.025483 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.157587 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 34991565 96.26% 96.26% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 1359192 3.74% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 51978032 97.45% 97.45% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 1359192 2.55% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 36350757 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 53337224 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt index cca0e71cb..4324d934c 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt @@ -1,174 +1,174 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.274696 # Number of seconds simulated -sim_ticks 51274696167500 # Number of ticks simulated -final_tick 51274696167500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.235006 # Number of seconds simulated +sim_ticks 51235005618500 # Number of ticks simulated +final_tick 51235005618500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 293957 # Simulator instruction rate (inst/s) -host_op_rate 345410 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17006997815 # Simulator tick rate (ticks/s) -host_mem_usage 724900 # Number of bytes of host memory used -host_seconds 3014.92 # Real time elapsed on the host -sim_insts 886256415 # Number of instructions simulated -sim_ops 1041383802 # Number of ops (including micro ops) simulated +host_inst_rate 299120 # Simulator instruction rate (inst/s) +host_op_rate 351506 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17342892504 # Simulator tick rate (ticks/s) +host_mem_usage 728488 # Number of bytes of host memory used +host_seconds 2954.24 # Real time elapsed on the host +sim_insts 883670074 # Number of instructions simulated +sim_ops 1038432543 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 116160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 120000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 2956980 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 25219400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 40192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 37376 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 753536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 7117376 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 92544 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.itb.walker 94080 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 2191808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 17867136 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 430080 # Number of bytes read from this memory -system.physmem.bytes_read::total 57036668 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 2956980 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 753536 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 2191808 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5902324 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 77190720 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 126592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 125376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 2934708 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 51720008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 38784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 35712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 741632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 9002048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 95296 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.itb.walker 86336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 2270528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 22315456 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 419776 # Number of bytes read from this memory +system.physmem.bytes_read::total 89912252 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 2934708 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 741632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 2270528 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5946868 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 77430208 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 77211300 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1815 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1875 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 86610 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 394066 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 628 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 584 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 11774 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 111209 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 1446 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.itb.walker 1470 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 34247 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 279174 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6720 # Number of read requests responded to by this memory -system.physmem.num_reads::total 931618 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1206105 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 77450788 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1978 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1959 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 86262 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 808138 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 606 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 558 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 11588 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 140657 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 1489 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.itb.walker 1349 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 35477 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 348679 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6559 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1445299 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1209847 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1208678 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2265 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 57669 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 491849 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 784 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 729 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 14696 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 138809 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 1805 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.itb.walker 1835 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 42746 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 348459 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8388 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1112375 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 57669 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 14696 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 42746 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 115112 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1505435 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1505836 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1505435 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2265 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 57669 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 492250 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 784 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 729 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 14696 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 138809 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 1805 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.itb.walker 1835 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 42746 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 348459 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8388 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2618211 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 440592 # Number of read requests accepted -system.physmem.writeReqs 615308 # Number of write requests accepted -system.physmem.readBursts 440592 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 615308 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28181248 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 16640 # Total number of bytes read from write queue -system.physmem.bytesWritten 38332736 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28197888 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 39379712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 260 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 16359 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 18561 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25854 # Per bank write bursts -system.physmem.perBankRdBursts::1 28544 # Per bank write bursts -system.physmem.perBankRdBursts::2 25469 # Per bank write bursts -system.physmem.perBankRdBursts::3 27506 # Per bank write bursts -system.physmem.perBankRdBursts::4 26728 # Per bank write bursts -system.physmem.perBankRdBursts::5 30588 # Per bank write bursts -system.physmem.perBankRdBursts::6 26415 # Per bank write bursts -system.physmem.perBankRdBursts::7 27502 # Per bank write bursts -system.physmem.perBankRdBursts::8 26500 # Per bank write bursts -system.physmem.perBankRdBursts::9 31676 # Per bank write bursts -system.physmem.perBankRdBursts::10 27941 # Per bank write bursts -system.physmem.perBankRdBursts::11 30917 # Per bank write bursts -system.physmem.perBankRdBursts::12 25895 # Per bank write bursts -system.physmem.perBankRdBursts::13 27920 # Per bank write bursts -system.physmem.perBankRdBursts::14 25066 # Per bank write bursts -system.physmem.perBankRdBursts::15 25811 # Per bank write bursts -system.physmem.perBankWrBursts::0 36067 # Per bank write bursts -system.physmem.perBankWrBursts::1 36031 # Per bank write bursts -system.physmem.perBankWrBursts::2 34636 # Per bank write bursts -system.physmem.perBankWrBursts::3 37309 # Per bank write bursts -system.physmem.perBankWrBursts::4 37132 # Per bank write bursts -system.physmem.perBankWrBursts::5 40234 # Per bank write bursts -system.physmem.perBankWrBursts::6 38375 # Per bank write bursts -system.physmem.perBankWrBursts::7 37986 # Per bank write bursts -system.physmem.perBankWrBursts::8 35542 # Per bank write bursts -system.physmem.perBankWrBursts::9 42123 # Per bank write bursts -system.physmem.perBankWrBursts::10 38624 # Per bank write bursts -system.physmem.perBankWrBursts::11 39603 # Per bank write bursts -system.physmem.perBankWrBursts::12 35582 # Per bank write bursts -system.physmem.perBankWrBursts::13 38033 # Per bank write bursts -system.physmem.perBankWrBursts::14 36333 # Per bank write bursts -system.physmem.perBankWrBursts::15 35339 # Per bank write bursts +system.physmem.num_writes::total 1212420 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2471 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2447 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 57279 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1009466 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 757 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 697 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 14475 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 175701 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 1860 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.itb.walker 1685 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 44316 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 435551 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8193 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1754899 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 57279 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 14475 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 44316 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 116070 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1511275 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 402 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1511677 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1511275 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2471 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2447 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 57279 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1009868 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 757 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 697 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 14475 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 175701 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 1860 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.itb.walker 1685 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 44316 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 435551 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8193 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3266576 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 540590 # Number of read requests accepted +system.physmem.writeReqs 467319 # Number of write requests accepted +system.physmem.readBursts 540590 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 467319 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 34576064 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 21696 # Total number of bytes read from write queue +system.physmem.bytesWritten 29908416 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 34597760 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 29908416 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 339 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 52057 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 34722 # Per bank write bursts +system.physmem.perBankRdBursts::1 34925 # Per bank write bursts +system.physmem.perBankRdBursts::2 34806 # Per bank write bursts +system.physmem.perBankRdBursts::3 34433 # Per bank write bursts +system.physmem.perBankRdBursts::4 35553 # Per bank write bursts +system.physmem.perBankRdBursts::5 39917 # Per bank write bursts +system.physmem.perBankRdBursts::6 33295 # Per bank write bursts +system.physmem.perBankRdBursts::7 34606 # Per bank write bursts +system.physmem.perBankRdBursts::8 31417 # Per bank write bursts +system.physmem.perBankRdBursts::9 34834 # Per bank write bursts +system.physmem.perBankRdBursts::10 32861 # Per bank write bursts +system.physmem.perBankRdBursts::11 34723 # Per bank write bursts +system.physmem.perBankRdBursts::12 29445 # Per bank write bursts +system.physmem.perBankRdBursts::13 31855 # Per bank write bursts +system.physmem.perBankRdBursts::14 31705 # Per bank write bursts +system.physmem.perBankRdBursts::15 31154 # Per bank write bursts +system.physmem.perBankWrBursts::0 29588 # Per bank write bursts +system.physmem.perBankWrBursts::1 28520 # Per bank write bursts +system.physmem.perBankWrBursts::2 28987 # Per bank write bursts +system.physmem.perBankWrBursts::3 29728 # Per bank write bursts +system.physmem.perBankWrBursts::4 31002 # Per bank write bursts +system.physmem.perBankWrBursts::5 33624 # Per bank write bursts +system.physmem.perBankWrBursts::6 29096 # Per bank write bursts +system.physmem.perBankWrBursts::7 30620 # Per bank write bursts +system.physmem.perBankWrBursts::8 28064 # Per bank write bursts +system.physmem.perBankWrBursts::9 30877 # Per bank write bursts +system.physmem.perBankWrBursts::10 28622 # Per bank write bursts +system.physmem.perBankWrBursts::11 29758 # Per bank write bursts +system.physmem.perBankWrBursts::12 25484 # Per bank write bursts +system.physmem.perBankWrBursts::13 27499 # Per bank write bursts +system.physmem.perBankWrBursts::14 28130 # Per bank write bursts +system.physmem.perBankWrBursts::15 27720 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 73 # Number of times write queue was full causing retry -system.physmem.totGap 51273531025000 # Total gap between requests +system.physmem.numWrRetry 11 # Number of times write queue was full causing retry +system.physmem.totGap 51233860786000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 440592 # Read request sizes (log2) +system.physmem.readPktSize::6 540590 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 615308 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 297815 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 95022 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 32137 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 15175 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 467319 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 342994 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 115802 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 50344 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 30801 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 151 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 24 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -180,183 +180,186 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 474 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 472 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 472 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 470 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 470 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 474 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 476 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 475 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 473 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 472 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 470 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 469 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 468 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 467 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 469 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 468 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 462 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 461 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 465 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 465 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 457 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 463 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 456 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 455 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 12335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 14792 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 22598 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 26146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 30213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 32129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 33829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 34268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 34523 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 35690 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 34679 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 37755 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 35326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 34217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 40396 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 33787 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 31090 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2039 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1661 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2381 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 2205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1910 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1760 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1452 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1514 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 914 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 639 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 618 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 367 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 182 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 276595 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 240.471737 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 144.485529 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 284.203347 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 127319 46.03% 46.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 69542 25.14% 71.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 24812 8.97% 80.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 12377 4.47% 84.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 8866 3.21% 87.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 5372 1.94% 89.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4514 1.63% 91.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3651 1.32% 92.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 20142 7.28% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 276595 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 29231 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 15.063871 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 10.425422 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-15 11898 40.70% 40.70% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::16-31 15954 54.58% 95.28% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::32-47 1083 3.70% 98.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::48-63 204 0.70% 99.69% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::64-79 56 0.19% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::80-95 22 0.08% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::96-111 6 0.02% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::112-127 2 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 6847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7567 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 20463 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 25091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 27451 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 27607 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 28499 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 29120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 30157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 29862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 30268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 29365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 30568 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32780 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 28599 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 28666 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 27259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 393 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 34 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 258364 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 249.586227 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 149.482668 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 288.931122 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 115624 44.75% 44.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 63401 24.54% 69.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 24271 9.39% 78.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 12099 4.68% 83.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 9378 3.63% 87.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 5671 2.19% 89.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4999 1.93% 91.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3884 1.50% 92.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19037 7.37% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 258364 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 26815 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 20.147343 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 9.386417 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-15 3084 11.50% 11.50% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::16-31 21562 80.41% 91.91% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::32-47 1686 6.29% 98.20% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::48-63 338 1.26% 99.46% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::64-79 91 0.34% 99.80% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::80-95 28 0.10% 99.90% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::96-111 17 0.06% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::112-127 4 0.01% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::128-143 2 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::176-191 2 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::160-175 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::240-255 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::288-303 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::320-335 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 29231 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 29231 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.490199 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.518949 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 18.634153 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-15 58 0.20% 0.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 27476 94.00% 94.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 804 2.75% 96.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 250 0.86% 97.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 169 0.58% 98.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 102 0.35% 98.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 99 0.34% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 124 0.42% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 61 0.21% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 8 0.03% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 5 0.02% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 19 0.06% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 14 0.05% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 5 0.02% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 2 0.01% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 2 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 3 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 1 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 3 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 2 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 7 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 7 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 3 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::400-415 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::416-431 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 2 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::560-575 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 29231 # Writes before turning the bus around for reads -system.physmem.totQLat 10175638298 # Total ticks spent queuing -system.physmem.totMemAccLat 18431863298 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2201660000 # Total ticks spent in databus transfers -system.physmem.avgQLat 23109.01 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 26815 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 26815 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.427522 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.974087 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 6.290252 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 17 0.06% 0.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 10 0.04% 0.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 10 0.04% 0.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 46 0.17% 0.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 25300 94.35% 94.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 507 1.89% 96.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 249 0.93% 97.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 127 0.47% 97.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 87 0.32% 98.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 125 0.47% 98.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 58 0.22% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 14 0.05% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 19 0.07% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 19 0.07% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 12 0.04% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 8 0.03% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 123 0.46% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 19 0.07% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 20 0.07% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 17 0.06% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 6 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 3 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 6 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 3 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 26815 # Writes before turning the bus around for reads +system.physmem.totQLat 12836932182 # Total ticks spent queuing +system.physmem.totMemAccLat 22966638432 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2701255000 # Total ticks spent in databus transfers +system.physmem.avgQLat 23761.05 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 41859.01 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 0.55 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.75 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 0.55 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.77 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 42511.05 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 0.67 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.58 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 0.68 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.58 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.01 # Data bus utilization in percentage -system.physmem.busUtilRead 0.00 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.67 # Average write queue length when enqueuing -system.physmem.readRowHits 330665 # Number of row buffer hits during reads -system.physmem.writeRowHits 432014 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.09 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 72.13 # Row buffer hit rate for writes -system.physmem.avgGap 48559078.53 # Average gap between requests -system.physmem.pageHitRate 73.39 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1047672360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 569481000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1705126800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 1929536640 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3307165171440 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1163738784870 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29596559989500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34072715762610 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.713146 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 48842268608197 # Time in different power states -system.physmem_0.memoryStateTime::REF 1690779740000 # Time in different power states +system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing +system.physmem.avgWrQLen 22.63 # Average write queue length when enqueuing +system.physmem.readRowHits 422337 # Number of row buffer hits during reads +system.physmem.writeRowHits 326863 # Number of row buffer hits during writes +system.physmem.readRowHitRate 78.17 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 69.94 # Row buffer hit rate for writes +system.physmem.avgGap 50831831.83 # Average gap between requests +system.physmem.pageHitRate 74.36 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1022081760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 555373500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2201604600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 1562664960 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3304577109600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1165623840135 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29580668399250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34056211073805 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.700210 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 48799941577250 # Time in different power states +system.physmem_0.memoryStateTime::REF 1689456600000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 102045610303 # Time in different power states +system.physmem_0.memoryStateTime::ACT 106076762500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1043355600 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 567088500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1729462800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 1951549200 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3307165171440 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1164487973490 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29604202640250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34081147241280 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.697375 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 48841133395944 # Time in different power states -system.physmem_1.memoryStateTime::REF 1690779740000 # Time in different power states +system.physmem_1.actEnergy 931059360 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 506149875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2012353200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 1465445520 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3304577109600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1160291732670 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29572164937500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34041948787725 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.708167 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 48807751567992 # Time in different power states +system.physmem_1.memoryStateTime::REF 1689456600000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 103204176556 # Time in different power states +system.physmem_1.memoryStateTime::ACT 98247859258 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -416,48 +419,48 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 113114 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 113114 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 113114 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 113114 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 113114 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walksPending::samples 1113616699016 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.572841 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.494666 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 475691482516 42.72% 42.72% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 637925216500 57.28% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 1113616699016 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 82726 84.85% 84.85% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 14770 15.15% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 97496 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 113114 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 112814 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 112814 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 112814 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 112814 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 112814 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 1116892952476 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.571172 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.494909 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 478954833976 42.88% 42.88% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 637938118500 57.12% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 1116892952476 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 81756 84.41% 84.41% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 15104 15.59% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 96860 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 112814 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 113114 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 97496 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 112814 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 96860 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 97496 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 210610 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 96860 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 209674 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 78321186 # DTB read hits -system.cpu0.dtb.read_misses 84847 # DTB read misses -system.cpu0.dtb.write_hits 71529400 # DTB write hits -system.cpu0.dtb.write_misses 28267 # DTB write misses +system.cpu0.dtb.read_hits 78427319 # DTB read hits +system.cpu0.dtb.read_misses 84483 # DTB read misses +system.cpu0.dtb.write_hits 71558713 # DTB write hits +system.cpu0.dtb.write_misses 28331 # DTB write misses system.cpu0.dtb.flush_tlb 1285 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 20997 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 507 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 51007 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 21339 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 502 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 51365 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 4028 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 3702 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 9780 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 78406033 # DTB read accesses -system.cpu0.dtb.write_accesses 71557667 # DTB write accesses +system.cpu0.dtb.perms_faults 9826 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 78511802 # DTB read accesses +system.cpu0.dtb.write_accesses 71587044 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 149850586 # DTB hits -system.cpu0.dtb.misses 113114 # DTB misses -system.cpu0.dtb.accesses 149963700 # DTB accesses +system.cpu0.dtb.hits 149986032 # DTB hits +system.cpu0.dtb.misses 112814 # DTB misses +system.cpu0.dtb.accesses 150098846 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -487,585 +490,585 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 63285 # Table walker walks requested -system.cpu0.itb.walker.walksLong 63285 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walkWaitTime::samples 63285 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 63285 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 63285 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walksPending::samples 1113616695516 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.572887 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.494659 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 475639854016 42.71% 42.71% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 637976841500 57.29% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 1113616695516 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 55054 95.20% 95.20% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 2776 4.80% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 57830 # Table walker page sizes translated +system.cpu0.itb.walker.walks 63116 # Table walker walks requested +system.cpu0.itb.walker.walksLong 63116 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walkWaitTime::samples 63116 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 63116 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 63116 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 1116892951476 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.571207 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.494904 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 478916115976 42.88% 42.88% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 637976835500 57.12% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 1116892951476 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 54727 95.15% 95.15% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 2791 4.85% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 57518 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 63285 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 63285 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 63116 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 63116 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 57830 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 57830 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 121115 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 419986176 # ITB inst hits -system.cpu0.itb.inst_misses 63285 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 57518 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 57518 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 120634 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 420544157 # ITB inst hits +system.cpu0.itb.inst_misses 63116 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 1285 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 20997 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 507 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 35884 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 21339 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 502 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 35909 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 420049461 # ITB inst accesses -system.cpu0.itb.hits 419986176 # DTB hits -system.cpu0.itb.misses 63285 # DTB misses -system.cpu0.itb.accesses 420049461 # DTB accesses -system.cpu0.numCycles 505091044 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 420607273 # ITB inst accesses +system.cpu0.itb.hits 420544157 # DTB hits +system.cpu0.itb.misses 63116 # DTB misses +system.cpu0.itb.accesses 420607273 # DTB accesses +system.cpu0.numCycles 505895917 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 419794202 # Number of instructions committed -system.cpu0.committedOps 493796806 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 453197936 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 421943 # Number of float alu accesses -system.cpu0.num_func_calls 25265539 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 63928321 # number of instructions that are conditional controls -system.cpu0.num_int_insts 453197936 # number of integer instructions -system.cpu0.num_fp_insts 421943 # number of float instructions -system.cpu0.num_int_register_reads 668318275 # number of times the integer registers were read -system.cpu0.num_int_register_writes 360308744 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 682016 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 353392 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 110766057 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 110481712 # number of times the CC registers were written -system.cpu0.num_mem_refs 149944655 # number of memory refs -system.cpu0.num_load_insts 78394551 # Number of load instructions -system.cpu0.num_store_insts 71550104 # Number of store instructions -system.cpu0.num_idle_cycles 493080351.361326 # Number of idle cycles -system.cpu0.num_busy_cycles 12010692.638674 # Number of busy cycles -system.cpu0.not_idle_fraction 0.023779 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.976221 # Percentage of idle cycles -system.cpu0.Branches 93737042 # Number of branches fetched +system.cpu0.committedInsts 420346594 # Number of instructions committed +system.cpu0.committedOps 494579830 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 453915139 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 407993 # Number of float alu accesses +system.cpu0.num_func_calls 25255441 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 64064604 # number of instructions that are conditional controls +system.cpu0.num_int_insts 453915139 # number of integer instructions +system.cpu0.num_fp_insts 407993 # number of float instructions +system.cpu0.num_int_register_reads 669796814 # number of times the integer registers were read +system.cpu0.num_int_register_writes 361015506 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 660600 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 338556 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 110996958 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 110750515 # number of times the CC registers were written +system.cpu0.num_mem_refs 150079107 # number of memory refs +system.cpu0.num_load_insts 78499668 # Number of load instructions +system.cpu0.num_store_insts 71579439 # Number of store instructions +system.cpu0.num_idle_cycles 493874204.516617 # Number of idle cycles +system.cpu0.num_busy_cycles 12021712.483383 # Number of busy cycles +system.cpu0.not_idle_fraction 0.023763 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.976237 # Percentage of idle cycles +system.cpu0.Branches 93830955 # Number of branches fetched system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 342973363 69.42% 69.42% # Class of executed instruction -system.cpu0.op_class::IntMult 1071330 0.22% 69.63% # Class of executed instruction -system.cpu0.op_class::IntDiv 48623 0.01% 69.64% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.64% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.64% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.64% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.64% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.64% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.64% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.64% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.64% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.64% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.64% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.64% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.64% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.64% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.64% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.64% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.64% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.64% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.64% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.64% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.64% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.64% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.64% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 51721 0.01% 69.65% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.65% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.65% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.65% # Class of executed instruction -system.cpu0.op_class::MemRead 78394551 15.87% 85.52% # Class of executed instruction -system.cpu0.op_class::MemWrite 71550104 14.48% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 343614791 69.43% 69.43% # Class of executed instruction +system.cpu0.op_class::IntMult 1086596 0.22% 69.65% # Class of executed instruction +system.cpu0.op_class::IntDiv 48369 0.01% 69.66% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.66% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.66% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.66% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.66% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.66% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.66% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.66% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.66% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.66% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.66% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.66% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.66% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.66% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.66% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.66% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.66% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.66% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.66% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.66% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.66% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.66% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.66% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 49130 0.01% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::MemRead 78499668 15.86% 85.54% # Class of executed instruction +system.cpu0.op_class::MemWrite 71579439 14.46% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 494089735 # Class of executed instruction +system.cpu0.op_class::total 494878036 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 16313 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 10220953 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.999720 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 305187926 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 10221465 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 29.857552 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 16312 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 10193982 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.999718 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 304221340 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 10194494 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 29.841730 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.221457 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 6.755911 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 8.022352 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.971136 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.013195 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.015669 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 495.636821 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 5.388351 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 10.974546 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.968041 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.010524 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.021435 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 204 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 295 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1297346809 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1297346809 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 73103498 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 24004695 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 59713819 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 156822012 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 67621876 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 22136915 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 50273570 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 140032361 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 191205 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 58550 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 144781 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 394536 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 151179 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data 54099 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu2.data 126065 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 331343 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1805832 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 567281 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 1240318 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 3613431 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1916828 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 614023 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 1418006 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 3948857 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 140725374 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 46141610 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 109987389 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 296854373 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 140916579 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 46200160 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 110132170 # number of overall hits -system.cpu0.dcache.overall_hits::total 297248909 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 2537446 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 778664 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 4676407 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 7992517 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1084233 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 329896 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 4337927 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 5752056 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 625359 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 184328 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu2.data 464541 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 1274228 # number of SoftPFReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 751309 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu1.data 143971 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu2.data 338834 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 1234114 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 111816 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 47069 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 226989 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 385874 # number of LoadLockedReq misses +system.cpu0.dcache.tags.tag_accesses 1293146150 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 1293146150 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 73192810 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 24078178 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 59062839 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 156333827 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 67632120 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 22097804 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 49843167 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 139573091 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 193481 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 58228 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu2.data 144072 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 395781 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 150752 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu1.data 54007 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu2.data 125506 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 330265 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1823556 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 547758 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 1229270 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 3600584 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1933646 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 595016 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 1413472 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 3942134 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 140824930 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 46175982 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 108906006 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 295906918 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 141018411 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 46234210 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 109050078 # number of overall hits +system.cpu0.dcache.overall_hits::total 296302699 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 2530012 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 810343 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 4548856 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 7889211 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1084459 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 324852 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 4363130 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 5772441 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 629295 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 177552 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu2.data 467332 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 1274179 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 753152 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu1.data 142541 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu2.data 338665 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 1234358 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 110926 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 47584 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 233520 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 392030 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu1.data 2 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu2.data 2 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3621679 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 1108560 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 9014334 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 13744573 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 4247038 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 1292888 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 9478875 # number of overall misses -system.cpu0.dcache.overall_misses::total 15018801 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 12082220500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 71708819033 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 83791039533 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 9788716367 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 139964630413 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 149753346780 # number of WriteReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu1.data 2906340501 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu2.data 7459202639 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 10365543140 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 670206750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 2926933738 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 3597140488 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_misses::cpu2.data 7 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 9 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3614471 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 1135195 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 8911986 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 13661652 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 4243766 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 1312747 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 9379318 # number of overall misses +system.cpu0.dcache.overall_misses::total 14935831 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 12443944000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 69833838000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 82277782000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 9722892000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 137997538214 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 147720430214 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data 3829880000 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu2.data 11756491801 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 15586371801 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 699957500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 2904634000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 3604591500 # number of LoadLockedReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 164000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 26000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 190000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 21870936867 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 211673449446 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 233544386313 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 21870936867 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 211673449446 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 233544386313 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 75640944 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 24783359 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 64390226 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 164814529 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 68706109 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 22466811 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 54611497 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 145784417 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 816564 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 242878 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 609322 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 1668764 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 902488 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu1.data 198070 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu2.data 464899 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 1565457 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1917648 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 614350 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 1467307 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 3999305 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1916828 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 614025 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 1418008 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 3948861 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 144347053 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 47250170 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 119001723 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 310598946 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 145163617 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 47493048 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 119611045 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 312267710 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033546 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.031419 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.072626 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.048494 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.015781 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014684 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.079432 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.039456 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.765842 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.758932 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.762390 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.763576 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.832486 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.726869 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu2.data 0.728834 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.788341 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.058309 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.076616 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.154698 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.096485 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 111000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 275000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 22166836000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 207831376214 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 229998212214 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 22166836000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 207831376214 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 229998212214 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 75722822 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 24888521 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 63611695 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 164223038 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 68716579 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 22422656 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 54206297 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 145345532 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 822776 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 235780 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 611404 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 1669960 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 903904 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu1.data 196548 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu2.data 464171 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 1564623 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1934482 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 595342 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 1462790 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 3992614 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1933646 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 595018 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 1413479 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 3942143 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 144439401 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 47311177 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 117817992 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 309568570 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 145262177 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 47546957 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 118429396 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 311238530 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033411 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.032559 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.071510 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.048040 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.015782 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014488 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.080491 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.039715 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.764844 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.753041 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.764359 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.763000 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.833221 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.725222 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu2.data 0.729613 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.788917 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.057341 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.079927 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.159640 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.098189 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000003 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000001 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025090 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.023462 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.075750 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.044252 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029257 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.027223 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.079247 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.048096 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15516.603439 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15334.169809 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 10483.686120 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 29672.128086 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32265.326367 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 26034.751188 # average WriteReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 20186.985580 # average WriteInvalidateReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu2.data 22014.327485 # average WriteInvalidateReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 8399.177985 # average WriteInvalidateReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14238.814294 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 12894.606073 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9322.059760 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000005 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025024 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.023994 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.075642 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.044131 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029215 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.027609 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.079198 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.047988 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15356.391059 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15351.956184 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 10429.152167 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 29930.220531 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 31628.106019 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 25590.634918 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 26868.620257 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu2.data 34714.221431 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 12627.108020 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14709.934011 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 12438.480644 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9194.682805 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 82000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 47500 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 19729.141289 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 23481.873364 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 16991.752768 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16916.342999 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 22331.072986 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 15550.135215 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 14700393 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 25808 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 1130734 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 457 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.000753 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 56.472648 # average number of cycles each access was blocked +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 15857.142857 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 30555.555556 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 19526.897141 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 23320.433427 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 16835.314808 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16885.840150 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 22158.474232 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 15399.090430 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 17007920 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 25831 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 1141319 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 442 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.901986 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 58.441176 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 7872498 # number of writebacks -system.cpu0.dcache.writebacks::total 7872498 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 2189 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 2608868 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 2611057 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1745 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 3598244 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 3599989 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu2.data 2407 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 2407 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 10418 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 138207 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 148625 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 3934 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 6207112 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 6211046 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 3934 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 6207112 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 6211046 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 776475 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 2067539 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 2844014 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 328151 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 739683 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1067834 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 184212 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 454745 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 638957 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 143971 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu2.data 336427 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 480398 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 36651 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 88782 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 125433 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.writebacks::writebacks 7849789 # number of writebacks +system.cpu0.dcache.writebacks::total 7849789 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 2357 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 2525238 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 2527595 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1733 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 3623036 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 3624769 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu2.data 2374 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 2374 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 10549 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 144753 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 155302 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 4090 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 6148274 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 6152364 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 4090 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 6148274 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 6152364 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 807986 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 2023618 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 2831604 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 323119 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 740094 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1063213 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 177438 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 455361 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 632799 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data 142541 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu2.data 336291 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 478832 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 37035 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 88767 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 125802 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 2 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 2 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 1104626 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 2807222 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 3911848 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 1288838 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 3261967 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 4550805 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 5448 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 8279 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 13727 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 5373 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 7916 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 13289 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 10821 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 16195 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 27016 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 10846992750 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 30627833111 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 41474825861 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 9219061633 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 24093607640 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 33312669273 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 2717019500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 8086528259 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 10803547759 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 2690383999 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu2.data 6865304661 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 9555688660 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 463968000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 1147138011 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1611106011 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 161000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 23000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 184000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 20066054383 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 54721440751 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 74787495134 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 22783073883 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 62807969010 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 85591042893 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 895108750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1474898001 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2370006751 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 895104500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1438317956 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2333422456 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1790213250 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 2913215957 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4703429207 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.031330 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.032110 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017256 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014606 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.013544 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007325 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.758455 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.746313 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.382892 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.726869 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu2.data 0.723656 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.306874 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.059658 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.060507 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.031364 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 7 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 9 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 1131105 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 2763712 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 3894817 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 1308543 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 3219073 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 4527616 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 4998 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 8152 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 13150 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 4942 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 7788 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 12730 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 9940 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 15940 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 25880 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 11585855500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 31062083000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 42647938500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 9355442500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 24215406665 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 33570849165 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 2741056000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 8202281000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 10943337000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 3687339000 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu2.data 11324765301 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 15012104301 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 496140000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 1176567000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1672707000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 162000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 104000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 266000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 20941298000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 55277489665 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 76218787665 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 23682354000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 63479770665 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 87162124665 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 826187000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1474974000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2301161000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 827724000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1436870963 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2264594963 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1653911000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 2911844963 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4565755963 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032464 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.031812 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017242 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014410 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.013653 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007315 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.752557 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.744779 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.378931 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.725222 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data 0.724498 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.306037 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.062208 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.060683 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.031509 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000003 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.023378 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.023590 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.012595 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.027137 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.027271 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.014573 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13969.532503 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14813.666446 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14583.200315 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28093.961722 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32572.882762 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31196.486788 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14749.416433 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 17782.555628 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16908.098290 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 18686.985567 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu2.data 20406.521061 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 19891.191595 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12659.081608 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12920.839934 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12844.355241 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 80500 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11500 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 46000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18165.473548 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19493.093439 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19118.200690 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17677.220786 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19254.630415 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18807.890668 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164300.431351 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 178149.293514 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172652.928608 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 166593.057882 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 181697.568974 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 175590.522688 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 165438.799556 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 179883.665144 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 174097.912607 # average overall mshr uncacheable latency +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000005 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.023908 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.023457 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.012581 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.027521 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.027181 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.014547 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14339.178525 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15349.775995 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15061.406362 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28953.551168 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32719.366276 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31574.904713 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15447.964923 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 18012.699814 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17293.543447 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 25868.620257 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 33675.493251 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31351.505958 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13396.516808 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 13254.554057 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13296.346640 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 81000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 14857.142857 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 29555.555556 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18514.017708 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20001.175833 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19569.285968 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18098.261960 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19719.891616 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19251.218448 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 165303.521409 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 180934.003925 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 174993.231939 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 167487.656819 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 184498.069209 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 177894.341163 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 166389.436620 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 182675.342723 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 176420.245866 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 14550991 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.976833 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 611237841 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 14551503 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 42.005135 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 9058621500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 496.705744 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 5.210417 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 10.060673 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.970128 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.010177 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.019650 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 14504187 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.976820 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 610702941 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 14504699 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 42.103800 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 9090101500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 497.013968 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 4.629060 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 10.333792 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.970730 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.009041 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.020183 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999955 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 79 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 173 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 87 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 640780747 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 640780747 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 413451033 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 134065919 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 63720889 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 611237841 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 413451033 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 134065919 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 63720889 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 611237841 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 413451033 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 134065919 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 63720889 # number of overall hits -system.cpu0.icache.overall_hits::total 611237841 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 6592973 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 2115468 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 6282843 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 14991284 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 6592973 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 2115468 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 6282843 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 14991284 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 6592973 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 2115468 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 6282843 # number of overall misses -system.cpu0.icache.overall_misses::total 14991284 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 28339007992 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 82279227443 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 110618235435 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 28339007992 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 82279227443 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 110618235435 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 28339007992 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 82279227443 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 110618235435 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 420044006 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 136181387 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 70003732 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 626229125 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 420044006 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 136181387 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 70003732 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 626229125 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 420044006 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 136181387 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 70003732 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 626229125 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015696 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015534 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.089750 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.023939 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015696 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015534 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.089750 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.023939 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015696 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015534 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.089750 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.023939 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13396.093910 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13095.859222 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 7378.836625 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13396.093910 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13095.859222 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 7378.836625 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13396.093910 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13095.859222 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 7378.836625 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 51965 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 640161996 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 640161996 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 414014521 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 133530266 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 63158154 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 610702941 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 414014521 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 133530266 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 63158154 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 610702941 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 414014521 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 133530266 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 63158154 # number of overall hits +system.cpu0.icache.overall_hits::total 610702941 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 6587154 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 2095893 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 6271180 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 14954227 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 6587154 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 2095893 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 6271180 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 14954227 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 6587154 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 2095893 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 6271180 # number of overall misses +system.cpu0.icache.overall_misses::total 14954227 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 28071619000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 82050168313 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 110121787313 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 28071619000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 82050168313 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 110121787313 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 28071619000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 82050168313 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 110121787313 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 420601675 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 135626159 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 69429334 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 625657168 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 420601675 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 135626159 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 69429334 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 625657168 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 420601675 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 135626159 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 69429334 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 625657168 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015661 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015453 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.090325 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.023902 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015661 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015453 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.090325 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.023902 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015661 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015453 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.090325 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.023902 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13393.631736 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13083.688925 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 7363.923746 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13393.631736 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13083.688925 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 7363.923746 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13393.631736 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13083.688925 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 7363.923746 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 53098 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 3925 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 4092 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.239490 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 12.976051 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 439662 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 439662 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 439662 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 439662 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 439662 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 439662 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 2115468 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 5843181 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 7958649 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 2115468 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 5843181 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 7958649 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 2115468 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 5843181 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 7958649 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 25161480508 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 69932206790 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 95093687298 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 25161480508 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 69932206790 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 95093687298 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 25161480508 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 69932206790 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 95093687298 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015534 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.083470 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.012709 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015534 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.083470 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.012709 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015534 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.083470 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.012709 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11894.049217 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11968.173977 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11948.471066 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11894.049217 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11968.173977 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11948.471066 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11894.049217 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11968.173977 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11948.471066 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 449399 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 449399 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 449399 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 449399 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 449399 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 449399 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 2095893 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 5821781 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 7917674 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 2095893 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 5821781 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 7917674 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 2095893 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 5821781 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 7917674 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 25975726000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 72655138349 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 98630864349 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 25975726000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 72655138349 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 98630864349 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 25975726000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 72655138349 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 98630864349 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015453 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.083852 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.012655 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015453 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.083852 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.012655 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015453 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.083852 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.012655 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12393.631736 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12479.881732 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12457.050435 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12393.631736 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12479.881732 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12457.050435 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12393.631736 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12479.881732 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12457.050435 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1096,70 +1099,69 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 40069 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 40069 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 6011 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 28822 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 3 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 40066 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 0.287026 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 57.452621 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-1023 40065 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walks 40125 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 40125 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 6166 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 29054 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 2 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 40123 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.299080 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 59.907962 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-1023 40122 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::11264-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 40066 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 34836 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 23148.919221 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 19687.951217 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 13456.896972 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 22742 65.28% 65.28% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 11809 33.90% 99.18% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-98303 149 0.43% 99.61% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-131071 100 0.29% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-163839 2 0.01% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::163840-196607 13 0.04% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-229375 2 0.01% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::229376-262143 8 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-294911 9 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::294912-327679 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkWaitTime::total 40123 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 35222 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 25010.164102 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 22134.109650 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 13083.481555 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 22653 64.31% 64.31% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 12324 34.99% 99.30% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 130 0.37% 99.67% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 82 0.23% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-196607 11 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-229375 3 0.01% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::229376-262143 6 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 7 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-360447 5 0.01% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 34836 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 2552299344 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.586801 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.492408 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1054607500 41.32% 41.32% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 1497691844 58.68% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 2552299344 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 28822 82.74% 82.74% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 6011 17.26% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 34833 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 40069 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkCompletionTime::total 35222 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -2750429288 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 1.373730 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1027918000 -37.37% -37.37% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 -3778347288 137.37% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -2750429288 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 29054 82.49% 82.49% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 6166 17.51% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 35220 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 40125 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 40069 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 34833 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 40125 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 35220 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 34833 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 74902 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 35220 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 75345 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25646035 # DTB read hits -system.cpu1.dtb.read_misses 30818 # DTB read misses -system.cpu1.dtb.write_hits 23287178 # DTB write hits -system.cpu1.dtb.write_misses 9251 # DTB write misses -system.cpu1.dtb.flush_tlb 1276 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 25724641 # DTB read hits +system.cpu1.dtb.read_misses 30962 # DTB read misses +system.cpu1.dtb.write_hits 23221976 # DTB write hits +system.cpu1.dtb.write_misses 9163 # DTB write misses +system.cpu1.dtb.flush_tlb 1277 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 6462 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 159 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 22057 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 6096 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 163 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 21958 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 1362 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 1268 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 2875 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25676853 # DTB read accesses -system.cpu1.dtb.write_accesses 23296429 # DTB write accesses +system.cpu1.dtb.perms_faults 2784 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25755603 # DTB read accesses +system.cpu1.dtb.write_accesses 23231139 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 48933213 # DTB hits -system.cpu1.dtb.misses 40069 # DTB misses -system.cpu1.dtb.accesses 48973282 # DTB accesses +system.cpu1.dtb.hits 48946617 # DTB hits +system.cpu1.dtb.misses 40125 # DTB misses +system.cpu1.dtb.accesses 48986742 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1189,137 +1191,135 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 23826 # Table walker walks requested -system.cpu1.itb.walker.walksLong 23826 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 1156 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 20921 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 23826 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 23826 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 23826 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 22077 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 26240.136794 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 22930.281403 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 15976.450560 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-32767 11277 51.08% 51.08% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-65535 10485 47.49% 98.57% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-98303 121 0.55% 99.12% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::98304-131071 153 0.69% 99.81% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-163839 3 0.01% 99.83% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::163840-196607 13 0.06% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-229375 7 0.03% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::229376-262143 4 0.02% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-294911 4 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::294912-327679 2 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-360447 4 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::360448-393215 1 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-425983 2 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 22077 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 23205 # Table walker walks requested +system.cpu1.itb.walker.walksLong 23205 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 1161 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 20405 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 23205 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 23205 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 23205 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 21566 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 27973.105815 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 25131.407006 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 15236.984733 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 11031 51.15% 51.15% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 10248 47.52% 98.67% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 108 0.50% 99.17% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 142 0.66% 99.83% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 2 0.01% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 12 0.06% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 2 0.01% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 10 0.05% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 2 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 6 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 2 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 21566 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 20921 94.76% 94.76% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 1156 5.24% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 22077 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 20405 94.62% 94.62% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 1161 5.38% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 21566 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 23826 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 23826 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 23205 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 23205 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 22077 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 22077 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 45903 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 136181387 # ITB inst hits -system.cpu1.itb.inst_misses 23826 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 21566 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 21566 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 44771 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 135626159 # ITB inst hits +system.cpu1.itb.inst_misses 23205 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1276 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 1277 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 6462 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 159 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 16176 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 6096 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 163 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 16107 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 136205213 # ITB inst accesses -system.cpu1.itb.hits 136181387 # DTB hits -system.cpu1.itb.misses 23826 # DTB misses -system.cpu1.itb.accesses 136205213 # DTB accesses -system.cpu1.numCycles 1276125055 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 135649364 # ITB inst accesses +system.cpu1.itb.hits 135626159 # DTB hits +system.cpu1.itb.misses 23205 # DTB misses +system.cpu1.itb.accesses 135649364 # DTB accesses +system.cpu1.numCycles 1276121974 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 136088494 # Number of instructions committed -system.cpu1.committedOps 159971532 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 146914767 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 136439 # Number of float alu accesses -system.cpu1.num_func_calls 8067189 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 20777484 # number of instructions that are conditional controls -system.cpu1.num_int_insts 146914767 # number of integer instructions -system.cpu1.num_fp_insts 136439 # number of float instructions -system.cpu1.num_int_register_reads 213265371 # number of times the integer registers were read -system.cpu1.num_int_register_writes 116491926 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 215836 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 125376 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 35465151 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 35400633 # number of times the CC registers were written -system.cpu1.num_mem_refs 48930269 # number of memory refs -system.cpu1.num_load_insts 25645213 # Number of load instructions -system.cpu1.num_store_insts 23285056 # Number of store instructions -system.cpu1.num_idle_cycles 1249288140.787440 # Number of idle cycles -system.cpu1.num_busy_cycles 26836914.212560 # Number of busy cycles -system.cpu1.not_idle_fraction 0.021030 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.978970 # Percentage of idle cycles -system.cpu1.Branches 30426471 # Number of branches fetched +system.cpu1.committedInsts 135538016 # Number of instructions committed +system.cpu1.committedOps 159130731 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 146160247 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 138681 # Number of float alu accesses +system.cpu1.num_func_calls 7978033 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 20702063 # number of instructions that are conditional controls +system.cpu1.num_int_insts 146160247 # number of integer instructions +system.cpu1.num_fp_insts 138681 # number of float instructions +system.cpu1.num_int_register_reads 211618661 # number of times the integer registers were read +system.cpu1.num_int_register_writes 115744147 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 219623 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 127108 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 35291781 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 35222922 # number of times the CC registers were written +system.cpu1.num_mem_refs 48943439 # number of memory refs +system.cpu1.num_load_insts 25723579 # Number of load instructions +system.cpu1.num_store_insts 23219860 # Number of store instructions +system.cpu1.num_idle_cycles 1249309266.868014 # Number of idle cycles +system.cpu1.num_busy_cycles 26812707.131986 # Number of busy cycles +system.cpu1.not_idle_fraction 0.021011 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.978989 # Percentage of idle cycles +system.cpu1.Branches 30260595 # Number of branches fetched system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 110766463 69.20% 69.20% # Class of executed instruction -system.cpu1.op_class::IntMult 334649 0.21% 69.41% # Class of executed instruction -system.cpu1.op_class::IntDiv 13512 0.01% 69.42% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.42% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.42% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.42% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.42% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.42% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.42% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.42% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.42% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.42% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.42% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.42% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.42% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.42% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.42% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.42% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.42% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 19532 0.01% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::MemRead 25645213 16.02% 85.45% # Class of executed instruction -system.cpu1.op_class::MemWrite 23285056 14.55% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 109906813 69.03% 69.03% # Class of executed instruction +system.cpu1.op_class::IntMult 333855 0.21% 69.24% # Class of executed instruction +system.cpu1.op_class::IntDiv 14527 0.01% 69.25% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.25% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.25% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.25% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.25% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.25% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.25% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.25% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.25% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.25% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.25% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.25% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.25% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.25% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.25% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.25% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.25% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.25% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.25% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.25% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.25% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.25% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.25% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 20240 0.01% 69.26% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.26% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.26% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.26% # Class of executed instruction +system.cpu1.op_class::MemRead 25723579 16.16% 85.42% # Class of executed instruction +system.cpu1.op_class::MemWrite 23219860 14.58% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 160064425 # Class of executed instruction +system.cpu1.op_class::total 159218874 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 97087615 # Number of BP lookups -system.cpu2.branchPred.condPredicted 66103650 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 4347660 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 66231841 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 47108077 # Number of BTB hits +system.cpu2.branchPred.lookups 96379868 # Number of BP lookups +system.cpu2.branchPred.condPredicted 65507682 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 4329047 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 66096416 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 46823178 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 71.126027 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 12454763 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 133862 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 70.840722 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 12400698 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 133614 # Number of incorrect RAS predictions. system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1349,88 +1349,86 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.dtb.walker.walks 649855 # Table walker walks requested -system.cpu2.dtb.walker.walksLong 649855 # Table walker walks initiated with long descriptors -system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 11017 # Level at which table walker walks with long descriptors terminate -system.cpu2.dtb.walker.walksLongTerminationLevel::Level3 66935 # Level at which table walker walks with long descriptors terminate -system.cpu2.dtb.walker.walksSquashedBefore 396890 # Table walks squashed before starting -system.cpu2.dtb.walker.walkWaitTime::samples 252965 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::mean 2053.590418 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::stdev 12193.038070 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::0-65535 251454 99.40% 99.40% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::65536-131071 1182 0.47% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::131072-196607 177 0.07% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::196608-262143 62 0.02% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::262144-327679 45 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walks 662632 # Table walker walks requested +system.cpu2.dtb.walker.walksLong 662632 # Table walker walks initiated with long descriptors +system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 11252 # Level at which table walker walks with long descriptors terminate +system.cpu2.dtb.walker.walksLongTerminationLevel::Level3 67139 # Level at which table walker walks with long descriptors terminate +system.cpu2.dtb.walker.walksSquashedBefore 410741 # Table walks squashed before starting +system.cpu2.dtb.walker.walkWaitTime::samples 251891 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::mean 2203.738919 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::stdev 12798.903480 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::0-65535 250391 99.40% 99.40% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::65536-131071 1085 0.43% 99.84% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::131072-196607 243 0.10% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::196608-262143 75 0.03% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::262144-327679 48 0.02% 99.98% # Table walker wait (enqueue to first request) latency system.cpu2.dtb.walker.walkWaitTime::327680-393215 26 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::393216-458751 17 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::total 252965 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkCompletionTime::samples 293492 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::mean 21382.093181 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::gmean 17292.884496 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::stdev 15231.620197 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::0-65535 288902 98.44% 98.44% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::65536-131071 4097 1.40% 99.83% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::131072-196607 265 0.09% 99.92% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::196608-262143 159 0.05% 99.98% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::262144-327679 56 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::327680-393215 9 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::total 293492 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walksPending::samples 636867012660 # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::mean 0.530422 # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::stdev 0.615162 # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::0-3 636197778160 99.89% 99.89% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::4-7 383895000 0.06% 99.96% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::8-11 122059000 0.02% 99.97% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::12-15 78250500 0.01% 99.99% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::16-19 30640500 0.00% 99.99% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::20-23 15817000 0.00% 99.99% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::24-27 14461500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::28-31 20012000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::32-35 3793500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::36-39 253000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::40-43 22000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::44-47 10000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::48-51 6500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::52-55 3000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::56-59 11000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::total 636867012660 # Table walker pending requests distribution -system.cpu2.dtb.walker.walkPageSizes::4K 66935 85.87% 85.87% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::2M 11017 14.13% 100.00% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::total 77952 # Table walker page sizes translated -system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 649855 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkWaitTime::393216-458751 21 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::total 251891 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkCompletionTime::samples 304707 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::mean 22494.824536 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::gmean 18425.462627 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::stdev 15718.326432 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::0-65535 298255 97.88% 97.88% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::65536-131071 5951 1.95% 99.84% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::131072-196607 243 0.08% 99.92% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::196608-262143 191 0.06% 99.98% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::262144-327679 38 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::327680-393215 19 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::393216-458751 5 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::total 304707 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walksPending::samples 640151154620 # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::mean 0.510260 # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::stdev 0.628480 # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::0-3 639427998620 99.89% 99.89% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::4-7 404049000 0.06% 99.95% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::8-11 134377500 0.02% 99.97% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::12-15 87391000 0.01% 99.98% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::16-19 34713500 0.01% 99.99% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::20-23 17695000 0.00% 99.99% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::24-27 17014000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::28-31 22612000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::32-35 4758500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::36-39 448500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::40-43 50500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::44-47 27500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::48-51 19000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::total 640151154620 # Table walker pending requests distribution +system.cpu2.dtb.walker.walkPageSizes::4K 67139 85.65% 85.65% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::2M 11252 14.35% 100.00% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::total 78391 # Table walker page sizes translated +system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 662632 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 649855 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 77952 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 662632 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 78391 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 77952 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin::total 727807 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 78391 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin::total 741023 # Table walker requests started/completed, data/inst system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 77417011 # DTB read hits -system.cpu2.dtb.read_misses 450124 # DTB read misses -system.cpu2.dtb.write_hits 59942200 # DTB write hits -system.cpu2.dtb.write_misses 199731 # DTB write misses -system.cpu2.dtb.flush_tlb 1277 # Number of times complete TLB was flushed +system.cpu2.dtb.read_hits 76683824 # DTB read hits +system.cpu2.dtb.read_misses 455088 # DTB read misses +system.cpu2.dtb.write_hits 59509350 # DTB write hits +system.cpu2.dtb.write_misses 207544 # DTB write misses +system.cpu2.dtb.flush_tlb 1276 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 14741 # Number of times TLB was flushed by MVA & ASID -system.cpu2.dtb.flush_tlb_asid 389 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 38279 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 93 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 6471 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_tlb_mva_asid 14760 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_asid 390 # Number of times TLB was flushed by ASID +system.cpu2.dtb.flush_entries 38772 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 82 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 6499 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 38915 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 77867135 # DTB read accesses -system.cpu2.dtb.write_accesses 60141931 # DTB write accesses +system.cpu2.dtb.perms_faults 41159 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 77138912 # DTB read accesses +system.cpu2.dtb.write_accesses 59716894 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 137359211 # DTB hits -system.cpu2.dtb.misses 649855 # DTB misses -system.cpu2.dtb.accesses 138009066 # DTB accesses +system.cpu2.dtb.hits 136193174 # DTB hits +system.cpu2.dtb.misses 662632 # DTB misses +system.cpu2.dtb.accesses 136855806 # DTB accesses system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1460,395 +1458,394 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.walker.walks 80378 # Table walker walks requested -system.cpu2.itb.walker.walksLong 80378 # Table walker walks initiated with long descriptors -system.cpu2.itb.walker.walksLongTerminationLevel::Level2 2425 # Level at which table walker walks with long descriptors terminate -system.cpu2.itb.walker.walksLongTerminationLevel::Level3 55766 # Level at which table walker walks with long descriptors terminate -system.cpu2.itb.walker.walksSquashedBefore 10589 # Table walks squashed before starting -system.cpu2.itb.walker.walkWaitTime::samples 69789 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::mean 1377.194114 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::stdev 8185.559112 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::0-32767 69315 99.32% 99.32% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::32768-65535 221 0.32% 99.64% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::65536-98303 162 0.23% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::98304-131071 61 0.09% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::131072-163839 8 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::163840-196607 9 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::196608-229375 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::229376-262143 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::262144-294911 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::294912-327679 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::total 69789 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkCompletionTime::samples 68780 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::mean 26602.237307 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::gmean 22568.644275 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::stdev 16910.110071 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::0-32767 37031 53.84% 53.84% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::32768-65535 30619 44.52% 98.36% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::65536-98303 406 0.59% 98.95% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::98304-131071 526 0.76% 99.71% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::131072-163839 70 0.10% 99.81% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::163840-196607 66 0.10% 99.91% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::196608-229375 22 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::229376-262143 14 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::262144-294911 9 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::294912-327679 7 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::327680-360447 2 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::360448-393215 3 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::393216-425983 1 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walks 81585 # Table walker walks requested +system.cpu2.itb.walker.walksLong 81585 # Table walker walks initiated with long descriptors +system.cpu2.itb.walker.walksLongTerminationLevel::Level2 2498 # Level at which table walker walks with long descriptors terminate +system.cpu2.itb.walker.walksLongTerminationLevel::Level3 56536 # Level at which table walker walks with long descriptors terminate +system.cpu2.itb.walker.walksSquashedBefore 10896 # Table walks squashed before starting +system.cpu2.itb.walker.walkWaitTime::samples 70689 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::mean 1473.991710 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::stdev 8586.891139 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::0-32767 70027 99.06% 99.06% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::32768-65535 428 0.61% 99.67% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::65536-98303 144 0.20% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::98304-131071 50 0.07% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::131072-163839 13 0.02% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::163840-196607 13 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::196608-229375 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::229376-262143 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::262144-294911 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::294912-327679 5 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::total 70689 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkCompletionTime::samples 69930 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::mean 28234.749035 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::gmean 24509.520790 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::stdev 16350.855698 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::0-32767 36490 52.18% 52.18% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::32768-65535 32158 45.99% 98.17% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::65536-98303 628 0.90% 99.06% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::98304-131071 491 0.70% 99.77% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::131072-163839 45 0.06% 99.83% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::163840-196607 57 0.08% 99.91% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::196608-229375 23 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::229376-262143 10 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::262144-294911 12 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::294912-327679 4 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::327680-360447 6 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::360448-393215 4 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu2.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::458752-491519 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::total 68780 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walksPending::samples 465075818820 # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::mean 0.908790 # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::stdev 0.288323 # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::0 42467517784 9.13% 9.13% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::1 422566839536 90.86% 99.99% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::2 36100000 0.01% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::3 4751500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::4 426500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::5 73000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::6 66000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::7 44500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::total 465075818820 # Table walker pending requests distribution -system.cpu2.itb.walker.walkPageSizes::4K 55766 95.83% 95.83% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::2M 2425 4.17% 100.00% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::total 58191 # Table walker page sizes translated +system.cpu2.itb.walker.walkCompletionTime::total 69930 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walksPending::samples 485530683964 # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::mean 0.892648 # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::stdev 0.309939 # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::0 52174022580 10.75% 10.75% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::1 433310679884 89.24% 99.99% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::2 41019000 0.01% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::3 4632000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::4 311000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::5 12000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::6 6000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::7 1500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::total 485530683964 # Table walker pending requests distribution +system.cpu2.itb.walker.walkPageSizes::4K 56536 95.77% 95.77% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::2M 2498 4.23% 100.00% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::total 59034 # Table walker page sizes translated system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 80378 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::total 80378 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 81585 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::total 81585 # Table walker requests started/completed, data/inst system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 58191 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::total 58191 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin::total 138569 # Table walker requests started/completed, data/inst -system.cpu2.itb.inst_hits 70175055 # ITB inst hits -system.cpu2.itb.inst_misses 80378 # ITB inst misses +system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 59034 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Completed::total 59034 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin::total 140619 # Table walker requests started/completed, data/inst +system.cpu2.itb.inst_hits 69601857 # ITB inst hits +system.cpu2.itb.inst_misses 81585 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses -system.cpu2.itb.flush_tlb 1277 # Number of times complete TLB was flushed +system.cpu2.itb.flush_tlb 1276 # Number of times complete TLB was flushed system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 14741 # Number of times TLB was flushed by MVA & ASID -system.cpu2.itb.flush_tlb_asid 389 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 30057 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_tlb_mva_asid 14760 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_asid 390 # Number of times TLB was flushed by ASID +system.cpu2.itb.flush_entries 30530 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 147979 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 148496 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 70255433 # ITB inst accesses -system.cpu2.itb.hits 70175055 # DTB hits -system.cpu2.itb.misses 80378 # DTB misses -system.cpu2.itb.accesses 70255433 # DTB accesses -system.cpu2.numCycles 460136549 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 69683442 # ITB inst accesses +system.cpu2.itb.hits 69601857 # DTB hits +system.cpu2.itb.misses 81585 # DTB misses +system.cpu2.itb.accesses 69683442 # DTB accesses +system.cpu2.numCycles 461100419 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 178152693 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 431776536 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 97087615 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 59562840 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 255654820 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 9805571 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 1895155 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 7918 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1866 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 3768954 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 115299 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 5484 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 70003785 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 2663761 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 31715 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 444504807 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.135202 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.375157 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 177123206 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 428437277 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 96379868 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 59223876 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 257401667 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 9762973 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 2005280 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 7949 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 2437 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 3773015 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 114784 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 5106 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 69429398 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 2656278 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 32686 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 445314772 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.124877 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.366658 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 338236255 76.09% 76.09% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 13308034 2.99% 79.09% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 13681319 3.08% 82.16% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 9908939 2.23% 84.39% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 20069262 4.51% 88.91% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 6632314 1.49% 90.40% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 7130783 1.60% 92.01% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 6321378 1.42% 93.43% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 29216523 6.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 339836575 76.31% 76.31% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 13185142 2.96% 79.27% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 13574991 3.05% 82.32% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 9797674 2.20% 84.52% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 20004635 4.49% 89.02% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 6578482 1.48% 90.49% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 7061868 1.59% 92.08% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 6288982 1.41% 93.49% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 28986423 6.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 444504807 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.210997 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.938366 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 145587242 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 206867789 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 78822121 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 9322949 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 3902682 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 14396196 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 1015243 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 471778409 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 3111772 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 3902682 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 151005109 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 15075303 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 166939616 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 82595953 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 24983877 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 460482983 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 55875 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 1575989 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 1122405 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 11824382 # Number of times rename has blocked due to SQ full -system.cpu2.rename.FullRegisterEvents 2747 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 440049969 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 701739830 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 543201034 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 591948 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 368298602 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 71751367 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 10111591 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 8659381 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 51276485 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 74779146 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 63098170 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 9504759 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 10253668 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 437555873 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 10088471 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 436351243 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 628919 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 60028880 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 38531819 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 239828 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 444504807 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.981657 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.695270 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 445314772 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.209021 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.929163 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 144945569 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 209061419 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 78115064 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 9308814 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 3881927 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 14332703 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 1014310 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 468249315 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 3113109 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 3881927 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 150342023 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 16281945 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 167363518 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 81901775 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 25541188 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 457027313 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 55411 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 1577150 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 1077305 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 12432724 # Number of times rename has blocked due to SQ full +system.cpu2.rename.FullRegisterEvents 2850 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 436738370 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 696876474 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 538877799 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 611175 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 365603185 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 71135185 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 10148334 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 8698822 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 51282276 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 73817911 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 62641049 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 9297155 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 10241835 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 434108561 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 10116895 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 433413553 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 631683 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 59503474 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 37916216 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 236413 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 445314772 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.973275 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.689353 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 276381275 62.18% 62.18% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 68338590 15.37% 77.55% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 31936602 7.18% 84.74% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 22769301 5.12% 89.86% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 16982310 3.82% 93.68% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 11978521 2.69% 96.37% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 8056839 1.81% 98.19% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 4822285 1.08% 99.27% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 3239084 0.73% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 278168249 62.47% 62.47% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 68048730 15.28% 77.75% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 31692331 7.12% 84.86% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 22597394 5.07% 89.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 16978227 3.81% 93.75% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 11874624 2.67% 96.42% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 7985798 1.79% 98.21% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 4768189 1.07% 99.28% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 3201230 0.72% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 444504807 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 445314772 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 2174414 25.25% 25.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 16907 0.20% 25.44% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 1448 0.02% 25.46% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 25.46% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 25.46% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 25.46% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 25.46% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 25.46% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 25.46% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 25.46% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 25.46% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 25.46% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 25.46% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 25.46% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 25.46% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 25.46% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 25.46% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 25.46% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 25.46% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 25.46% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 25.46% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 25.46% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 25.46% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 25.46% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 25.46% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 25.46% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 25.46% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.46% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 25.46% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 3443156 39.98% 65.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 2977212 34.57% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 2163580 25.08% 25.08% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 17452 0.20% 25.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 1463 0.02% 25.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 25.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 25.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 25.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 25.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 25.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 25.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 25.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 25.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 25.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 25.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 25.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 25.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 25.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 25.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 25.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 25.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 25.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 25.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 25.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 25.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 25.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 25.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 25.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 25.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 25.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 3490107 40.46% 65.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 2952914 34.23% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 20 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 295429003 67.70% 67.70% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 1051015 0.24% 67.95% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 50004 0.01% 67.96% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 103 0.00% 67.96% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 67.96% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 67.96% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 67.96% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 67.96% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 67.96% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 67.96% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 67.96% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 67.96% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 67.96% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 67.96% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 67.96% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 67.96% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 67.96% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 67.96% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.96% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 67.96% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.96% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.96% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.96% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.96% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.96% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 46521 0.01% 67.97% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 67.97% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.97% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.97% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 79012045 18.11% 86.07% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 60762532 13.93% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 293684501 67.76% 67.76% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 1025227 0.24% 68.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 47766 0.01% 68.01% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 317 0.00% 68.01% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 68.01% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 68.01% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 68.01% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 68.01% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 68.01% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 68.01% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 68.01% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 68.01% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 1 0.00% 68.01% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 68.01% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 68.01% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 68.01% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 68.01% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 68.01% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.01% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 68.01% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.01% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.01% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.01% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.01% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.01% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 48576 0.01% 68.02% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 68.02% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.02% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.02% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 78271434 18.06% 86.08% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 60335731 13.92% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 436351243 # Type of FU issued -system.cpu2.iq.rate 0.948308 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 8613137 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.019739 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 1325660566 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 507771301 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 420349481 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 788783 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 391414 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 352523 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 444542452 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 421908 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 3464909 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 433413553 # Type of FU issued +system.cpu2.iq.rate 0.939955 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 8625516 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.019901 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 1320585789 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 503812289 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 417285848 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 813288 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 405263 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 361974 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 441604210 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 434859 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 3381259 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 12199650 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 16692 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 497657 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 6603925 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 11998288 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 16552 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 496769 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 6557326 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 2708670 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 5665546 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 2684885 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 5754188 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 3902682 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 10385108 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 3443992 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 447742813 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 1337786 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 74779146 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 63098170 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 8466807 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 165633 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 3216656 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 497657 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 2020710 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 1734931 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 3755641 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 431226765 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 77404459 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 4484174 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 3881927 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 10679636 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 4407291 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 444323917 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 1337797 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 73817911 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 62641049 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 8508217 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 157244 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 4192594 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 496769 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 2009659 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 1725096 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 3734755 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 428275662 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 76671253 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 4484086 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 98469 # number of nop insts executed -system.cpu2.iew.exec_refs 137346126 # number of memory reference insts executed -system.cpu2.iew.exec_branches 80126150 # Number of branches executed -system.cpu2.iew.exec_stores 59941667 # Number of stores executed -system.cpu2.iew.exec_rate 0.937171 # Inst execution rate -system.cpu2.iew.wb_sent 421619050 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 420702004 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 208179390 # num instructions producing a value -system.cpu2.iew.wb_consumers 361509938 # num instructions consuming a value +system.cpu2.iew.exec_nop 98461 # number of nop insts executed +system.cpu2.iew.exec_refs 136179692 # number of memory reference insts executed +system.cpu2.iew.exec_branches 79539500 # Number of branches executed +system.cpu2.iew.exec_stores 59508439 # Number of stores executed +system.cpu2.iew.exec_rate 0.928812 # Inst execution rate +system.cpu2.iew.wb_sent 418566552 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 417647822 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 206637380 # num instructions producing a value +system.cpu2.iew.wb_consumers 358874398 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.914298 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.575861 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.905763 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.575793 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 60056737 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 9848643 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 3347389 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 434346973 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.892410 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.889968 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 59540982 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 9880482 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 3329329 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 435241532 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.883928 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.881300 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 295032576 67.93% 67.93% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 66481508 15.31% 83.23% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 24486149 5.64% 88.87% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 11154018 2.57% 91.44% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 8043816 1.85% 93.29% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 4878030 1.12% 94.41% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 4540806 1.05% 95.46% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 2951206 0.68% 96.14% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 16778864 3.86% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 296713491 68.17% 68.17% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 66287598 15.23% 83.40% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 24183303 5.56% 88.96% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 11166549 2.57% 91.52% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 8012002 1.84% 93.36% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 4870056 1.12% 94.48% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 4489994 1.03% 95.52% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 2918433 0.67% 96.19% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 16600106 3.81% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 434346973 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 330373719 # Number of instructions committed -system.cpu2.commit.committedOps 387615464 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 435241532 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 327785464 # Number of instructions committed +system.cpu2.commit.committedOps 384721982 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 119073741 # Number of memory references committed -system.cpu2.commit.loads 62579496 # Number of loads committed -system.cpu2.commit.membars 2588612 # Number of memory barriers committed -system.cpu2.commit.branches 73762518 # Number of branches committed -system.cpu2.commit.fp_insts 337914 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 356071087 # Number of committed integer instructions. -system.cpu2.commit.function_calls 9588871 # Number of function calls committed. +system.cpu2.commit.refs 117903346 # Number of memory references committed +system.cpu2.commit.loads 61819623 # Number of loads committed +system.cpu2.commit.membars 2573370 # Number of memory barriers committed +system.cpu2.commit.branches 73211237 # Number of branches committed +system.cpu2.commit.fp_insts 346819 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 353394375 # Number of committed integer instructions. +system.cpu2.commit.function_calls 9534563 # Number of function calls committed. system.cpu2.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 267662094 69.05% 69.05% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 802922 0.21% 69.26% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 37337 0.01% 69.27% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 69.27% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 69.27% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 69.27% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 69.27% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 69.27% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 69.27% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 69.27% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 69.27% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 69.27% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 69.27% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 69.27% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 69.27% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 69.27% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 69.27% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 69.27% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 69.27% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 69.27% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 69.27% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 69.27% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 69.27% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 69.27% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 69.27% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 39370 0.01% 69.28% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 69.28% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.28% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.28% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 62579496 16.14% 85.43% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 56494245 14.57% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 265954850 69.13% 69.13% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 786882 0.20% 69.33% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 35653 0.01% 69.34% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 69.34% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 69.34% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 69.34% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 69.34% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 69.34% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 69.34% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 69.34% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 69.34% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 69.34% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 69.34% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 69.34% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 69.34% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 69.34% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 69.34% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 69.34% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 69.34% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 69.34% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 69.34% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 69.34% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 69.34% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 69.34% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 69.34% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 41251 0.01% 69.35% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 69.35% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.35% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.35% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 61819623 16.07% 85.42% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 56083723 14.58% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 387615464 # Class of committed instruction -system.cpu2.commit.bw_lim_events 16778864 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 862595097 # The number of ROB reads -system.cpu2.rob.rob_writes 905518660 # The number of ROB writes -system.cpu2.timesIdled 2960768 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 15631742 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 99536690500 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 330373719 # Number of Instructions Simulated -system.cpu2.committedOps 387615464 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.392776 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.392776 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.717991 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.717991 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 507371314 # number of integer regfile reads -system.cpu2.int_regfile_writes 300778245 # number of integer regfile writes -system.cpu2.fp_regfile_reads 673893 # number of floating regfile reads -system.cpu2.fp_regfile_writes 409456 # number of floating regfile writes -system.cpu2.cc_regfile_reads 92253105 # number of cc regfile reads -system.cpu2.cc_regfile_writes 93114012 # number of cc regfile writes -system.cpu2.misc_regfile_reads 838596406 # number of misc regfile reads -system.cpu2.misc_regfile_writes 9943766 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 40265 # Transaction distribution -system.iobus.trans_dist::ReadResp 40265 # Transaction distribution +system.cpu2.commit.op_class_0::total 384721982 # Class of committed instruction +system.cpu2.commit.bw_lim_events 16600106 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 860271406 # The number of ROB reads +system.cpu2.rob.rob_writes 898612976 # The number of ROB writes +system.cpu2.timesIdled 2954119 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 15785647 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 99456385277 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 327785464 # Number of Instructions Simulated +system.cpu2.committedOps 384721982 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.406714 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.406714 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.710877 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.710877 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 503674657 # number of integer regfile reads +system.cpu2.int_regfile_writes 298593848 # number of integer regfile writes +system.cpu2.fp_regfile_reads 690106 # number of floating regfile reads +system.cpu2.fp_regfile_writes 421944 # number of floating regfile writes +system.cpu2.cc_regfile_reads 91580916 # number of cc regfile reads +system.cpu2.cc_regfile_writes 92419773 # number of cc regfile writes +system.cpu2.misc_regfile_reads 837090025 # number of misc regfile reads +system.cpu2.misc_regfile_writes 9982057 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 40263 # Transaction distribution +system.iobus.trans_dist::ReadResp 40263 # Transaction distribution system.iobus.trans_dist::WriteReq 136537 # Transaction distribution -system.iobus.trans_dist::WriteResp 29873 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution +system.iobus.trans_dist::WriteResp 136537 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47686 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -1865,11 +1862,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122568 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230956 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230956 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230952 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230952 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353604 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353600 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47706 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1886,93 +1883,93 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155698 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334240 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334240 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492040 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 13825000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492024 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 13118000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 8203000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 7299000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 34000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 33000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 16991000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 196611881 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 175678218 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 39351000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 37744000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36922037 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 35540000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 80000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115459 # number of replacements -system.iocache.tags.tagsinuse 10.421568 # Cycle average of tags in use +system.iocache.tags.replacements 115457 # number of replacements +system.iocache.tags.tagsinuse 10.416552 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115475 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115473 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13085930884009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.547277 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.874291 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.221705 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.429643 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651348 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13085993128009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 5.913060 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 4.503492 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.369566 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.281468 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651035 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039659 # Number of tag accesses -system.iocache.tags.data_accesses 1039659 # Number of data accesses +system.iocache.tags.tag_accesses 1039641 # Number of tag accesses +system.iocache.tags.data_accesses 1039641 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8814 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8851 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8812 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8849 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8814 # number of demand (read+write) misses -system.iocache.demand_misses::total 8854 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8812 # number of demand (read+write) misses +system.iocache.demand_misses::total 8852 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8814 # number of overall misses -system.iocache.overall_misses::total 8854 # number of overall misses +system.iocache.overall_misses::realview.ide 8812 # number of overall misses +system.iocache.overall_misses::total 8852 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 2432000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 61206163 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 63638163 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6636577681 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 6636577681 # number of WriteInvalidateReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 80359879 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 82791879 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 3987954339 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 3987954339 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 2432000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 61206163 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 63638163 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 80359879 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 82791879 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 2432000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 61206163 # number of overall miss cycles -system.iocache.overall_miss_latency::total 63638163 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 80359879 # number of overall miss cycles +system.iocache.overall_miss_latency::total 82791879 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8814 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8851 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8812 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8849 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8814 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8854 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8812 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8852 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8814 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8854 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8812 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8852 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses @@ -1980,409 +1977,424 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 65729.729730 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 6944.198207 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 7189.940459 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 62219.471246 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 62219.471246 # average WriteInvalidateReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 9119.368929 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 9356.071760 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 37388.006628 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 37388.006628 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 60800 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 6944.198207 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 7187.504292 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 9119.368929 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 9352.900926 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 60800 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 6944.198207 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 7187.504292 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 24555 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 9119.368929 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 9352.900926 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 1026 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3712 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 106 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.615032 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.679245 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 16 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 424 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 440 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 35584 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 35584 # number of WriteInvalidateReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 518 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 534 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 33736 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 33736 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 16 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 424 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 440 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 518 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 534 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 16 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 424 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 440 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 1600000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 38938201 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 40538201 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4786173717 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4786173717 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 1600000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 38938201 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 40538201 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 1600000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 38938201 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 40538201 # number of overall MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 518 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 534 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 1632000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 54459879 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 56091879 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2301154339 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2301154339 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 1632000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 54459879 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 56091879 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 1632000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 54459879 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 56091879 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 0.432432 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.048105 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.049712 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 0.333608 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.333608 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.058783 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.060346 # mshr miss rate for ReadReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.316283 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.316283 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::realview.ethernet 0.400000 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::realview.ide 0.048105 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.049695 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::realview.ide 0.058783 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.060325 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ethernet 0.400000 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::realview.ide 0.048105 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.049695 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 100000 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 91835.379717 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 92132.275000 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134503.532964 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134503.532964 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 100000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 91835.379717 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 92132.275000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 100000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 91835.379717 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 92132.275000 # average overall mshr miss latency +system.iocache.overall_mshr_miss_rate::realview.ide 0.058783 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.060325 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 102000 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 105134.901544 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 105040.971910 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68210.645571 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68210.645571 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 102000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 105134.901544 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 105040.971910 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 102000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 105134.901544 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 105040.971910 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1296366 # number of replacements -system.l2c.tags.tagsinuse 65320.100787 # Cycle average of tags in use -system.l2c.tags.total_refs 28848747 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1358615 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 21.233938 # Average number of references to valid blocks. +system.l2c.tags.replacements 1303829 # number of replacements +system.l2c.tags.tagsinuse 65263.667418 # Cycle average of tags in use +system.l2c.tags.total_refs 45613639 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1366689 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 33.375288 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 37068.766455 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 192.906222 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 268.941849 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3824.960525 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 8195.071890 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 57.414493 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 82.820036 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 874.447112 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2433.555862 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 94.156487 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.itb.walker 158.776869 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2237.420000 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 9830.862987 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.565624 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002944 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.004104 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.058364 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.125047 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000876 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.001264 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.013343 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.037133 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.001437 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.itb.walker 0.002423 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.034140 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.150007 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.996706 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 358 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 61891 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 358 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 140 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 590 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2804 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4928 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53429 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.005463 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.944382 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 273721010 # Number of tag accesses -system.l2c.tags.data_accesses 273721010 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 197948 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 127305 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 6549451 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 3139875 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 71739 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 49467 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 2103694 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 962152 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 389616 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 148852 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 5808812 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 2494651 # number of ReadReq hits -system.l2c.ReadReq_hits::total 22043562 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 7872498 # number of Writeback hits -system.l2c.Writeback_hits::total 7872498 # number of Writeback hits -system.l2c.WriteInvalidateReq_hits::cpu0.data 348712 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::cpu1.data 112622 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::cpu2.data 261017 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::total 722351 # number of WriteInvalidateReq hits -system.l2c.UpgradeReq_hits::cpu0.data 4748 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1579 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 3377 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 9704 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu2.data 2 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 802024 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 244881 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 560523 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 1607428 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 197948 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 127305 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 6549451 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 3941899 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 71739 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 49467 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 2103694 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 1207033 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 389616 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 148852 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 5808812 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 3055174 # number of demand (read+write) hits -system.l2c.demand_hits::total 23650990 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 197948 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 127305 # number of overall hits -system.l2c.overall_hits::cpu0.inst 6549451 # number of overall hits -system.l2c.overall_hits::cpu0.data 3941899 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 71739 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 49467 # number of overall hits -system.l2c.overall_hits::cpu1.inst 2103694 # number of overall hits -system.l2c.overall_hits::cpu1.data 1207033 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 389616 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 148852 # number of overall hits -system.l2c.overall_hits::cpu2.inst 5808812 # number of overall hits -system.l2c.overall_hits::cpu2.data 3055174 # number of overall hits -system.l2c.overall_hits::total 23650990 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 1815 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1875 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 43522 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 134746 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 628 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 584 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 11774 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 35186 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 1454 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.itb.walker 1485 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 34248 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 112174 # number of ReadReq misses -system.l2c.ReadReq_misses::total 379491 # number of ReadReq misses -system.l2c.WriteInvalidateReq_misses::cpu0.data 402597 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::cpu1.data 31349 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::cpu2.data 75410 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::total 509356 # number of WriteInvalidateReq misses -system.l2c.UpgradeReq_misses::cpu0.data 17318 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 5542 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 12758 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 35618 # number of UpgradeReq misses +system.l2c.tags.occ_blocks::writebacks 37041.292991 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 185.441819 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 257.864893 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3799.344283 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 8420.169172 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 49.795293 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 72.886191 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 899.312109 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2654.836821 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 113.517705 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.itb.walker 173.967622 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2205.940609 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 9389.297910 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.565205 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002830 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.003935 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.057973 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.128482 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000760 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.001112 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.013722 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.040510 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.001732 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.itb.walker 0.002655 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.033660 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.143269 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.995845 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 366 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 62494 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 365 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 142 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 561 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2733 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4954 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 54104 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.005585 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.953583 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 407870689 # Number of tag accesses +system.l2c.tags.data_accesses 407870689 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 197247 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 127080 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 74241 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 49038 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 389886 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 153027 # number of ReadReq hits +system.l2c.ReadReq_hits::total 990519 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 7849789 # number of Writeback hits +system.l2c.Writeback_hits::total 7849789 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 4877 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 1479 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2.data 3456 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 9812 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu2.data 6 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 6 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 800462 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 239420 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 561376 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 1601258 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 6543980 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 2084305 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu2.inst 5786165 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 14414450 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 3131607 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 987096 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu2.data 2453224 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 6571927 # number of ReadSharedReq hits +system.l2c.InvalidateReq_hits::cpu0.data 344275 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::cpu1.data 113975 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::cpu2.data 264333 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::total 722583 # number of InvalidateReq hits +system.l2c.demand_hits::cpu0.dtb.walker 197247 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 127080 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 6543980 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 3932069 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 74241 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 49038 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 2084305 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 1226516 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.dtb.walker 389886 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.itb.walker 153027 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 5786165 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 3014600 # number of demand (read+write) hits +system.l2c.demand_hits::total 23578154 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 197247 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 127080 # number of overall hits +system.l2c.overall_hits::cpu0.inst 6543980 # number of overall hits +system.l2c.overall_hits::cpu0.data 3932069 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 74241 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 49038 # number of overall hits +system.l2c.overall_hits::cpu1.inst 2084305 # number of overall hits +system.l2c.overall_hits::cpu1.data 1226516 # number of overall hits +system.l2c.overall_hits::cpu2.dtb.walker 389886 # number of overall hits +system.l2c.overall_hits::cpu2.itb.walker 153027 # number of overall hits +system.l2c.overall_hits::cpu2.inst 5786165 # number of overall hits +system.l2c.overall_hits::cpu2.data 3014600 # number of overall hits +system.l2c.overall_hits::total 23578154 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 1978 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 1959 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 606 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 558 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.dtb.walker 1500 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.itb.walker 1371 # number of ReadReq misses +system.l2c.ReadReq_misses::total 7972 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 17687 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 5395 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 12690 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 35772 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 2 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 260143 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 76149 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 167266 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 503558 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 1815 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1875 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 43522 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 394889 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 628 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 584 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 11774 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 111335 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.dtb.walker 1454 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.itb.walker 1485 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 34248 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 279440 # number of demand (read+write) misses -system.l2c.demand_misses::total 883049 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 1815 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1875 # number of overall misses -system.l2c.overall_misses::cpu0.inst 43522 # number of overall misses -system.l2c.overall_misses::cpu0.data 394889 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 628 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 584 # number of overall misses -system.l2c.overall_misses::cpu1.inst 11774 # number of overall misses -system.l2c.overall_misses::cpu1.data 111335 # number of overall misses -system.l2c.overall_misses::cpu2.dtb.walker 1454 # number of overall misses -system.l2c.overall_misses::cpu2.itb.walker 1485 # number of overall misses -system.l2c.overall_misses::cpu2.inst 34248 # number of overall misses -system.l2c.overall_misses::cpu2.data 279440 # number of overall misses -system.l2c.overall_misses::total 883049 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 53034750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 51385500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 957183750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 2927898000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 131170504 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.itb.walker 133193759 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 2952102750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 10395270751 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 17601239764 # number of ReadReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 30999 # number of WriteInvalidateReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::cpu2.data 902971 # number of WriteInvalidateReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::total 933970 # number of WriteInvalidateReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 83997793 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2.data 205155438 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 289153231 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_misses::cpu2.data 1 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 261433 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 76825 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 166750 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 505008 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 43174 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 11588 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu2.inst 35478 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 90240 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 138626 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 35363 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu2.data 110344 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 284333 # number of ReadSharedReq misses +system.l2c.InvalidateReq_misses::cpu0.data 408877 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::cpu1.data 28566 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::cpu2.data 71958 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::total 509401 # number of InvalidateReq misses +system.l2c.demand_misses::cpu0.dtb.walker 1978 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 1959 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 43174 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 400059 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 606 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 558 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 11588 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 112188 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.dtb.walker 1500 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.itb.walker 1371 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 35478 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 277094 # number of demand (read+write) misses +system.l2c.demand_misses::total 887553 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 1978 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 1959 # number of overall misses +system.l2c.overall_misses::cpu0.inst 43174 # number of overall misses +system.l2c.overall_misses::cpu0.data 400059 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 606 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 558 # number of overall misses +system.l2c.overall_misses::cpu1.inst 11588 # number of overall misses +system.l2c.overall_misses::cpu1.data 112188 # number of overall misses +system.l2c.overall_misses::cpu2.dtb.walker 1500 # number of overall misses +system.l2c.overall_misses::cpu2.itb.walker 1371 # number of overall misses +system.l2c.overall_misses::cpu2.inst 35478 # number of overall misses +system.l2c.overall_misses::cpu2.data 277094 # number of overall misses +system.l2c.overall_misses::total 887553 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 52967500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.itb.walker 49106500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 131463500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.itb.walker 122401500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 355939000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 83182000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2.data 202962500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 286144500 # number of UpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::cpu1.data 159000 # number of SCUpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 6131099175 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 16871513594 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 23002612769 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 53034750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 51385500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 957183750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 9058997175 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.dtb.walker 131170504 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.itb.walker 133193759 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 2952102750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 27266784345 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 40603852533 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 53034750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 51385500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 957183750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 9058997175 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.dtb.walker 131170504 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.itb.walker 133193759 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 2952102750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 27266784345 # number of overall miss cycles -system.l2c.overall_miss_latency::total 40603852533 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 199763 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 129180 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 6592973 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 3274621 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 72367 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 50051 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 2115468 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 997338 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.dtb.walker 391070 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.itb.walker 150337 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 5843060 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 2606825 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 22423053 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 7872498 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 7872498 # number of Writeback accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu0.data 751309 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu1.data 143971 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu2.data 336427 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::total 1231707 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 22066 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 7121 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 16135 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 45322 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_miss_latency::cpu1.data 6175953000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 16594839500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 22770792500 # number of ReadExReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu1.inst 940204000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu2.inst 3036482500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 3976686500 # number of ReadCleanReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 2924693000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu2.data 10192533500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 13117226500 # number of ReadSharedReq miss cycles +system.l2c.InvalidateReq_miss_latency::cpu1.data 2276790000 # number of InvalidateReq miss cycles +system.l2c.InvalidateReq_miss_latency::cpu2.data 7675556000 # number of InvalidateReq miss cycles +system.l2c.InvalidateReq_miss_latency::total 9952346000 # number of InvalidateReq miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 52967500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 49106500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 940204000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 9100646000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.dtb.walker 131463500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.itb.walker 122401500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 3036482500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 26787373000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 40220644500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 52967500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 49106500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 940204000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 9100646000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.dtb.walker 131463500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.itb.walker 122401500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 3036482500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 26787373000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 40220644500 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 199225 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 129039 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 74847 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 49596 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.dtb.walker 391386 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.itb.walker 154398 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 998491 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 7849789 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 7849789 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 22564 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 6874 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 16146 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 45584 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu2.data 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 4 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 1062167 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 321030 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 727789 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 2110986 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 199763 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 129180 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 6592973 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 4336788 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 72367 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 50051 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 2115468 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 1318368 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.dtb.walker 391070 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.itb.walker 150337 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 5843060 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 3334614 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 24534039 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 199763 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 129180 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 6592973 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 4336788 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 72367 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 50051 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 2115468 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 1318368 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.dtb.walker 391070 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.itb.walker 150337 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 5843060 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 3334614 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 24534039 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.009086 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.014515 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.006601 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.041149 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.008678 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.011668 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.005566 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.035280 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.003718 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.itb.walker 0.009878 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.005861 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.043031 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.016924 # miss rate for ReadReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.535861 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.217745 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu2.data 0.224150 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::total 0.413537 # miss rate for WriteInvalidateReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.784827 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.778261 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 0.790703 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.785888 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_accesses::cpu2.data 7 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 9 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 1061895 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 316245 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 728126 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 2106266 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 6587154 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 2095893 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu2.inst 5821643 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 14504690 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 3270233 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 1022459 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu2.data 2563568 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 6856260 # number of ReadSharedReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::cpu0.data 753152 # number of InvalidateReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::cpu1.data 142541 # number of InvalidateReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::cpu2.data 336291 # number of InvalidateReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::total 1231984 # number of InvalidateReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 199225 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 129039 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 6587154 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 4332128 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 74847 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 49596 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 2095893 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 1338704 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.dtb.walker 391386 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.itb.walker 154398 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 5821643 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 3291694 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 24465707 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 199225 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 129039 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 6587154 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 4332128 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 74847 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 49596 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 2095893 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 1338704 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.dtb.walker 391386 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.itb.walker 154398 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 5821643 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 3291694 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 24465707 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.009928 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.015181 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.008097 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.011251 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.003833 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.itb.walker 0.008880 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.007984 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.783859 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.784841 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 0.785953 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.784749 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.244917 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.237202 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 0.229828 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.238542 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.009086 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.014515 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.006601 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.091056 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.008678 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.011668 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.005566 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.084449 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.dtb.walker 0.003718 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.itb.walker 0.009878 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.005861 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.083800 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.035993 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.009086 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.014515 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.006601 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.091056 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.008678 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.011668 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.005566 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.084449 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.dtb.walker 0.003718 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.itb.walker 0.009878 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.005861 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.083800 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.035993 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 84450.238854 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 87988.869863 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 81296.394598 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 83212.016143 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 90213.551582 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 89692.767003 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 86197.814471 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 92670.946485 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 46381.178378 # average ReadReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data 0.988835 # average WriteInvalidateReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::cpu2.data 11.974155 # average WriteInvalidateReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::total 1.833629 # average WriteInvalidateReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 15156.584807 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 16080.532842 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 8118.177073 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_miss_rate::cpu2.data 0.142857 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.333333 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.246195 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.242929 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 0.229013 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.239765 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.006554 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.005529 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.006094 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.006221 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.042390 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.034586 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.043043 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.041471 # miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_miss_rate::cpu0.data 0.542888 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::cpu1.data 0.200405 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::cpu2.data 0.213975 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::total 0.413480 # miss rate for InvalidateReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.009928 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.015181 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.006554 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.092347 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.008097 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.011251 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.005529 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.083803 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.dtb.walker 0.003833 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.itb.walker 0.008880 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.006094 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.084180 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.036277 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.009928 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.015181 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.006554 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.092347 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.008097 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.011251 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.005529 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.083803 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.dtb.walker 0.003833 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.itb.walker 0.008880 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.006094 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.084180 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.036277 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 87405.115512 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 88004.480287 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 87642.333333 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 89278.993435 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 44648.645258 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 15418.350324 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 15993.892829 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 7999.119423 # average UpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 79500 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 80514.506756 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 100866.366111 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 45680.165480 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 84450.238854 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 87988.869863 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 81296.394598 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 81367.020030 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 90213.551582 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.itb.walker 89692.767003 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 86197.814471 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 97576.525712 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 45981.426323 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 84450.238854 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 87988.869863 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 81296.394598 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 81367.020030 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 90213.551582 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.itb.walker 89692.767003 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 86197.814471 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 97576.525712 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 45981.426323 # average overall miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 53000 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 80389.886105 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 99519.277361 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 45089.963921 # average ReadExReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 81136.002761 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 85587.758611 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 44067.891179 # average ReadCleanReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 82704.889291 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 92370.527623 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 46133.324306 # average ReadSharedReq miss latency +system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 79702.793531 # average InvalidateReq miss latency +system.l2c.InvalidateReq_avg_miss_latency::cpu2.data 106667.166959 # average InvalidateReq miss latency +system.l2c.InvalidateReq_avg_miss_latency::total 19537.350732 # average InvalidateReq miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 87405.115512 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 88004.480287 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 81136.002761 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 81119.602810 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 87642.333333 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.itb.walker 89278.993435 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 85587.758611 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 96672.511855 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 45316.329842 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 87405.115512 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 88004.480287 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 81136.002761 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 81119.602810 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 87642.333333 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.itb.walker 89278.993435 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 85587.758611 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 96672.511855 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 45316.329842 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2391,251 +2403,270 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 1099475 # number of writebacks -system.l2c.writebacks::total 1099475 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu2.dtb.walker 8 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2.itb.walker 15 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2.data 2 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 25 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu2.dtb.walker 8 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2.itb.walker 15 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2.data 2 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 25 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu2.dtb.walker 8 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2.itb.walker 15 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2.data 2 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 25 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 628 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 584 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 11774 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 35186 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 1446 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.itb.walker 1470 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 34248 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 112172 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 197508 # number of ReadReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data 31349 # number of WriteInvalidateReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::cpu2.data 75410 # number of WriteInvalidateReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::total 106759 # number of WriteInvalidateReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 5542 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 12758 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 18300 # number of UpgradeReq MSHR misses +system.l2c.writebacks::writebacks 1103217 # number of writebacks +system.l2c.writebacks::total 1103217 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu2.dtb.walker 11 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2.itb.walker 22 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 33 # number of ReadReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu2.data 5 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 5 # number of ReadSharedReq MSHR hits +system.l2c.demand_mshr_hits::cpu2.dtb.walker 11 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2.itb.walker 22 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2.data 5 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 38 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu2.dtb.walker 11 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2.itb.walker 22 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2.data 5 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 38 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 606 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 558 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 1489 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.itb.walker 1349 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 4002 # number of ReadReq MSHR misses +system.l2c.CleanEvict_mshr_misses::writebacks 328 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 328 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 5395 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 12690 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 18085 # number of UpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 2 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 76149 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 167266 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 243415 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 628 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 584 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 11774 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 111335 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.dtb.walker 1446 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.itb.walker 1470 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 34248 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 279438 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 440923 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 628 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 584 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 11774 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 111335 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.dtb.walker 1446 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.itb.walker 1470 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 34248 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 279438 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 440923 # number of overall MSHR misses -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 5448 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu2.data 8279 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 13727 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 5373 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu2.data 7916 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 13289 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 10821 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu2.data 16195 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 27016 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 45139750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 44046000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 809585750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 2487118500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 112189752 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 113691259 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 2523258750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 8999138499 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 15134168260 # number of ReadReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 987692501 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu2.data 2488109529 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::total 3475802030 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 97166042 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 226510254 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 323676296 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 135000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 135000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 5178636325 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 14796575906 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 19975212231 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 45139750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 44046000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 809585750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 7665754825 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 112189752 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 113691259 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 2523258750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 23795714405 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 35109380491 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 45139750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 44046000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 809585750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 7665754825 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 112189752 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 113691259 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 2523258750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 23795714405 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 35109380491 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 818834500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 1358915500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 2177750000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 825245000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 1335319496 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 2160564496 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1644079500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 2694234996 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 4338314496 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.008678 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.011668 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.005566 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.035280 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.003698 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.009778 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.005861 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.043030 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.008808 # mshr miss rate for ReadReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.217745 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu2.data 0.224150 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.086676 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.778261 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.790703 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.403777 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_misses::cpu2.data 1 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 76825 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 166750 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 243575 # number of ReadExReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 11588 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 35478 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::total 47066 # number of ReadCleanReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 35363 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu2.data 110339 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 145702 # number of ReadSharedReq MSHR misses +system.l2c.InvalidateReq_mshr_misses::cpu1.data 28566 # number of InvalidateReq MSHR misses +system.l2c.InvalidateReq_mshr_misses::cpu2.data 71958 # number of InvalidateReq MSHR misses +system.l2c.InvalidateReq_mshr_misses::total 100524 # number of InvalidateReq MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 606 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 558 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 11588 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 112188 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.dtb.walker 1489 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.itb.walker 1349 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 35478 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 277089 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 440345 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 606 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 558 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 11588 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 112188 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.dtb.walker 1489 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.itb.walker 1349 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 35478 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 277089 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 440345 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 4998 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu2.data 8152 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 13150 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 4942 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu2.data 7788 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 12730 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 9940 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu2.data 15940 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 25880 # number of overall MSHR uncacheable misses +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 46907500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 43526500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 115771000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 107384500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 313589500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 111371500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 263334500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 374706000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 139000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data 20500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 159500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 5407703000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 14927339500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 20335042500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 824324000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 2681702500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 3506026500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 2571063000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 9088897000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 11659960000 # number of ReadSharedReq MSHR miss cycles +system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 1991130000 # number of InvalidateReq MSHR miss cycles +system.l2c.InvalidateReq_mshr_miss_latency::cpu2.data 6955976000 # number of InvalidateReq MSHR miss cycles +system.l2c.InvalidateReq_mshr_miss_latency::total 8947106000 # number of InvalidateReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 46907500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 43526500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 824324000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 7978766000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 115771000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 107384500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 2681702500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 24016236500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 35814618500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 46907500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 43526500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 824324000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 7978766000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 115771000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 107384500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 2681702500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 24016236500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 35814618500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 763712000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 1373074000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 2136786000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 770891000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 1347269000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2118160000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1534603000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 2720343000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4254946000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.008097 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.011251 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.003804 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.008737 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.004008 # mshr miss rate for ReadReq accesses +system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.784841 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.785953 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.396740 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.237202 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.229828 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.115309 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.008678 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.011668 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005566 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.084449 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.003698 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.009778 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.005861 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.083799 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.017972 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.008678 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.011668 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005566 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.084449 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.003698 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.009778 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.005861 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.083799 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.017972 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 71878.582803 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 75421.232877 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 68760.467980 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 70684.888876 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 77586.273859 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 77340.992517 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 73676.090575 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 80226.246291 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 76625.596229 # average ReadReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 31506.347922 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu2.data 32994.424201 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 32557.461479 # average WriteInvalidateReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17532.667268 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 17754.370121 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17687.229290 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 67500 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 67500 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 68006.622871 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 88461.348427 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 82062.371797 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 71878.582803 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 75421.232877 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 68760.467980 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 68853.054520 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 77586.273859 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 77340.992517 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73676.090575 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 85155.613786 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 79627.010818 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 71878.582803 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 75421.232877 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 68760.467980 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 68853.054520 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 77586.273859 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 77340.992517 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73676.090575 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 85155.613786 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 79627.010818 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 150300.018355 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 164140.053147 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 158647.191666 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 153591.103666 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 168686.141486 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 162582.925427 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 151934.155808 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 166362.148564 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 160583.154279 # average overall mshr uncacheable latency +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.142857 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.242929 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.229013 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.115643 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.005529 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.006094 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.003245 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.034586 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.043041 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.021251 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.200405 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu2.data 0.213975 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.081595 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.008097 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.011251 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005529 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.083803 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.003804 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.008737 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.006094 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.084178 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.017998 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.008097 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.011251 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005529 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.083803 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.003804 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.008737 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.006094 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.084178 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.017998 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 77405.115512 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 78004.480287 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 77750.839490 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 79603.039288 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 78358.195902 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20643.466172 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20751.339638 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20719.159524 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 69500 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 20500 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 53166.666667 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 70389.886105 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 89519.277361 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 83485.753875 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 71136.002761 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 75587.758611 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 74491.703140 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 72704.889291 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 82372.479359 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 80026.080630 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69702.793531 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu2.data 96667.166959 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 89004.675500 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 77405.115512 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 78004.480287 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71136.002761 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71119.602810 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 77750.839490 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 79603.039288 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 75587.758611 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 86673.366680 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 81333.087693 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77405.115512 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 78004.480287 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71136.002761 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71119.602810 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 77750.839490 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 79603.039288 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 75587.758611 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 86673.366680 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 81333.087693 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 152803.521409 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 168434.003925 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 162493.231939 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 155987.656819 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 172992.937853 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 166391.201885 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 154386.619718 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 170661.417817 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 164410.587326 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 465050 # Transaction distribution -system.membus.trans_dist::ReadResp 465050 # Transaction distribution +system.membus.trans_dist::ReadReq 76733 # Transaction distribution +system.membus.trans_dist::ReadResp 468089 # Transaction distribution system.membus.trans_dist::WriteReq 33644 # Transaction distribution system.membus.trans_dist::WriteResp 33644 # Transaction distribution -system.membus.trans_dist::Writeback 1206105 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 615969 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 615969 # Transaction distribution -system.membus.trans_dist::UpgradeReq 36256 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 36258 # Transaction distribution -system.membus.trans_dist::ReadExReq 502974 # Transaction distribution -system.membus.trans_dist::ReadExResp 502974 # Transaction distribution +system.membus.trans_dist::Writeback 1209847 # Transaction distribution +system.membus.trans_dist::CleanEvict 210029 # Transaction distribution +system.membus.trans_dist::UpgradeReq 36410 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.membus.trans_dist::UpgradeResp 36413 # Transaction distribution +system.membus.trans_dist::ReadExReq 1013774 # Transaction distribution +system.membus.trans_dist::ReadExResp 1013774 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 391356 # Transaction distribution +system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution +system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122568 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 60 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 61 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6750 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4046690 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4176068 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337286 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 337286 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4513354 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4261294 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4390673 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 345792 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 345792 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4736465 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155698 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 196 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13500 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 159620960 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 159790354 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14192960 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14192960 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 173983314 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 541 # Total snoops (count) -system.membus.snoop_fanout::samples 2860073 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 160146208 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 160315602 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7368448 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7368448 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 167684050 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 579 # Total snoops (count) +system.membus.snoop_fanout::samples 3078821 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2860073 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3078821 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2860073 # Request fanout histogram -system.membus.reqLayer0.occupancy 47655000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3078821 # Request fanout histogram +system.membus.reqLayer0.occupancy 45758500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 2500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1342002 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1294500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 3662717737 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 3125844189 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2514330197 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2930708426 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 37911963 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 61033927 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -2679,51 +2710,54 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 18 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 22942749 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 22942559 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 1510117 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 22871416 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 33644 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 33644 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 7872498 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 1267320 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 1231707 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 45322 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 45326 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2110986 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2110986 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 29189373 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 28540858 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 848998 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1760970 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 60340199 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 931468564 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1158220350 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3098688 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6299696 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 2099087298 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 376855 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 34352020 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.045142 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.207615 # Request fanout histogram +system.toL2Bus.trans_dist::Writeback 8317119 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 16946911 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 45584 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 9 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 45593 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2106266 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2106266 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 14504828 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 6856794 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 1265720 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 1231984 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 43598497 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 30808593 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 852484 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1760318 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 77019892 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 928472660 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1076191614 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3123312 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6312032 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 2014099618 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 938060 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 51670008 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.040962 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.198203 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 32801302 95.49% 95.49% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 1550718 4.51% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 49553478 95.90% 95.90% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 2116530 4.10% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 34352020 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 13384646524 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 51670008 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 17416968994 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 375000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 316500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 11949873226 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 11880834300 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 7318478020 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 7217033015 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 275201891 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 275805669 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 650856160 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 649517949 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt index f9affe46b..fa15729bd 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt @@ -1,157 +1,157 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.318118 # Number of seconds simulated -sim_ticks 51318118168000 # Number of ticks simulated -final_tick 51318118168000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.321386 # Number of seconds simulated +sim_ticks 51321386217000 # Number of ticks simulated +final_tick 51321386217000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 134879 # Simulator instruction rate (inst/s) -host_op_rate 158483 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7620199718 # Simulator tick rate (ticks/s) -host_mem_usage 732720 # Number of bytes of host memory used -host_seconds 6734.48 # Real time elapsed on the host -sim_insts 908340493 # Number of instructions simulated -sim_ops 1067303522 # Number of ops (including micro ops) simulated +host_inst_rate 131020 # Simulator instruction rate (inst/s) +host_op_rate 153952 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7451916901 # Simulator tick rate (ticks/s) +host_mem_usage 738104 # Number of bytes of host memory used +host_seconds 6887.00 # Real time elapsed on the host +sim_insts 902332774 # Number of instructions simulated +sim_ops 1060266688 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 160000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 146112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3855296 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 28386264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 162496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 145216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3634496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 27952240 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 430656 # Number of bytes read from this memory -system.physmem.bytes_read::total 64872776 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3855296 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3634496 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 7489792 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 83283200 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 154240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 142464 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 4107136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 45245848 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 165376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 158016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3334400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 43223216 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 435264 # Number of bytes read from this memory +system.physmem.bytes_read::total 96965960 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 4107136 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3334400 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7441536 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 82289920 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 83303780 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2500 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2283 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 60239 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 443543 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2539 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2269 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 56789 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 436759 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6729 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1013650 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1301300 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 82310500 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2410 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2226 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 64174 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 706974 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2584 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2469 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 52100 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 675368 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6801 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1515106 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1285780 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1303873 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3118 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2847 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 75125 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 553143 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 3166 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2830 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 70823 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 544686 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8392 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1264130 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 75125 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 70823 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 145948 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1622881 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1288353 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3005 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2776 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 80028 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 881618 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 3222 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 3079 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 64971 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 842207 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8481 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1889387 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 80028 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 64971 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 144999 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1603424 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1623282 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1622881 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3118 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2847 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 75125 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 553544 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 3166 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2830 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 70823 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 544686 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8392 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2887412 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1013650 # Number of read requests accepted -system.physmem.writeReqs 1930075 # Number of write requests accepted -system.physmem.readBursts 1013650 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1930075 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 64838144 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 35456 # Total number of bytes read from write queue -system.physmem.bytesWritten 120356480 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 64872776 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 123380708 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 554 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 49498 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 37388 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 61871 # Per bank write bursts -system.physmem.perBankRdBursts::1 62981 # Per bank write bursts -system.physmem.perBankRdBursts::2 60043 # Per bank write bursts -system.physmem.perBankRdBursts::3 58309 # Per bank write bursts -system.physmem.perBankRdBursts::4 58023 # Per bank write bursts -system.physmem.perBankRdBursts::5 70636 # Per bank write bursts -system.physmem.perBankRdBursts::6 62371 # Per bank write bursts -system.physmem.perBankRdBursts::7 61877 # Per bank write bursts -system.physmem.perBankRdBursts::8 57508 # Per bank write bursts -system.physmem.perBankRdBursts::9 84884 # Per bank write bursts -system.physmem.perBankRdBursts::10 63101 # Per bank write bursts -system.physmem.perBankRdBursts::11 65471 # Per bank write bursts -system.physmem.perBankRdBursts::12 60660 # Per bank write bursts -system.physmem.perBankRdBursts::13 66399 # Per bank write bursts -system.physmem.perBankRdBursts::14 58532 # Per bank write bursts -system.physmem.perBankRdBursts::15 60430 # Per bank write bursts -system.physmem.perBankWrBursts::0 115217 # Per bank write bursts -system.physmem.perBankWrBursts::1 115969 # Per bank write bursts -system.physmem.perBankWrBursts::2 118272 # Per bank write bursts -system.physmem.perBankWrBursts::3 117255 # Per bank write bursts -system.physmem.perBankWrBursts::4 115771 # Per bank write bursts -system.physmem.perBankWrBursts::5 124355 # Per bank write bursts -system.physmem.perBankWrBursts::6 120059 # Per bank write bursts -system.physmem.perBankWrBursts::7 119259 # Per bank write bursts -system.physmem.perBankWrBursts::8 113485 # Per bank write bursts -system.physmem.perBankWrBursts::9 118397 # Per bank write bursts -system.physmem.perBankWrBursts::10 117107 # Per bank write bursts -system.physmem.perBankWrBursts::11 118510 # Per bank write bursts -system.physmem.perBankWrBursts::12 116303 # Per bank write bursts -system.physmem.perBankWrBursts::13 122603 # Per bank write bursts -system.physmem.perBankWrBursts::14 113656 # Per bank write bursts -system.physmem.perBankWrBursts::15 114352 # Per bank write bursts +system.physmem.bw_write::total 1603825 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1603424 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3005 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2776 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 80028 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 882019 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 3222 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 3079 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 64971 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 842207 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8481 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3493212 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1515106 # Number of read requests accepted +system.physmem.writeReqs 1288353 # Number of write requests accepted +system.physmem.readBursts 1515106 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1288353 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 96901440 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 65344 # Total number of bytes read from write queue +system.physmem.bytesWritten 82309952 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 96965960 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 82310500 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1021 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2247 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 144011 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 91435 # Per bank write bursts +system.physmem.perBankRdBursts::1 93225 # Per bank write bursts +system.physmem.perBankRdBursts::2 89718 # Per bank write bursts +system.physmem.perBankRdBursts::3 87919 # Per bank write bursts +system.physmem.perBankRdBursts::4 92611 # Per bank write bursts +system.physmem.perBankRdBursts::5 102433 # Per bank write bursts +system.physmem.perBankRdBursts::6 93232 # Per bank write bursts +system.physmem.perBankRdBursts::7 90056 # Per bank write bursts +system.physmem.perBankRdBursts::8 87362 # Per bank write bursts +system.physmem.perBankRdBursts::9 117909 # Per bank write bursts +system.physmem.perBankRdBursts::10 95229 # Per bank write bursts +system.physmem.perBankRdBursts::11 97284 # Per bank write bursts +system.physmem.perBankRdBursts::12 90073 # Per bank write bursts +system.physmem.perBankRdBursts::13 103730 # Per bank write bursts +system.physmem.perBankRdBursts::14 91691 # Per bank write bursts +system.physmem.perBankRdBursts::15 90178 # Per bank write bursts +system.physmem.perBankWrBursts::0 77827 # Per bank write bursts +system.physmem.perBankWrBursts::1 79309 # Per bank write bursts +system.physmem.perBankWrBursts::2 76608 # Per bank write bursts +system.physmem.perBankWrBursts::3 77829 # Per bank write bursts +system.physmem.perBankWrBursts::4 80050 # Per bank write bursts +system.physmem.perBankWrBursts::5 85847 # Per bank write bursts +system.physmem.perBankWrBursts::6 79718 # Per bank write bursts +system.physmem.perBankWrBursts::7 79449 # Per bank write bursts +system.physmem.perBankWrBursts::8 76360 # Per bank write bursts +system.physmem.perBankWrBursts::9 83802 # Per bank write bursts +system.physmem.perBankWrBursts::10 81643 # Per bank write bursts +system.physmem.perBankWrBursts::11 83145 # Per bank write bursts +system.physmem.perBankWrBursts::12 78123 # Per bank write bursts +system.physmem.perBankWrBursts::13 87627 # Per bank write bursts +system.physmem.perBankWrBursts::14 79500 # Per bank write bursts +system.physmem.perBankWrBursts::15 79256 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 644 # Number of times write queue was full causing retry -system.physmem.totGap 51318117066500 # Total gap between requests +system.physmem.numWrRetry 14 # Number of times write queue was full causing retry +system.physmem.totGap 51321385112000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1013635 # Read request sizes (log2) +system.physmem.readPktSize::6 1515091 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1927502 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 564185 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 294633 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 102008 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 45915 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 724 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 557 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 502 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 740 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 491 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1923 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 318 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 174 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 159 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 126 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 122 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 115 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 113 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 92 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 72 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1285780 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 688629 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 426852 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 228074 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 164413 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 987 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 543 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 541 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 558 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 875 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 956 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 461 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 221 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 194 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 156 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 128 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 125 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 104 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 85 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 62 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -162,175 +162,189 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 743 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 732 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 725 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 731 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 755 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 745 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 744 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 735 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 736 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 718 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 732 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 725 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 29010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 66066 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 62259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 89013 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 88926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 107579 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 106733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 116711 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 108023 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 122723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 101978 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 129145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 103612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 95256 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 108517 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 90319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 86324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 81769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 9575 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 8389 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 8185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 9213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 9986 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 8806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 9359 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 9979 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 8573 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 8083 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 7257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 7806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 7695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 6239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 6318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 5151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 4640 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 3932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 3740 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 3115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 3218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 2806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 3055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 2506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 3036 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 2297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 2830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 2028 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 4689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 976 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 2118 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 627585 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 295.090291 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 168.534210 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 332.652886 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 259317 41.32% 41.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 149298 23.79% 65.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 56496 9.00% 74.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 28437 4.53% 78.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 21665 3.45% 82.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 12676 2.02% 84.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 11310 1.80% 85.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 8646 1.38% 87.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 79740 12.71% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 627585 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 69573 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 14.561338 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 62.076495 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 69566 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 3 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-2047 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::11776-12287 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 69573 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 69573 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.030170 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.998159 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 37.100716 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-31 59064 84.90% 84.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-63 4267 6.13% 91.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-95 4153 5.97% 97.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-127 990 1.42% 98.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-159 298 0.43% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-191 151 0.22% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-223 89 0.13% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-255 92 0.13% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-287 109 0.16% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-319 106 0.15% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-351 80 0.11% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-383 57 0.08% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-415 25 0.04% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::416-447 19 0.03% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::448-479 14 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-511 19 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-543 11 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-575 5 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::576-607 3 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::608-639 3 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::640-671 5 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::672-703 6 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::736-767 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::768-799 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::960-991 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1152-1183 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1600-1631 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 69573 # Writes before turning the bus around for reads -system.physmem.totQLat 27603415095 # Total ticks spent queuing -system.physmem.totMemAccLat 46598965095 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5065480000 # Total ticks spent in databus transfers -system.physmem.avgQLat 27246.59 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::12 728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 722 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 13812 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 16283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 29465 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 43941 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 62844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 76168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 76695 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 80163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 82135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 85619 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 84213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 87116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 83567 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 96056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 103672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 81346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 84582 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 77173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1417 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 915 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 475 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 424 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 410 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 446 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 375 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 37 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 590002 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 303.746442 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.840046 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 333.017877 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 235290 39.88% 39.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 136180 23.08% 62.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 56828 9.63% 72.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 27605 4.68% 77.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 24232 4.11% 81.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 13797 2.34% 83.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 13359 2.26% 85.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 9785 1.66% 87.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 72926 12.36% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 590002 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 74241 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 20.393489 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 234.888851 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 74237 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-12287 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::61440-63487 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 74241 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 74241 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.323218 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.863934 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 6.335765 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 39 0.05% 0.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 11 0.01% 0.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 20 0.03% 0.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 65 0.09% 0.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 70112 94.44% 94.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 1316 1.77% 96.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 568 0.77% 97.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 346 0.47% 97.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 342 0.46% 98.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 528 0.71% 98.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 134 0.18% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 37 0.05% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 41 0.06% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 27 0.04% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 42 0.06% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 26 0.04% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 396 0.53% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 32 0.04% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 46 0.06% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 38 0.05% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 9 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 3 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 5 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 3 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 3 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 4 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 24 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 4 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 74241 # Writes before turning the bus around for reads +system.physmem.totQLat 44116098728 # Total ticks spent queuing +system.physmem.totMemAccLat 72505192478 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 7570425000 # Total ticks spent in databus transfers +system.physmem.avgQLat 29137.13 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 45996.59 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.26 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.35 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.26 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.40 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 47887.13 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.89 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.60 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.89 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.60 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing -system.physmem.avgWrQLen 8.19 # Average write queue length when enqueuing -system.physmem.readRowHits 781690 # Number of row buffer hits during reads -system.physmem.writeRowHits 1484389 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.16 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.93 # Row buffer hit rate for writes -system.physmem.avgGap 17433054.06 # Average gap between requests -system.physmem.pageHitRate 78.31 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2390683680 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1304440500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3869626800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 6131097360 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3351849795840 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1233875646405 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29708521981500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34307943272085 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.534751 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49422598441359 # Time in different power states -system.physmem_0.memoryStateTime::REF 1713624640000 # Time in different power states +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 11.13 # Average write queue length when enqueuing +system.physmem.readRowHits 1245847 # Number of row buffer hits during reads +system.physmem.writeRowHits 964327 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.28 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.98 # Row buffer hit rate for writes +system.physmem.avgGap 18306451.11 # Average gap between requests +system.physmem.pageHitRate 78.93 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2222337600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1212585000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 5776859400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4125407760 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3352063391040 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1232605432755 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29711598339000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34309604352555 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.524518 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49427675587817 # Time in different power states +system.physmem_0.memoryStateTime::REF 1713733840000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 181894714141 # Time in different power states +system.physmem_0.memoryStateTime::ACT 179976420183 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2353858920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1284347625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4032475200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 6054996240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3351849795840 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1235994503985 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29706663342750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34308233320560 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.540403 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49419482573169 # Time in different power states -system.physmem_1.memoryStateTime::REF 1713624640000 # Time in different power states +system.physmem_1.actEnergy 2238077520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1221173250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 6032956800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4208474880 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3352063391040 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1237235987925 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29707536448500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34310536509915 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.542681 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49420862619804 # Time in different power states +system.physmem_1.memoryStateTime::REF 1713733840000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 185010821331 # Time in different power states +system.physmem_1.memoryStateTime::ACT 186788845196 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 768 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -360,15 +374,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 133240776 # Number of BP lookups -system.cpu0.branchPred.condPredicted 90773806 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 5898398 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 90806413 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 65300191 # Number of BTB hits +system.cpu0.branchPred.lookups 132571032 # Number of BP lookups +system.cpu0.branchPred.condPredicted 90050105 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 5878539 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 90490581 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 64975080 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 71.911431 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 17271308 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 187435 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 71.803142 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 17318147 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 190057 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -399,86 +413,94 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 900960 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 900960 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 16847 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 91388 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 546326 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 354634 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 2141.455698 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 12590.575916 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-65535 352292 99.34% 99.34% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-131071 1866 0.53% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::131072-196607 247 0.07% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::196608-262143 95 0.03% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::262144-327679 68 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::327680-393215 37 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::393216-458751 25 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::458752-524287 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 354634 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 411836 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 21432.646658 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 17288.307814 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 16337.255715 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 405278 98.41% 98.41% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 5723 1.39% 99.80% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 333 0.08% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 332 0.08% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 90 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 39 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 17 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 21 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 913008 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 913008 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 16692 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 92976 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 560771 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 352237 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 2376.777567 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 13703.858808 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-32767 344408 97.78% 97.78% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::32768-65535 5384 1.53% 99.31% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-98303 983 0.28% 99.58% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::98304-131071 725 0.21% 99.79% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-163839 276 0.08% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::163840-196607 169 0.05% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::196608-229375 94 0.03% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::229376-262143 47 0.01% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::262144-294911 59 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::294912-327679 14 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::327680-360447 14 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::360448-393215 25 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::393216-425983 25 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::425984-458751 8 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::458752-491519 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::491520-524287 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 352237 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 421207 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 22517.986406 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 18384.767938 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 16267.103719 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 412281 97.88% 97.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 8071 1.92% 99.80% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 392 0.09% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 363 0.09% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 55 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 22 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 7 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 13 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 411836 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 323720569592 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.132299 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.681450 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-3 322818413592 99.72% 99.72% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-7 497609500 0.15% 99.88% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-11 179612000 0.06% 99.93% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-15 106469500 0.03% 99.96% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-19 44651500 0.01% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::20-23 21065000 0.01% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::24-27 19836500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::28-31 27755000 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::32-35 4822000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::36-39 304000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::40-43 19500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::44-47 8500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::48-51 3000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 323720569592 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 91388 84.43% 84.43% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 16847 15.57% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 108235 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 900960 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkCompletionTime::total 421207 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 353008884868 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.117411 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.682149 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-3 352021835868 99.72% 99.72% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-7 541843500 0.15% 99.87% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-11 193463500 0.05% 99.93% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-15 118741500 0.03% 99.96% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-19 46634500 0.01% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::20-23 24285000 0.01% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::24-27 23543000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::28-31 31748500 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::32-35 6046000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::36-39 436000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::40-43 56500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::44-47 38500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::48-51 27500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::52-55 185000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 353008884868 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 92977 84.78% 84.78% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 16692 15.22% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 109669 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 913008 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 900960 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 108235 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 913008 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 109669 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 108235 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 1009195 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 109669 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 1022677 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 105886901 # DTB read hits -system.cpu0.dtb.read_misses 623655 # DTB read misses -system.cpu0.dtb.write_hits 81874264 # DTB write hits -system.cpu0.dtb.write_misses 277305 # DTB write misses -system.cpu0.dtb.flush_tlb 1077 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 104802286 # DTB read hits +system.cpu0.dtb.read_misses 628192 # DTB read misses +system.cpu0.dtb.write_hits 81730320 # DTB write hits +system.cpu0.dtb.write_misses 284816 # DTB write misses +system.cpu0.dtb.flush_tlb 1079 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 22243 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 520 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 54719 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 205 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 9949 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 22185 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 501 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 54383 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 188 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 9307 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 55268 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 106510556 # DTB read accesses -system.cpu0.dtb.write_accesses 82151569 # DTB write accesses +system.cpu0.dtb.perms_faults 56122 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 105430478 # DTB read accesses +system.cpu0.dtb.write_accesses 82015136 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 187761165 # DTB hits -system.cpu0.dtb.misses 900960 # DTB misses -system.cpu0.dtb.accesses 188662125 # DTB accesses +system.cpu0.dtb.hits 186532606 # DTB hits +system.cpu0.dtb.misses 913008 # DTB misses +system.cpu0.dtb.accesses 187445614 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -508,851 +530,847 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 103995 # Table walker walks requested -system.cpu0.itb.walker.walksLong 103995 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 2920 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 70184 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 13953 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 90042 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1564.791986 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 9356.128105 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-32767 89344 99.22% 99.22% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-65535 299 0.33% 99.56% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-98303 238 0.26% 99.82% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::98304-131071 101 0.11% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::131072-163839 19 0.02% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::163840-196607 13 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::196608-229375 12 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::229376-262143 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::262144-294911 7 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::294912-327679 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walks 102934 # Table walker walks requested +system.cpu0.itb.walker.walksLong 102934 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 2830 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 69670 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 14211 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 88723 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1670.198257 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 9993.098637 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-32767 87793 98.95% 98.95% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-65535 509 0.57% 99.53% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-98303 243 0.27% 99.80% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::98304-131071 94 0.11% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::131072-163839 34 0.04% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::163840-196607 21 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::196608-229375 9 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::229376-262143 1 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::262144-294911 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::294912-327679 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::327680-360447 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 90042 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 87057 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 26438.085553 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 21999.622082 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 18398.516639 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-32767 48630 55.86% 55.86% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-65535 36690 42.14% 98.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-98303 630 0.72% 98.73% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::98304-131071 790 0.91% 99.64% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-163839 103 0.12% 99.75% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::163840-196607 96 0.11% 99.86% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-229375 32 0.04% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::229376-262143 31 0.04% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-294911 24 0.03% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::294912-327679 18 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-360447 10 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 87057 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 276399275336 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 1.905006 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 -250074257964 -90.48% -90.48% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 526414060300 190.45% 99.98% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 52102500 0.02% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 6093500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 943000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::5 232500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::6 42500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::7 59000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 276399275336 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 70184 96.01% 96.01% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 2920 3.99% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 73104 # Table walker page sizes translated +system.cpu0.itb.walker.walkWaitTime::total 88723 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 86711 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 27827.271050 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 23655.790569 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 18399.370737 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 84751 97.74% 97.74% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 1686 1.94% 99.68% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 179 0.21% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 53 0.06% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 20 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 14 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 86711 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 499035191932 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 1.085193 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -42443239012 -8.51% -8.51% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 541415505444 108.49% 99.99% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 55393500 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 6761000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 722500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::5 48000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::6 500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 499035191932 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 69670 96.10% 96.10% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 2830 3.90% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 72500 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 103995 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 103995 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 102934 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 102934 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 73104 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 73104 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 177099 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 95374234 # ITB inst hits -system.cpu0.itb.inst_misses 103995 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 72500 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 72500 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 175434 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 95094277 # ITB inst hits +system.cpu0.itb.inst_misses 102934 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 1077 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 1079 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 22243 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 520 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 40386 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 22185 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 501 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 40091 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 207806 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 207907 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 95478229 # ITB inst accesses -system.cpu0.itb.hits 95374234 # DTB hits -system.cpu0.itb.misses 103995 # DTB misses -system.cpu0.itb.accesses 95478229 # DTB accesses -system.cpu0.numCycles 670757384 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 95197211 # ITB inst accesses +system.cpu0.itb.hits 95094277 # DTB hits +system.cpu0.itb.misses 102934 # DTB misses +system.cpu0.itb.accesses 95197211 # DTB accesses +system.cpu0.numCycles 675702202 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 244295585 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 592642803 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 133240776 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 82571499 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 387821427 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 13413764 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 2417197 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 21066 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 3440 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 5441880 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 164758 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 2028 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 95148929 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 3635106 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 41714 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 646873994 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.071808 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.317751 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 244757501 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 589419880 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 132571032 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 82293227 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 391738714 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 13356245 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 2509355 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 22606 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 4900 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 5469917 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 167540 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 2725 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 94868898 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 3621980 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 41300 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 651351111 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.059349 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.306953 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 500514392 77.37% 77.37% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 18314774 2.83% 80.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 18453367 2.85% 83.06% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 13440049 2.08% 85.14% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 29078999 4.50% 89.63% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 9061143 1.40% 91.03% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 9714650 1.50% 92.53% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 8499613 1.31% 93.85% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 39797007 6.15% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 505677761 77.64% 77.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 18279909 2.81% 80.44% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 18243298 2.80% 83.24% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 13516535 2.08% 85.32% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 28852465 4.43% 89.75% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 8999693 1.38% 91.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 9719421 1.49% 92.62% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 8528805 1.31% 93.93% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 39533224 6.07% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 646873994 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.198642 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.883543 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 198183326 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 323426019 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 105981621 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 13950733 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 5329290 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 19638547 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 1397625 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 646526277 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 4318123 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 5329290 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 205971985 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 23697587 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 259101155 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 111995163 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 40775442 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 631047036 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 83751 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2209243 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 1613560 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 20761963 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 3444 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 605295621 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 976490610 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 746368883 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 733214 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 508351996 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 96943625 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 15774650 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 13795198 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 78408950 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 101681556 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 86254396 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 13698017 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 14540360 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 598113520 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 15856672 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 599090036 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 857856 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 81807793 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 52627296 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 360655 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 646873994 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.926131 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.649248 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 651351111 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.196197 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.872307 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 198764731 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 327769223 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 105831567 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 13682981 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5300378 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 19660361 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 1397395 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 643175990 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 4312729 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5300378 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 206434504 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 26397501 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 257870314 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 111703786 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 43642083 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 627780362 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 81911 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 1880696 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 1582827 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 24120192 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 3699 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 601307944 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 969598831 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 742471294 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 750947 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 504947564 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 96360375 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 15500464 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 13524428 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 76866665 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 101145902 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 86060501 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 13628383 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 14576675 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 595266457 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 15567772 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 595602490 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 860155 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 81220997 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 52302062 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 356361 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 651351111 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.914411 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.641831 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 410738698 63.50% 63.50% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 100810060 15.58% 79.08% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 43443549 6.72% 85.80% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 31018554 4.80% 90.59% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 22931602 3.54% 94.14% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 16104373 2.49% 96.63% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 11033021 1.71% 98.33% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 6462279 1.00% 99.33% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 4331858 0.67% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 416907124 64.01% 64.01% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 99553383 15.28% 79.29% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 43434757 6.67% 85.96% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 30928180 4.75% 90.71% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 22872426 3.51% 94.22% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 16003542 2.46% 96.68% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 10950121 1.68% 98.36% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 6425711 0.99% 99.34% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 4275867 0.66% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 646873994 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 651351111 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 2999808 25.24% 25.24% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 22948 0.19% 25.43% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 2663 0.02% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 3 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4871857 40.99% 66.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 3988147 33.55% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 2977313 25.58% 25.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 21726 0.19% 25.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 2146 0.02% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 1 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4737742 40.71% 66.50% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 3899084 33.50% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 4 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 406422040 67.84% 67.84% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 1476912 0.25% 68.09% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 65361 0.01% 68.10% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 96 0.00% 68.10% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.10% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.10% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.10% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.10% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 1 0.00% 68.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 58788 0.01% 68.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.11% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 108073598 18.04% 86.15% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 82993236 13.85% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 69 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 404218599 67.87% 67.87% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1425375 0.24% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 67506 0.01% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 50 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 58410 0.01% 68.13% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.13% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.13% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.13% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 106977397 17.96% 86.09% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 82855084 13.91% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 599090036 # Type of FU issued -system.cpu0.iq.rate 0.893155 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 11885426 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.019839 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1856813329 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 695962848 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 576693438 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 984019 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 489184 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 438468 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 610449620 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 525838 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 4726109 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 595602490 # Type of FU issued +system.cpu0.iq.rate 0.881457 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 11638012 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.019540 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1854047614 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 692214073 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 573874162 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 1006644 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 498985 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 447097 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 606702343 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 538090 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 4757420 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 16731454 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 21127 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 684950 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 9161643 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 16585910 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 22662 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 668240 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 9092320 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 3853062 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 8592397 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 3863731 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 7820378 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 5329290 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 14836046 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 7169747 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 614106722 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 1810261 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 101681556 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 86254396 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 13499171 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 248453 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 6830033 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 684950 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 2723761 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 2339558 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 5063319 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 592213762 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 105878130 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 5990174 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 5300378 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 15293530 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 9669423 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 610970772 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 1799898 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 101145902 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 86060501 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 13228626 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 242900 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 9335617 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 668240 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 2719159 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 2323934 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 5043093 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 588743474 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 104791307 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 5960112 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 136530 # number of nop insts executed -system.cpu0.iew.exec_refs 187756937 # number of memory reference insts executed -system.cpu0.iew.exec_branches 109862908 # Number of branches executed -system.cpu0.iew.exec_stores 81878807 # Number of stores executed -system.cpu0.iew.exec_rate 0.882903 # Inst execution rate -system.cpu0.iew.wb_sent 578421970 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 577131906 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 284711853 # num instructions producing a value -system.cpu0.iew.wb_consumers 494921051 # num instructions consuming a value +system.cpu0.iew.exec_nop 136543 # number of nop insts executed +system.cpu0.iew.exec_refs 186525171 # number of memory reference insts executed +system.cpu0.iew.exec_branches 109265890 # Number of branches executed +system.cpu0.iew.exec_stores 81733864 # Number of stores executed +system.cpu0.iew.exec_rate 0.871306 # Inst execution rate +system.cpu0.iew.wb_sent 575597633 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 574321259 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 283300170 # num instructions producing a value +system.cpu0.iew.wb_consumers 492230600 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.860418 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.575267 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.849962 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.575544 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 81841846 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 15496017 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 4520537 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 632994694 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.840706 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.831217 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 81268346 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 15211411 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 4500525 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 637573218 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.830670 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.824266 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 436057133 68.89% 68.89% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 98370072 15.54% 84.43% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 33369017 5.27% 89.70% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 15116509 2.39% 92.09% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 10820224 1.71% 93.80% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 6529796 1.03% 94.83% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 6075579 0.96% 95.79% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 3929496 0.62% 96.41% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 22726868 3.59% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 442173264 69.35% 69.35% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 97173464 15.24% 84.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 33154077 5.20% 89.79% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 15182673 2.38% 92.18% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 10793922 1.69% 93.87% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 6469162 1.01% 94.88% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 6019139 0.94% 95.83% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 3912878 0.61% 96.44% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 22694639 3.56% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 632994694 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 453175477 # Number of instructions committed -system.cpu0.commit.committedOps 532162399 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 637573218 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 450633299 # Number of instructions committed +system.cpu0.commit.committedOps 529613227 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 162042855 # Number of memory references committed -system.cpu0.commit.loads 84950102 # Number of loads committed -system.cpu0.commit.membars 3716655 # Number of memory barriers committed -system.cpu0.commit.branches 101218853 # Number of branches committed -system.cpu0.commit.fp_insts 419354 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 488117298 # Number of committed integer instructions. -system.cpu0.commit.function_calls 13243427 # Number of function calls committed. +system.cpu0.commit.refs 161528172 # Number of memory references committed +system.cpu0.commit.loads 84559991 # Number of loads committed +system.cpu0.commit.membars 3687184 # Number of memory barriers committed +system.cpu0.commit.branches 100678778 # Number of branches committed +system.cpu0.commit.fp_insts 428537 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 486019598 # Number of committed integer instructions. +system.cpu0.commit.function_calls 13276351 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 368889724 69.32% 69.32% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 1132190 0.21% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 48139 0.01% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 49491 0.01% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 84950102 15.96% 85.51% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 77092753 14.49% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 366882155 69.27% 69.27% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1103700 0.21% 69.48% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 50072 0.01% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 49128 0.01% 69.50% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.50% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.50% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.50% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 84559991 15.97% 85.47% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 76968181 14.53% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 532162399 # Class of committed instruction -system.cpu0.commit.bw_lim_events 22726868 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 1220262369 # The number of ROB reads -system.cpu0.rob.rob_writes 1241914021 # The number of ROB writes -system.cpu0.timesIdled 4040058 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 23883390 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 52531652861 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 453175477 # Number of Instructions Simulated -system.cpu0.committedOps 532162399 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.480127 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.480127 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.675618 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.675618 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 698520758 # number of integer regfile reads -system.cpu0.int_regfile_writes 411524007 # number of integer regfile writes -system.cpu0.fp_regfile_reads 797183 # number of floating regfile reads -system.cpu0.fp_regfile_writes 468068 # number of floating regfile writes -system.cpu0.cc_regfile_reads 128308023 # number of cc regfile reads -system.cpu0.cc_regfile_writes 129504102 # number of cc regfile writes -system.cpu0.misc_regfile_reads 1200484287 # number of misc regfile reads -system.cpu0.misc_regfile_writes 15629054 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 10737693 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.983333 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 307043958 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 10738205 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 28.593602 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 1675743000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 201.777727 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 310.205606 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.394097 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.605870 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999967 # Average percentage of cache occupancy +system.cpu0.commit.op_class_0::total 529613227 # Class of committed instruction +system.cpu0.commit.bw_lim_events 22694639 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 1221719500 # The number of ROB reads +system.cpu0.rob.rob_writes 1235563732 # The number of ROB writes +system.cpu0.timesIdled 4062222 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 24351091 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 46889510422 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 450633299 # Number of Instructions Simulated +system.cpu0.committedOps 529613227 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.499450 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.499450 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.666911 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.666911 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 694532138 # number of integer regfile reads +system.cpu0.int_regfile_writes 409756453 # number of integer regfile writes +system.cpu0.fp_regfile_reads 813886 # number of floating regfile reads +system.cpu0.fp_regfile_writes 470480 # number of floating regfile writes +system.cpu0.cc_regfile_reads 126655644 # number of cc regfile reads +system.cpu0.cc_regfile_writes 127915254 # number of cc regfile writes +system.cpu0.misc_regfile_reads 1202729248 # number of misc regfile reads +system.cpu0.misc_regfile_writes 15348526 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 10661519 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.983500 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 305118964 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 10662031 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 28.617340 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 1659069500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 285.071495 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 226.912005 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.556780 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.443188 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999968 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 175 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 316 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1354997138 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1354997138 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 80652766 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 81489620 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 162142386 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 67583074 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 68792819 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 136375893 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 205065 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 202220 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 407285 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 153643 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data 172343 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 325986 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1812235 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1802328 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 3614563 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2053127 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 2077480 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 4130607 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 148235840 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 150282439 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 298518279 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 148440905 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 150484659 # number of overall hits -system.cpu0.dcache.overall_hits::total 298925564 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 6532573 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 6224591 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 12757164 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 6661148 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 6436273 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 13097421 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 707910 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 622488 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 1330398 # number of SoftPFReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 634041 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu1.data 606833 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 1240874 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 305625 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 336516 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 642141 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 9 # number of StoreCondReq misses +system.cpu0.dcache.tags.tag_accesses 1346452186 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 1346452186 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 80589927 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 80681589 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 161271516 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 67520868 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 67884168 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 135405036 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 204627 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 201539 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 406166 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 174874 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu1.data 149966 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 324840 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1793684 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1773233 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 3566917 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2041252 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 2056052 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 4097304 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 148110795 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 148565757 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 296676552 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 148315422 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 148767296 # number of overall hits +system.cpu0.dcache.overall_hits::total 297082718 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 6173656 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 6486433 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 12660089 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 6585609 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 6413253 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 12998862 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 647829 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 671589 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 1319418 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 637368 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu1.data 603972 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 1241340 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 307807 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 348230 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 656037 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 8 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::cpu1.data 3 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 13193721 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 12660864 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 25854585 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 13901631 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 13283352 # number of overall misses -system.cpu0.dcache.overall_misses::total 27184983 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 101439335987 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 96122979264 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 197562315251 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 231140325721 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 230924128196 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 462064453917 # number of WriteReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 18916873838 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu1.data 17351565044 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 36268438882 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 3997419982 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 4421548736 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 8418968718 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 187500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 109500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 297000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 332579661708 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 327047107460 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 659626769168 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 332579661708 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 327047107460 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 659626769168 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 87185339 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 87714211 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 174899550 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 74244222 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 75229092 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 149473314 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 912975 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 824708 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 1737683 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 787684 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu1.data 779176 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 1566860 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2117860 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 2138844 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 4256704 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2053136 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 2077483 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 4130619 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 161429561 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 162943303 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 324372864 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 162342536 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 163768011 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 326110547 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.074927 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.070964 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.072940 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.089719 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.085556 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.087624 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.775388 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.754798 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.765616 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.804943 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.778814 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.791950 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.144308 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.157335 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.150854 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_misses::total 11 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 12759265 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 12899686 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 25658951 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 13407094 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 13571275 # number of overall misses +system.cpu0.dcache.overall_misses::total 26978369 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 95102935500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 99484470500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 194587406000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 227327993853 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 219936608514 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 447264602367 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 33983690404 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data 32156071893 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 66139762297 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4002448500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 4417133500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 8419582000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 243500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 108000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 351500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 322430929353 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 319421079014 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 641852008367 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 322430929353 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 319421079014 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 641852008367 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 86763583 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 87168022 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 173931605 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 74106477 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 74297421 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 148403898 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 852456 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 873128 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 1725584 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 812242 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu1.data 753938 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 1566180 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2101491 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 2121463 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 4222954 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2041260 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 2056055 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 4097315 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 160870060 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 161465443 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 322335503 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 161722516 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 162338571 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 324061087 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.071155 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.074413 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.072788 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.088867 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.086319 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.087591 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.759956 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.769176 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.764621 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.784702 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.801090 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.792591 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.146471 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.164146 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.155350 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000004 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000001 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000003 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.081731 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.077701 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.079706 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.085631 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.081111 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.083361 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15528.236116 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15442.457065 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15486.382024 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34699.773331 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 35878.547755 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 35279.041112 # average WriteReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 29835.411019 # average WriteInvalidateReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 28593.641157 # average WriteInvalidateReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 29228.139909 # average WriteInvalidateReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13079.492784 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13139.193191 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13110.778969 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 20833.333333 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 36500 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24750 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25207.419628 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 25831.341957 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 25512.951346 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23923.787195 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 24620.826690 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 24264.380418 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 52126007 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 51266 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 3578465 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 1028 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.566583 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 49.869650 # average number of cycles each access was blocked +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.079314 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.079891 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.079603 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.082902 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.083599 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.083251 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15404.637949 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15337.315671 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15370.145186 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34518.902330 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 34294.079543 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 34407.981435 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 53318.789779 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 53240.997750 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 53280.940191 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13003.110715 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12684.528903 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12834.004789 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 30437.500000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 36000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 31954.545455 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25270.337230 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 24761.926687 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 25014.740796 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24049.277894 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 23536.556367 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 23791.357008 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 66975280 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 45752 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 3575735 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 1017 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 18.730493 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 44.987217 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 8209351 # number of writebacks -system.cpu0.dcache.writebacks::total 8209351 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3628927 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 3346283 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 6975210 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5547863 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 5347347 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 10895210 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 3396 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 3377 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 6773 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 184138 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 204631 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 388769 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 9176790 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 8693630 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 17870420 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 9176790 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 8693630 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 17870420 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2903646 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 2878308 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 5781954 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1113285 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 1088926 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 2202211 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 695379 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 617800 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 1313179 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 630645 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 603456 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 1234101 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 121487 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 131885 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 253372 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 9 # number of StoreCondReq MSHR misses +system.cpu0.dcache.writebacks::writebacks 8160945 # number of writebacks +system.cpu0.dcache.writebacks::total 8160945 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3346545 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 3573146 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 6919691 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5483385 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 5330407 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 10813792 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 3566 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu1.data 3327 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 6893 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 188282 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 213819 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 402101 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 8829930 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 8903553 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 17733483 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 8829930 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 8903553 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 17733483 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2827111 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 2913287 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 5740398 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1102224 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 1082846 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 2185070 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 638719 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 656171 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 1294890 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 633802 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data 600645 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 1234447 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 119525 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 134411 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 253936 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 8 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 3 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 4016931 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 3967234 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 7984165 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 4712310 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 4585034 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 9297344 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16397 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 17283 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.StoreCondReq_mshr_misses::total 11 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 3929335 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 3996133 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 7925468 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 4568054 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 4652304 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 9220358 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 17396 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 16284 # number of ReadReq MSHR uncacheable system.cpu0.dcache.ReadReq_mshr_uncacheable::total 33680 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 17951 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 15746 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 18911 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 14786 # number of WriteReq MSHR uncacheable system.cpu0.dcache.WriteReq_mshr_uncacheable::total 33697 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 34348 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 33029 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 36307 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 31070 # number of overall MSHR uncacheable misses system.cpu0.dcache.overall_mshr_uncacheable_misses::total 67377 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43556644701 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 43095096417 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 86651741118 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 39142786504 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 39217956097 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 78360742601 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 11875956517 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 9839614769 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 21715571286 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 17839341538 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 16312287276 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 34151628814 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1586128009 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1744790264 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 3330918273 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 174000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43970285000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 44965591500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 88935876500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 39469232389 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 38108394120 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 77577626509 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 10196891500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 11887921500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 22084813000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 33197271404 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 31430048393 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 64627319797 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1640365500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1815773000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 3456138500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 235500 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 105000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 279000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 82699431205 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 82313052514 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 165012483719 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 94575387722 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 92152667283 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 186728055005 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2796204500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2965118250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5761322750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2832162536 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2783504957 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5615667493 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5628367036 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5748623207 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11376990243 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033304 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032815 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033059 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014995 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014475 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014733 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.761663 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.749114 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.755707 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.800632 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.774480 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.787627 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.057363 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.061662 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059523 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 340500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 83439517389 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 83073985620 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 166513503009 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 93636408889 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 94961907120 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 188598316009 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3034885000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2806255000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5841140000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3049818991 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2643724500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5693543491 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6084703991 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5449979500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11534683491 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.032584 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033422 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033004 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014874 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014574 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014724 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.749269 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.751518 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.750407 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.780312 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.796677 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.788190 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056876 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063358 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.060132 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000001 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000003 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024883 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024347 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.024614 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029027 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.027997 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.028510 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15000.673188 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14972.371413 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14986.584314 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35159.717866 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36015.262834 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35582.758692 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 17078.393965 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15926.861070 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16536.642214 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 28287.454175 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 27031.444341 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 27673.285099 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13055.948447 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13229.633878 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13146.355055 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19333.333333 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024426 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024749 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.024588 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028246 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028658 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.028453 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15553.080512 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15434.659029 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15492.980887 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35808.721629 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35192.810538 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35503.497146 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15964.597108 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18117.108955 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17055.358370 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 52377.984613 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 52327.162289 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 52353.255990 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13724.036812 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13509.110117 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13610.273849 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 29437.500000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 35000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23250 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20587.715150 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20748.222191 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20667.469137 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20069.856975 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20098.578829 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20084.021308 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 170531.469171 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171562.706127 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171060.651722 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 157771.853156 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 176775.368792 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 166651.853073 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 163863.020729 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 174047.752187 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 168855.696202 # average overall mshr uncacheable latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 30954.545455 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21235.022565 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20788.593778 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21009.926860 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20498.095883 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20411.801791 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20454.554586 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 174458.783628 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172332.043724 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173430.522565 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 161272.222040 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178799.168132 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 168962.919281 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 167590.381772 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 175409.703894 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 171196.157309 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 16169102 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.955735 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 173971503 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 16169614 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.759162 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 13124671250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 233.058192 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 278.897543 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.455192 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.544722 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999914 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 16142168 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.947517 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 172883065 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 16142680 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 10.709688 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 16340342500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 273.082606 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 238.864911 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.533364 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.466533 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999897 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 153 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 289 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 70 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 76 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 207520278 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 207520278 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 86520761 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 87450742 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 173971503 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 86520761 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 87450742 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 173971503 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 86520761 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 87450742 # number of overall hits -system.cpu0.icache.overall_hits::total 173971503 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 8615803 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 8763236 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 17379039 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 8615803 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 8763236 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 17379039 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 8615803 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 8763236 # number of overall misses -system.cpu0.icache.overall_misses::total 17379039 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 112931076635 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 114850105161 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 227781181796 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 112931076635 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 114850105161 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 227781181796 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 112931076635 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 114850105161 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 227781181796 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 95136564 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 96213978 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 191350542 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 95136564 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 96213978 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 191350542 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 95136564 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 96213978 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 191350542 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.090562 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.091081 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.090823 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.090562 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.091081 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.090823 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.090562 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.091081 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.090823 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13107.434865 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13105.901195 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13106.661525 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13107.434865 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13105.901195 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13106.661525 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13107.434865 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13105.901195 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13106.661525 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 82244 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 206401666 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 206401666 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 86191123 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 86691942 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 172883065 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 86191123 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 86691942 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 172883065 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 86191123 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 86691942 # number of overall hits +system.cpu0.icache.overall_hits::total 172883065 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 8665288 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 8710490 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 17375778 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 8665288 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 8710490 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 17375778 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 8665288 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 8710490 # number of overall misses +system.cpu0.icache.overall_misses::total 17375778 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 113689396380 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 113502001896 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 227191398276 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 113689396380 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 113502001896 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 227191398276 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 113689396380 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 113502001896 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 227191398276 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 94856411 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 95402432 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 190258843 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 94856411 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 95402432 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 190258843 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 94856411 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 95402432 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 190258843 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.091352 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.091303 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.091327 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.091352 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.091303 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.091327 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.091352 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.091303 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.091327 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13120.094379 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13030.495632 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13075.178463 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13120.094379 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13030.495632 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13075.178463 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13120.094379 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13030.495632 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13075.178463 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 86637 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 6699 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 7314 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 12.277056 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 11.845365 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 602016 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 607287 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 1209303 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 602016 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu1.inst 607287 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 1209303 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 602016 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu1.inst 607287 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 1209303 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 8013787 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 8155949 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 16169736 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 8013787 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 8155949 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 16169736 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 8013787 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 8155949 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 16169736 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 12341 # number of ReadReq MSHR uncacheable -system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst 8298 # number of ReadReq MSHR uncacheable -system.cpu0.icache.ReadReq_mshr_uncacheable::total 20639 # number of ReadReq MSHR uncacheable -system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 12341 # number of overall MSHR uncacheable misses -system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst 8298 # number of overall MSHR uncacheable misses -system.cpu0.icache.overall_mshr_uncacheable_misses::total 20639 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 95968094429 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 97614087232 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 193582181661 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 95968094429 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 97614087232 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 193582181661 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 95968094429 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 97614087232 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 193582181661 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 951349751 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 639066000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1590415751 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 951349751 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 639066000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 1590415751 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.084235 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.084769 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.084503 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.084235 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.084769 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.084503 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.084235 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.084769 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.084503 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11975.373744 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11968.452381 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11971.882637 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11975.373744 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11968.452381 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11971.882637 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11975.373744 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11968.452381 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11971.882637 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 77088.546390 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 77014.461316 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 77058.760163 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 77088.546390 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 77014.461316 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 77058.760163 # average overall mshr uncacheable latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 615328 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 617627 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 1232955 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 615328 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu1.inst 617627 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 1232955 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 615328 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu1.inst 617627 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 1232955 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 8049960 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 8092863 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 16142823 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 8049960 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 8092863 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 16142823 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 8049960 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 8092863 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 16142823 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 12465 # number of ReadReq MSHR uncacheable +system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst 8175 # number of ReadReq MSHR uncacheable +system.cpu0.icache.ReadReq_mshr_uncacheable::total 20640 # number of ReadReq MSHR uncacheable +system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 12465 # number of overall MSHR uncacheable misses +system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst 8175 # number of overall MSHR uncacheable misses +system.cpu0.icache.overall_mshr_uncacheable_misses::total 20640 # number of overall MSHR uncacheable misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 100646775925 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 100551252932 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 201198028857 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 100646775925 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 100551252932 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 201198028857 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 100646775925 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 100551252932 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 201198028857 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 965827500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 632670500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1598498000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 965827500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 632670500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 1598498000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.084865 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.084829 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.084847 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.084865 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.084829 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.084847 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.084865 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.084829 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.084847 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12502.767209 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12424.682456 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12463.621069 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12502.767209 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12424.682456 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12463.621069 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12502.767209 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12424.682456 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12463.621069 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 77483.152828 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 77390.886850 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 77446.608527 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 77483.152828 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 77390.886850 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 77446.608527 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 133788555 # Number of BP lookups -system.cpu1.branchPred.condPredicted 90573571 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 5908759 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 92439735 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 65341745 # Number of BTB hits +system.cpu1.branchPred.lookups 132830364 # Number of BP lookups +system.cpu1.branchPred.condPredicted 90187101 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 5886537 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 91288458 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 64898028 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 70.685777 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 17599042 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 188594 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 71.091165 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 17334778 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 185732 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1382,90 +1400,96 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 918015 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 918015 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 17288 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 94464 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 562013 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 356002 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 2214.229134 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 13073.684616 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-65535 353584 99.32% 99.32% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-131071 1851 0.52% 99.84% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::131072-196607 299 0.08% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::196608-262143 120 0.03% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::262144-327679 79 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::327680-393215 40 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::393216-458751 25 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 356002 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 421643 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 21453.513266 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 17357.718896 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 16015.202358 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 415023 98.43% 98.43% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 5756 1.37% 99.80% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 364 0.09% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 366 0.09% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 85 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 33 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 11 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 421643 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 354035793664 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.135779 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.675726 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-3 353071895664 99.73% 99.73% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-7 535230500 0.15% 99.88% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-11 190116000 0.05% 99.93% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-15 115191500 0.03% 99.97% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-19 44312000 0.01% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::20-23 22451500 0.01% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::24-27 21588500 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::28-31 29378000 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::32-35 5201500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::36-39 359000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::40-43 41000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::44-47 22500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::48-51 6000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 354035793664 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 94465 84.53% 84.53% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 17288 15.47% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 111753 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 918015 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 905180 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 905180 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 17142 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 92306 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 553484 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 351696 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 2321.493563 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 13592.585679 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-65535 349244 99.30% 99.30% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-131071 1804 0.51% 99.82% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-196607 390 0.11% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::196608-262143 114 0.03% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::262144-327679 67 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::327680-393215 32 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::393216-458751 30 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::458752-524287 6 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::524288-589823 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::589824-655359 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 351696 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 414217 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 22492.792425 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 18361.243775 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 16253.124731 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 322417 77.84% 77.84% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 82857 20.00% 97.84% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 6808 1.64% 99.48% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 1275 0.31% 99.79% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-163839 173 0.04% 99.83% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-196607 198 0.05% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-229375 298 0.07% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::229376-262143 83 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 62 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::294912-327679 12 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-360447 13 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::360448-393215 10 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::425984-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::491520-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 414217 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 326963093592 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.083701 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.672512 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-3 325992368092 99.70% 99.70% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-7 539476500 0.16% 99.87% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-11 187726500 0.06% 99.93% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-15 115407500 0.04% 99.96% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-19 46500000 0.01% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::20-23 23809500 0.01% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::24-27 21473500 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::28-31 29946500 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::32-35 5666000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::36-39 571000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::40-43 55000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::44-47 32500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::48-51 25000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::52-55 4000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::56-59 32000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 326963093592 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 92306 84.34% 84.34% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 17142 15.66% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 109448 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 905180 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 918015 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 111753 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 905180 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 109448 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 111753 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 1029768 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 109448 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 1014628 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 105548583 # DTB read hits -system.cpu1.dtb.read_misses 631805 # DTB read misses -system.cpu1.dtb.write_hits 82907544 # DTB write hits -system.cpu1.dtb.write_misses 286210 # DTB write misses -system.cpu1.dtb.flush_tlb 1083 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 105776812 # DTB read hits +system.cpu1.dtb.read_misses 627964 # DTB read misses +system.cpu1.dtb.write_hits 81868125 # DTB write hits +system.cpu1.dtb.write_misses 277216 # DTB write misses +system.cpu1.dtb.flush_tlb 1087 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 21604 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 553 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 56278 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 216 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 9625 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 21316 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 568 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 55232 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 212 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 8920 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 55021 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 106180388 # DTB read accesses -system.cpu1.dtb.write_accesses 83193754 # DTB write accesses +system.cpu1.dtb.perms_faults 54701 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 106404776 # DTB read accesses +system.cpu1.dtb.write_accesses 82145341 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 188456127 # DTB hits -system.cpu1.dtb.misses 918015 # DTB misses -system.cpu1.dtb.accesses 189374142 # DTB accesses +system.cpu1.dtb.hits 187644937 # DTB hits +system.cpu1.dtb.misses 905180 # DTB misses +system.cpu1.dtb.accesses 188550117 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1495,397 +1519,389 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 104751 # Table walker walks requested -system.cpu1.itb.walker.walksLong 104751 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 2979 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 72067 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 14103 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 90648 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 1509.569985 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 8604.112743 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-32767 89986 99.27% 99.27% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-65535 255 0.28% 99.55% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-98303 242 0.27% 99.82% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::98304-131071 116 0.13% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::131072-163839 27 0.03% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::163840-196607 14 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::196608-229375 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::229376-262143 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::262144-294911 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::294912-327679 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 90648 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 89149 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 26484.081515 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 22228.139492 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 17447.399907 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-32767 48433 54.33% 54.33% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-65535 39159 43.93% 98.25% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-98303 575 0.64% 98.90% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::98304-131071 708 0.79% 99.69% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-163839 93 0.10% 99.80% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::163840-196607 80 0.09% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-229375 45 0.05% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::229376-262143 20 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-294911 15 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::294912-327679 10 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::360448-393215 6 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::491520-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 89149 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 396982969624 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 1.388871 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -154312061728 -38.87% -38.87% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 551239764852 138.86% 99.99% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 48839000 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 5683000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 518000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::5 149500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::6 6000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::7 9000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::8 9000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::9 8500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::10 44500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 396982969624 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 72067 96.03% 96.03% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 2979 3.97% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 75046 # Table walker page sizes translated +system.cpu1.itb.walker.walks 106266 # Table walker walks requested +system.cpu1.itb.walker.walksLong 106266 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 3111 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 73302 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 14293 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 91973 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1630.543747 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 9941.577304 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-32767 90961 98.90% 98.90% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-65535 588 0.64% 99.54% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-98303 258 0.28% 99.82% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::98304-131071 90 0.10% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::131072-163839 38 0.04% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::163840-196607 13 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::196608-229375 7 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::229376-262143 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::262144-294911 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::294912-327679 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::327680-360447 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::360448-393215 5 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::458752-491519 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::491520-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 91973 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 90706 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 28271.216899 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 24128.368541 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 18525.575548 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 88461 97.52% 97.52% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 1926 2.12% 99.65% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 212 0.23% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 62 0.07% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 21 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 15 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 8 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 90706 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 610372252128 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.878972 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.326581 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 73947141376 12.12% 12.12% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 536358552252 87.87% 99.99% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 59179000 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 6640000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 645500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::5 94000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 610372252128 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 73302 95.93% 95.93% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 3111 4.07% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 76413 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 104751 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 104751 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 106266 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 106266 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 75046 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 75046 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 179797 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 96448537 # ITB inst hits -system.cpu1.itb.inst_misses 104751 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 76413 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 76413 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 182679 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 95636263 # ITB inst hits +system.cpu1.itb.inst_misses 106266 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1083 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 1087 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 21604 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 553 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 42139 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 21316 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 568 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 41371 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 204302 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 202868 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 96553288 # ITB inst accesses -system.cpu1.itb.hits 96448537 # DTB hits -system.cpu1.itb.misses 104751 # DTB misses -system.cpu1.itb.accesses 96553288 # DTB accesses -system.cpu1.numCycles 667631540 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 95742529 # ITB inst accesses +system.cpu1.itb.hits 95636263 # DTB hits +system.cpu1.itb.misses 106266 # DTB misses +system.cpu1.itb.accesses 95742529 # DTB accesses +system.cpu1.numCycles 670348620 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 247941482 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 595071407 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 133788555 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 82940787 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 381163571 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 13497944 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 2492160 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 22589 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 3825 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 5325029 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 172051 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 1992 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 96222293 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 3665245 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 41130 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 643871402 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.082515 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.328245 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 245802953 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 590871754 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 132830364 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 82232806 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 386445016 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 13431293 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 2639306 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 21635 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 4572 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 5276880 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 167481 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 2239 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 95410634 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 3652057 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 41964 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 647075459 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.068807 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.316374 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 496782409 77.16% 77.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 18583795 2.89% 80.04% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 18517016 2.88% 82.92% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 13597412 2.11% 85.03% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 28667245 4.45% 89.48% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 9152993 1.42% 90.90% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 9918803 1.54% 92.44% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 8570268 1.33% 93.77% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 40081461 6.23% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 501080801 77.44% 77.44% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 18371493 2.84% 80.28% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 18561867 2.87% 83.15% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 13401625 2.07% 85.22% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 28513625 4.41% 89.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 9105805 1.41% 91.03% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 9777924 1.51% 92.54% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 8450851 1.31% 93.85% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 39811468 6.15% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 643871402 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.200393 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.891317 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 201631753 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 315887121 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 107474204 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 13522341 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 5353840 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 20035378 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 1415024 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 649950843 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 4347472 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 5353840 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 209303047 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 22542941 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 254388545 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 113174340 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 39106401 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 634340427 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 84329 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 1777036 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 1562975 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 19949989 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 3657 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 605941232 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 974899397 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 750081260 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 811718 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 508709616 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 97231611 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 15188925 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 13206274 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 75533982 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 102194667 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 87314859 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 13957552 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 14774854 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 601797044 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 15287986 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 601499543 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 865295 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 81943902 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 52376442 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 362406 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 643871402 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.934192 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.656161 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 647075459 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.198151 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.881440 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 199983147 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 321798427 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 106352633 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 13609650 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 5329449 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 19773591 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 1406143 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 644884461 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 4323616 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 5329449 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 207655640 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 26665473 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 252746187 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 112130376 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 42545968 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 629384575 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 84102 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 2156884 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 1598140 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 23186474 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 3948 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 602389573 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 968798649 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 744085505 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 803060 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 505488932 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 96900641 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 15182115 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 13209558 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 75938042 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 101507501 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 86179777 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 13679637 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 14662477 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 596915130 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 15279603 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 597602438 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 863336 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 81541272 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 52071117 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 356106 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 647075459 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.923544 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.649381 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 408171960 63.39% 63.39% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 99067431 15.39% 78.78% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 44002532 6.83% 85.61% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 31313283 4.86% 90.48% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 23144485 3.59% 94.07% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 16264635 2.53% 96.60% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 11075626 1.72% 98.32% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 6519272 1.01% 99.33% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 4312178 0.67% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 412751344 63.79% 63.79% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 98711881 15.26% 79.04% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 43578879 6.73% 85.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 31028755 4.80% 90.57% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 23162473 3.58% 94.15% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 16109238 2.49% 96.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 10961200 1.69% 98.34% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 6490260 1.00% 99.34% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 4281429 0.66% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 643871402 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 647075459 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 3037678 26.20% 26.20% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 24339 0.21% 26.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 2694 0.02% 26.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 26.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 26.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 26.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 26.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 26.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 26.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 26.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 26.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 26.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 26.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 26.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 26.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 26.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 26.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 26.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 26.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 26.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 26.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 26.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 26.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 26.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 26.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 4 0.00% 26.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 26.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 26.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4607398 39.74% 66.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 3921783 33.83% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 3038725 25.54% 25.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 25345 0.21% 25.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 3128 0.03% 25.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 25.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 25.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 25.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 25.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 25.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 25.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 25.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 25.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 25.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 25.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 25.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 25.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 25.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 25.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 25.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 25.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 25.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 25.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 25.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 25.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 25.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 25.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 3 0.00% 25.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 25.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 25.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4885830 41.07% 66.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 3943683 33.15% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 408162511 67.86% 67.86% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 1426997 0.24% 68.09% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 69303 0.01% 68.11% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 134 0.00% 68.11% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.11% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.11% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.11% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.11% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 9 0.00% 68.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 14 0.00% 68.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 22 0.00% 68.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 70416 0.01% 68.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.12% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 107729216 17.91% 86.03% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 84040920 13.97% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 46 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 405061818 67.78% 67.78% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1472658 0.25% 68.03% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 66179 0.01% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 56 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 16 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 16 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 23 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 71237 0.01% 68.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.05% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 107954973 18.06% 86.12% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 82975408 13.88% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 601499543 # Type of FU issued -system.cpu1.iq.rate 0.900945 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 11593896 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.019275 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 1858238935 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 699228429 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 579923061 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 1090744 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 540881 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 488146 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 612510547 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 582891 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 4820885 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 597602438 # Type of FU issued +system.cpu1.iq.rate 0.891480 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 11896714 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.019907 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 1853948472 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 693931681 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 575193406 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 1091913 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 542260 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 485773 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 608916098 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 583008 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 4685337 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 16648209 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 23106 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 751890 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 9224511 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 16615869 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 21909 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 749717 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 9068365 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 4009170 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 7426024 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 3952894 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 8300380 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 5353840 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 14516681 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 6539646 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 617219827 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 1819635 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 102194667 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 87314859 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 12911400 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 240081 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 6211315 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 751890 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 2725767 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2332140 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 5057907 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 594561904 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 105538370 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 6033124 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 5329449 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 14829127 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 10212979 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 612328593 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 1790117 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 101507501 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 86179777 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 12919930 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 237071 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 9891044 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 749717 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 2710919 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2329182 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 5040101 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 590723670 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 105766513 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 5987554 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 134797 # number of nop insts executed -system.cpu1.iew.exec_refs 188445888 # number of memory reference insts executed -system.cpu1.iew.exec_branches 110364560 # Number of branches executed -system.cpu1.iew.exec_stores 82907518 # Number of stores executed -system.cpu1.iew.exec_rate 0.890554 # Inst execution rate -system.cpu1.iew.wb_sent 581679133 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 580411207 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 286057076 # num instructions producing a value -system.cpu1.iew.wb_consumers 496538403 # num instructions consuming a value +system.cpu1.iew.exec_nop 133860 # number of nop insts executed +system.cpu1.iew.exec_refs 187634979 # number of memory reference insts executed +system.cpu1.iew.exec_branches 109483047 # Number of branches executed +system.cpu1.iew.exec_stores 81868466 # Number of stores executed +system.cpu1.iew.exec_rate 0.881219 # Inst execution rate +system.cpu1.iew.wb_sent 576950915 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 575679179 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 284156915 # num instructions producing a value +system.cpu1.iew.wb_consumers 493402851 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.869359 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.576103 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.858776 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.575913 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 81975668 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 14925580 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 4513358 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 629946041 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.849503 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.842378 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 81583045 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 14923497 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4500070 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 633204147 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.838045 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.832186 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 433603733 68.83% 68.83% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 96615693 15.34% 84.17% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 33704251 5.35% 89.52% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 15419971 2.45% 91.97% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 10970958 1.74% 93.71% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 6585832 1.05% 94.75% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 6182969 0.98% 95.74% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 3954863 0.63% 96.36% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 22907771 3.64% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 438438352 69.24% 69.24% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 96042056 15.17% 84.41% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 33088291 5.23% 89.63% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 15382536 2.43% 92.06% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 10958189 1.73% 93.79% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 6612249 1.04% 94.84% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 6082014 0.96% 95.80% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3902550 0.62% 96.42% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 22697910 3.58% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 629946041 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 455165016 # Number of instructions committed -system.cpu1.commit.committedOps 535141123 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 633204147 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 451699475 # Number of instructions committed +system.cpu1.commit.committedOps 530653461 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 163636805 # Number of memory references committed -system.cpu1.commit.loads 85546457 # Number of loads committed -system.cpu1.commit.membars 3765916 # Number of memory barriers committed -system.cpu1.commit.branches 101697828 # Number of branches committed -system.cpu1.commit.fp_insts 467953 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 491500354 # Number of committed integer instructions. -system.cpu1.commit.function_calls 13521989 # Number of function calls committed. +system.cpu1.commit.refs 162003044 # Number of memory references committed +system.cpu1.commit.loads 84891632 # Number of loads committed +system.cpu1.commit.membars 3738235 # Number of memory barriers committed +system.cpu1.commit.branches 100868221 # Number of branches committed +system.cpu1.commit.fp_insts 465542 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 487126697 # Number of committed integer instructions. +system.cpu1.commit.function_calls 13297594 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 370285651 69.19% 69.19% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 1106053 0.21% 69.40% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 52121 0.01% 69.41% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.41% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.41% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.41% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.41% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.41% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.41% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.41% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.41% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.41% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.41% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.41% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.41% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.41% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.41% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.41% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.41% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.41% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.41% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.41% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.41% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.41% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.41% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 60451 0.01% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 85546457 15.99% 85.41% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 78090348 14.59% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 367411373 69.24% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 1128741 0.21% 69.45% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 49317 0.01% 69.46% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.46% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.46% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.46% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.46% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.46% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.46% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.46% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.46% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.46% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.46% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.46% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.46% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.46% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.46% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.46% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.46% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.46% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.46% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.46% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.46% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.46% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.46% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 60944 0.01% 69.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.47% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 84891632 16.00% 85.47% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 77111412 14.53% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 535141123 # Class of committed instruction -system.cpu1.commit.bw_lim_events 22907771 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 1220174232 # The number of ROB reads -system.cpu1.rob.rob_writes 1248183780 # The number of ROB writes -system.cpu1.timesIdled 4134360 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 23760138 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 48765821681 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 455165016 # Number of Instructions Simulated -system.cpu1.committedOps 535141123 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.466790 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.466790 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.681761 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.681761 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 701277155 # number of integer regfile reads -system.cpu1.int_regfile_writes 414494210 # number of integer regfile writes -system.cpu1.fp_regfile_reads 871148 # number of floating regfile reads -system.cpu1.fp_regfile_writes 523684 # number of floating regfile writes -system.cpu1.cc_regfile_reads 126609999 # number of cc regfile reads -system.cpu1.cc_regfile_writes 127812398 # number of cc regfile writes -system.cpu1.misc_regfile_reads 1197834701 # number of misc regfile reads -system.cpu1.misc_regfile_writes 15057964 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 40297 # Transaction distribution -system.iobus.trans_dist::ReadResp 40297 # Transaction distribution +system.cpu1.commit.op_class_0::total 530653461 # Class of committed instruction +system.cpu1.commit.bw_lim_events 22697910 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 1218827033 # The number of ROB reads +system.cpu1.rob.rob_writes 1238367651 # The number of ROB writes +system.cpu1.timesIdled 4095381 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 23273161 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 54406850213 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 451699475 # Number of Instructions Simulated +system.cpu1.committedOps 530653461 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.484059 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.484059 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.673828 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.673828 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 696515100 # number of integer regfile reads +system.cpu1.int_regfile_writes 411090108 # number of integer regfile writes +system.cpu1.fp_regfile_reads 864151 # number of floating regfile reads +system.cpu1.fp_regfile_writes 531144 # number of floating regfile writes +system.cpu1.cc_regfile_reads 126615327 # number of cc regfile reads +system.cpu1.cc_regfile_writes 127765048 # number of cc regfile writes +system.cpu1.misc_regfile_reads 1196239956 # number of misc regfile reads +system.cpu1.misc_regfile_writes 15044847 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 40301 # Transaction distribution +system.iobus.trans_dist::ReadResp 40301 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution -system.iobus.trans_dist::WriteResp 29907 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution +system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -1902,11 +1918,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230952 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230952 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230960 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230960 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353736 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353744 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1923,11 +1939,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334240 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334240 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334272 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7492192 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) @@ -1956,437 +1972,448 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 607055505 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 569059287 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 148389509 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147720000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 174500 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115457 # number of replacements -system.iocache.tags.tagsinuse 10.425424 # Cycle average of tags in use +system.iocache.tags.replacements 115460 # number of replacements +system.iocache.tags.tagsinuse 10.424672 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115473 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115476 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13090073143000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.544298 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.881126 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.221519 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.430070 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651589 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13093329887000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.544075 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.880598 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.221505 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.430037 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651542 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039641 # Number of tag accesses -system.iocache.tags.data_accesses 1039641 # Number of data accesses +system.iocache.tags.tag_accesses 1039677 # Number of tag accesses +system.iocache.tags.data_accesses 1039677 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8812 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8849 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8816 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8853 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8812 # number of demand (read+write) misses -system.iocache.demand_misses::total 8852 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8816 # number of demand (read+write) misses +system.iocache.demand_misses::total 8856 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8812 # number of overall misses -system.iocache.overall_misses::total 8852 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5072000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1661250694 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1666322694 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::realview.ethernet 352500 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 352500 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19868709302 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 19868709302 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5424500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1661250694 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1666675194 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5424500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1661250694 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1666675194 # number of overall miss cycles +system.iocache.overall_misses::realview.ide 8816 # number of overall misses +system.iocache.overall_misses::total 8856 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5069000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1614263059 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1619332059 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12613364228 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12613364228 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5420000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1614263059 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1619683059 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5420000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1614263059 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1619683059 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8812 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8849 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8816 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8853 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8812 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8852 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8816 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8856 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8812 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8852 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8816 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8856 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 188521.413300 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 188306.327721 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117500 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 117500 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186273.806551 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 186273.806551 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 188521.413300 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 188282.330999 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 188521.413300 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 188282.330999 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 113607 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137000 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 183106.063861 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 182913.369366 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118253.245969 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118253.245969 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135500 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 183106.063861 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 182891.040989 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135500 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 183106.063861 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 182891.040989 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 31017 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 16342 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3459 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.951842 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.967042 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106630 # number of writebacks -system.iocache.writebacks::total 106630 # number of writebacks +system.iocache.writebacks::writebacks 106629 # number of writebacks +system.iocache.writebacks::total 106629 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8812 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8849 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8816 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8853 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8812 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8852 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8816 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8856 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8812 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8852 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3142000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1201855604 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1204997604 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 193500 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 193500 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14322073410 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14322073410 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3335500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1201855604 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1205191104 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3335500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1201855604 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1205191104 # number of overall MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8816 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8856 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1173463059 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1176682059 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7280164228 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7280164228 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3420000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1173463059 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1176883059 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3420000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1173463059 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1176883059 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 84918.918919 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136388.516114 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 136173.308170 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 64500 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 64500 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134272.795039 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134272.795039 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 136388.516114 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 136149.017623 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 136388.516114 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 136149.017623 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87000 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133106.063861 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 132913.369366 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68253.245969 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68253.245969 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 133106.063861 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 132891.040989 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 133106.063861 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 132891.040989 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1412518 # number of replacements -system.l2c.tags.tagsinuse 65354.490513 # Cycle average of tags in use -system.l2c.tags.total_refs 31645259 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1474766 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 21.457817 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2643820000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 35783.123237 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 158.967100 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 249.670952 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3744.975731 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 12205.230455 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 164.981843 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 255.022053 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3435.700252 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 9356.818889 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.546007 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002426 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.003810 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.057144 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.186237 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002517 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.003891 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.052425 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.142774 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.997230 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 337 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 61911 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 333 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 503 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2841 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5066 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53373 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.005142 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.944687 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 297548374 # Number of tag accesses -system.l2c.tags.data_accesses 297548374 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 541623 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 186900 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 7965775 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 3551683 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 548604 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 190887 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 8107304 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 3470388 # number of ReadReq hits -system.l2c.ReadReq_hits::total 24563164 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 8209351 # number of Writeback hits -system.l2c.Writeback_hits::total 8209351 # number of Writeback hits -system.l2c.WriteInvalidateReq_hits::cpu0.data 352587 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::cpu1.data 361830 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::total 714417 # number of WriteInvalidateReq hits -system.l2c.UpgradeReq_hits::cpu0.data 4898 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 5089 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 9987 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 8 # number of SCUpgradeReq hits +system.l2c.tags.replacements 1395026 # number of replacements +system.l2c.tags.tagsinuse 65295.492166 # Cycle average of tags in use +system.l2c.tags.total_refs 50144400 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1458293 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 34.385682 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 15281090500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 35597.818988 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 166.792374 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 227.419292 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3927.975659 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 9604.860217 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 170.331373 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 255.084245 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3398.092398 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 11947.117619 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.543180 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002545 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.003470 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.059936 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.146559 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002599 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.003892 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.051851 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.182299 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.996330 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 361 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 62906 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 360 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 593 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2785 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5017 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 54411 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.005508 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.959869 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 445809940 # Number of tag accesses +system.l2c.tags.data_accesses 445809940 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 538533 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 183659 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 537301 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 193067 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1452560 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 8160945 # number of Writeback hits +system.l2c.Writeback_hits::total 8160945 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 5106 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 5035 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 10141 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 6 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 2 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 814701 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 785760 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 1600461 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 541623 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 186900 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 7965775 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 4366384 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 548604 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 190887 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 8107304 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 4256148 # number of demand (read+write) hits -system.l2c.demand_hits::total 26163625 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 541623 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 186900 # number of overall hits -system.l2c.overall_hits::cpu0.inst 7965775 # number of overall hits -system.l2c.overall_hits::cpu0.data 4366384 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 548604 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 190887 # number of overall hits -system.l2c.overall_hits::cpu1.inst 8107304 # number of overall hits -system.l2c.overall_hits::cpu1.data 4256148 # number of overall hits -system.l2c.overall_hits::total 26163625 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 2520 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2317 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 47910 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 162942 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 2554 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 2304 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 48528 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 151193 # number of ReadReq misses -system.l2c.ReadReq_misses::total 420268 # number of ReadReq misses -system.l2c.WriteInvalidateReq_misses::cpu0.data 278058 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::cpu1.data 241626 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::total 519684 # number of WriteInvalidateReq misses -system.l2c.UpgradeReq_misses::cpu0.data 18363 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 18249 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 36612 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_hits::total 8 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 801127 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 795359 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 1596486 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 7998143 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 8048835 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 16046978 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 3426730 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 3533561 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 6960291 # number of ReadSharedReq hits +system.l2c.InvalidateReq_hits::cpu0.data 362301 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::cpu1.data 359177 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::total 721478 # number of InvalidateReq hits +system.l2c.demand_hits::cpu0.dtb.walker 538533 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 183659 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 7998143 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 4227857 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 537301 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 193067 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 8048835 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 4328920 # number of demand (read+write) hits +system.l2c.demand_hits::total 26056315 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 538533 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 183659 # number of overall hits +system.l2c.overall_hits::cpu0.inst 7998143 # number of overall hits +system.l2c.overall_hits::cpu0.data 4227857 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 537301 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 193067 # number of overall hits +system.l2c.overall_hits::cpu1.inst 8048835 # number of overall hits +system.l2c.overall_hits::cpu1.data 4328920 # number of overall hits +system.l2c.overall_hits::total 26056315 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 2429 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 2264 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 2593 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 2507 # number of ReadReq misses +system.l2c.ReadReq_misses::total 9793 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 18387 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 18174 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 36561 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 2 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 281210 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 286240 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 567450 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 2520 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2317 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 47910 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 444152 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 2554 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 2304 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 48528 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 437433 # number of demand (read+write) misses -system.l2c.demand_misses::total 987718 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 2520 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 2317 # number of overall misses -system.l2c.overall_misses::cpu0.inst 47910 # number of overall misses -system.l2c.overall_misses::cpu0.data 444152 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 2554 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 2304 # number of overall misses -system.l2c.overall_misses::cpu1.inst 48528 # number of overall misses -system.l2c.overall_misses::cpu1.data 437433 # number of overall misses -system.l2c.overall_misses::total 987718 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 226047513 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 206307511 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 4115303294 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 15012705040 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 228872009 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 204494263 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 4127840290 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 13630721751 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 37752291671 # number of ReadReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::cpu0.data 2347926 # number of WriteInvalidateReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 2217929 # number of WriteInvalidateReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::total 4565855 # number of WriteInvalidateReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 282478467 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 293943100 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 576421567 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 81000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 81000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 162000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 28614775736 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 29088522937 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 57703298673 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 226047513 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 206307511 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 4115303294 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 43627480776 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 228872009 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 204494263 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 4127840290 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 42719244688 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 95455590344 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 226047513 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 206307511 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 4115303294 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 43627480776 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 228872009 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 204494263 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 4127840290 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 42719244688 # number of overall miss cycles -system.l2c.overall_miss_latency::total 95455590344 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 544143 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 189217 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 8013685 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 3714625 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 551158 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 193191 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 8155832 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 3621581 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 24983432 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 8209351 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 8209351 # number of Writeback accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu0.data 630645 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu1.data 603456 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::total 1234101 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 23261 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 23338 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 46599 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 9 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 284361 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 270457 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 554818 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 51722 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 43961 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 95683 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 151868 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 164132 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 316000 # number of ReadSharedReq misses +system.l2c.InvalidateReq_misses::cpu0.data 271501 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::cpu1.data 241468 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::total 512969 # number of InvalidateReq misses +system.l2c.demand_misses::cpu0.dtb.walker 2429 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 2264 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 51722 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 436229 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 2593 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 2507 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 43961 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 434589 # number of demand (read+write) misses +system.l2c.demand_misses::total 976294 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 2429 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 2264 # number of overall misses +system.l2c.overall_misses::cpu0.inst 51722 # number of overall misses +system.l2c.overall_misses::cpu0.data 436229 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 2593 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 2507 # number of overall misses +system.l2c.overall_misses::cpu1.inst 43961 # number of overall misses +system.l2c.overall_misses::cpu1.data 434589 # number of overall misses +system.l2c.overall_misses::total 976294 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 212763500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 201130500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 229023500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.itb.walker 219290000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 862207500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 279221000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 285672000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 564893000 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 160500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 79500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 240000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 28552328500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 27263762000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 55816090500 # number of ReadExReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu0.inst 4410990000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu1.inst 3717651000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 8128641000 # number of ReadCleanReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 13488162000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 15070468500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 28558630500 # number of ReadSharedReq miss cycles +system.l2c.InvalidateReq_miss_latency::cpu0.data 27681533000 # number of InvalidateReq miss cycles +system.l2c.InvalidateReq_miss_latency::cpu1.data 26039052000 # number of InvalidateReq miss cycles +system.l2c.InvalidateReq_miss_latency::total 53720585000 # number of InvalidateReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 212763500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 201130500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 4410990000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 42040490500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 229023500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 219290000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 3717651000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 42334230500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 93365569500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 212763500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 201130500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 4410990000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 42040490500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 229023500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 219290000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 3717651000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 42334230500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 93365569500 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 540962 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 185923 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 539894 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 195574 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1462353 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 8160945 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 8160945 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 23493 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 23209 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 46702 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 8 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 3 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 12 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 1095911 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 1072000 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 2167911 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 544143 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 189217 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 8013685 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 4810536 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 551158 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 193191 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 8155832 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 4693581 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 27151343 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 544143 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 189217 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 8013685 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 4810536 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 551158 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 193191 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 8155832 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 4693581 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 27151343 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.004631 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.012245 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.005979 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.043865 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.004634 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.011926 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.005950 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.041748 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.016822 # miss rate for ReadReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.440910 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.400404 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::total 0.421103 # miss rate for WriteInvalidateReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.789433 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.781944 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.785682 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.111111 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_accesses::total 11 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 1085488 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 1065816 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 2151304 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 8049865 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 8092796 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 16142661 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 3578598 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 3697693 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 7276291 # number of ReadSharedReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::cpu0.data 633802 # number of InvalidateReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::cpu1.data 600645 # number of InvalidateReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::total 1234447 # number of InvalidateReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 540962 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 185923 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 8049865 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 4664086 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 539894 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 195574 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 8092796 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 4763509 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 27032609 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 540962 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 185923 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 8049865 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 4664086 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 539894 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 195574 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 8092796 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 4763509 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 27032609 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.004490 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.012177 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.004803 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.012819 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.006697 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.782659 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.783058 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.782857 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.250000 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.333333 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.166667 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.256599 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.267015 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.261750 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.004631 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.012245 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.005979 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.092329 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.004634 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.011926 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.005950 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.093198 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.036378 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.004631 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.012245 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.005979 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.092329 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.004634 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.011926 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.005950 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.093198 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.036378 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 89701.394048 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 89040.790246 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 85896.541307 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 92135.269237 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 89613.159358 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 88756.190538 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 85061.001690 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 90154.449948 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 89829.089226 # average ReadReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data 8.444015 # average WriteInvalidateReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data 9.179182 # average WriteInvalidateReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::total 8.785829 # average WriteInvalidateReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 15383.023852 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 16107.353828 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 15744.061155 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 81000 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 81000 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 81000 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 101755.896789 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 101622.844246 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 101688.780814 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 89701.394048 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 89040.790246 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 85896.541307 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 98226.464760 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89613.159358 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 88756.190538 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 85061.001690 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 97658.943628 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 96642.554195 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 89701.394048 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 89040.790246 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 85896.541307 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 98226.464760 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89613.159358 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 88756.190538 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 85061.001690 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 97658.943628 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 96642.554195 # average overall miss latency +system.l2c.SCUpgradeReq_miss_rate::total 0.272727 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.261966 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.253756 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.257898 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.006425 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.005432 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.005927 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.042438 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.044388 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.043429 # miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_miss_rate::cpu0.data 0.428369 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::cpu1.data 0.402015 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::total 0.415546 # miss rate for InvalidateReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.004490 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.012177 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.006425 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.093529 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.004803 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.012819 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.005432 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.091233 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.036115 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.004490 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.012177 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.006425 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.093529 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.004803 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.012819 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.005432 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.091233 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.036115 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 87593.042404 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 88838.560071 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 88323.756267 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 87471.080973 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 88043.245175 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 15185.783434 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 15718.719049 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 15450.698832 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 80250 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 79500 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 80000 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 100408.735727 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 100806.272346 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 100602.522809 # average ReadExReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 85282.665017 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 84567.025318 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 84953.868503 # average ReadCleanReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 88815.036742 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 91819.197353 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 90375.412975 # average ReadSharedReq miss latency +system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 101957.388739 # average InvalidateReq miss latency +system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 107836.450379 # average InvalidateReq miss latency +system.l2c.InvalidateReq_avg_miss_latency::total 104724.817679 # average InvalidateReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 87593.042404 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 88838.560071 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 85282.665017 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 96372.525669 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 88323.756267 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 87471.080973 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 84567.025318 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 97412.107762 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 95632.636788 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 87593.042404 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 88838.560071 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 85282.665017 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 96372.525669 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 88323.756267 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 87471.080973 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 84567.025318 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 97412.107762 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 95632.636788 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2395,279 +2422,295 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 1194670 # number of writebacks -system.l2c.writebacks::total 1194670 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.dtb.walker 20 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.itb.walker 34 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.data 12 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.dtb.walker 15 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.itb.walker 35 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.data 9 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 126 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.dtb.walker 20 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.itb.walker 34 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 12 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.dtb.walker 15 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.itb.walker 35 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 9 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 126 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.dtb.walker 20 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.itb.walker 34 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 12 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.dtb.walker 15 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.itb.walker 35 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 9 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 126 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 2500 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2283 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 47910 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 162930 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 2539 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 2269 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 48527 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 151184 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 420142 # number of ReadReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::cpu0.data 278058 # number of WriteInvalidateReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data 241626 # number of WriteInvalidateReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::total 519684 # number of WriteInvalidateReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 18363 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 18249 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 36612 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 1 # number of SCUpgradeReq MSHR misses +system.l2c.writebacks::writebacks 1179151 # number of writebacks +system.l2c.writebacks::total 1179151 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.dtb.walker 19 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.itb.walker 38 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.dtb.walker 9 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.itb.walker 38 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 104 # number of ReadReq MSHR hits +system.l2c.ReadCleanReq_mshr_hits::cpu0.inst 1 # number of ReadCleanReq MSHR hits +system.l2c.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu0.data 10 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.data 12 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 22 # number of ReadSharedReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.dtb.walker 19 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.itb.walker 38 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 10 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.dtb.walker 9 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.itb.walker 38 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 12 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 127 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.dtb.walker 19 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.itb.walker 38 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 10 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.dtb.walker 9 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.itb.walker 38 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 12 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 127 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 2410 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2226 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 2584 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 2469 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 9689 # number of ReadReq MSHR misses +system.l2c.CleanEvict_mshr_misses::writebacks 1116 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 1116 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 18387 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 18174 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 36561 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 2 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 281210 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 286240 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 567450 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 2500 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 2283 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 47910 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 444140 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 2539 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 2269 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 48527 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 437424 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 987592 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 2500 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 2283 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 47910 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 444140 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 2539 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 2269 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 48527 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 437424 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 987592 # number of overall MSHR misses -system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 12341 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 16397 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 8298 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 17283 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 54319 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 17951 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 15746 # number of WriteReq MSHR uncacheable +system.l2c.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 284361 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 270457 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 554818 # number of ReadExReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 51721 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 43961 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::total 95682 # number of ReadCleanReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 151858 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 164120 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 315978 # number of ReadSharedReq MSHR misses +system.l2c.InvalidateReq_mshr_misses::cpu0.data 271501 # number of InvalidateReq MSHR misses +system.l2c.InvalidateReq_mshr_misses::cpu1.data 241468 # number of InvalidateReq MSHR misses +system.l2c.InvalidateReq_mshr_misses::total 512969 # number of InvalidateReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 2410 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 2226 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 51721 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 436219 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 2584 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 2469 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 43961 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 434577 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 976167 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 2410 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 2226 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 51721 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 436219 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 2584 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 2469 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 43961 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 434577 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 976167 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 12465 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 17396 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 8175 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 16284 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 54320 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 18911 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 14786 # number of WriteReq MSHR uncacheable system.l2c.WriteReq_mshr_uncacheable::total 33697 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 12341 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 34348 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 8298 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 33029 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 88016 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 193190761 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 175148007 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 3515798206 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 12982690710 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 195905009 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 173430261 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 3520714460 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 11743294499 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 32500171913 # number of ReadReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data 9375307322 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 8259706071 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::total 17635013393 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 326121860 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 324030745 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 650152605 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 68500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 68500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 137000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 25126437764 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 25538778563 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 50665216327 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 193190761 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 175148007 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 3515798206 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 38109128474 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 195905009 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 173430261 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 3520714460 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 37282073062 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 83165388240 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 193190761 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 175148007 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 3515798206 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 38109128474 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 195905009 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 173430261 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 3520714460 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 37282073062 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 83165388240 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 735361248 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2566401000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 493860500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2722892250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 6518514998 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2597122000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2578592496 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 5175714496 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 735361248 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5163523000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 493860500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5301484746 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 11694229494 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.004594 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.012066 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.005979 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.043862 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.004607 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.011745 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.005950 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.041745 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.016817 # mshr miss rate for ReadReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.440910 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.400404 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.421103 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.789433 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.781944 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.785682 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.111111 # mshr miss rate for SCUpgradeReq accesses +system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 12465 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 36307 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 8175 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 31070 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 88017 # number of overall MSHR uncacheable misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 186939500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 176128500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 202521000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 192107500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 757696500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 381648500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 377184000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 758832500 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 140500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 69500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 210000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 25708718500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 24559192000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 50267910500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 3893746000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 3278041000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 7171787000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 11968937500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 13428627500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 25397565000 # number of ReadSharedReq MSHR miss cycles +system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 24966523000 # number of InvalidateReq MSHR miss cycles +system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 23624372000 # number of InvalidateReq MSHR miss cycles +system.l2c.InvalidateReq_mshr_miss_latency::total 48590895000 # number of InvalidateReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 186939500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 176128500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 3893746000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 37677656000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 202521000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 192107500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 3278041000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 37987819500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 83594959000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 186939500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 176128500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 3893746000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 37677656000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 202521000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 192107500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 3278041000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 37987819500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 83594959000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 772594499 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2817435000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 505958000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2602704500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 6698691999 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2830764496 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2473673500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 5304437996 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 772594499 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5648199496 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 505958000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5076378000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 12003129995 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.004455 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.011973 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.004786 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.012624 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.006626 # mshr miss rate for ReadReq accesses +system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.782659 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.783058 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.782857 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.250000 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.333333 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.166667 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.256599 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.267015 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.261750 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.004594 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.012066 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.005979 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.092327 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.004607 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.011745 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005950 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.093196 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.036374 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.004594 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.012066 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.005979 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.092327 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.004607 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.011745 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005950 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.093196 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.036374 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 77276.304400 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 76718.356110 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 73383.389814 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 79682.628798 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 77158.333596 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76434.667695 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 72551.661137 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 77675.511291 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 77355.208270 # average ReadReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 33717.092556 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 34183.846403 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 33934.108791 # average WriteInvalidateReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17759.726624 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17756.082251 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17757.910111 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 68500 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 68500 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 68500 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 89351.153103 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 89221.557305 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 89285.780821 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 77276.304400 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 76718.356110 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73383.389814 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 85804.315022 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 77158.333596 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76434.667695 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72551.661137 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 85230.972836 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 84210.269261 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 77276.304400 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 76718.356110 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73383.389814 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 85804.315022 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77158.333596 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76434.667695 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72551.661137 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 85230.972836 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 84210.269261 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 59586.844502 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 156516.496920 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 59515.606170 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 157547.431002 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 120004.326258 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 144678.402317 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 163761.748762 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 153595.705730 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 59586.844502 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 150329.655293 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 59515.606170 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 160509.998668 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 132864.814284 # average overall mshr uncacheable latency +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.272727 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.261966 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.253756 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.257898 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.006425 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.005432 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.005927 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.042435 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.044384 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.043426 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.428369 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.402015 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.415546 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.004455 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.011973 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.006425 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.093527 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.004786 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.012624 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005432 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.091230 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.036111 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.004455 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.011973 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.006425 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.093527 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.004786 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.012624 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005432 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.091230 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.036111 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 77568.257261 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 79123.315364 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 78375 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 77807.816930 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 78201.723604 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20756.431174 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20754.044239 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20755.244660 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 70250 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 69500 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 70000 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 90408.735727 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 90806.272346 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 90602.522809 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 75283.656542 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 74567.025318 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 74954.401037 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78816.641204 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 81822.005240 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 80377.637051 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 91957.388739 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 97836.450379 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 94724.817679 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 77568.257261 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 79123.315364 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75283.656542 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 86373.257469 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 78375 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 77807.816930 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 74567.025318 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 87413.322610 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 85635.919878 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 77568.257261 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79123.315364 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75283.656542 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 86373.257469 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 78375 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 77807.816930 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 74567.025318 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 87413.322610 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 85635.919878 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 61981.107020 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 161958.783628 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 61890.886850 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 159832.013019 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 123319.072147 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 149688.778806 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 167298.356553 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 157415.734220 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 61981.107020 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 155567.782962 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 61890.886850 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 163385.194722 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 136372.859732 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 483310 # Transaction distribution -system.membus.trans_dist::ReadResp 483310 # Transaction distribution +system.membus.trans_dist::ReadReq 54320 # Transaction distribution +system.membus.trans_dist::ReadResp 484522 # Transaction distribution system.membus.trans_dist::WriteReq 33697 # Transaction distribution system.membus.trans_dist::WriteResp 33697 # Transaction distribution -system.membus.trans_dist::Writeback 1301300 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 626202 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 626202 # Transaction distribution -system.membus.trans_dist::UpgradeReq 37394 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 37396 # Transaction distribution -system.membus.trans_dist::ReadExReq 566817 # Transaction distribution -system.membus.trans_dist::ReadExResp 566817 # Transaction distribution +system.membus.trans_dist::Writeback 1285780 # Transaction distribution +system.membus.trans_dist::CleanEvict 222453 # Transaction distribution +system.membus.trans_dist::UpgradeReq 37353 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.membus.trans_dist::UpgradeResp 37356 # Transaction distribution +system.membus.trans_dist::ReadExReq 1066998 # Transaction distribution +system.membus.trans_dist::ReadExResp 1066998 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 430202 # Transaction distribution +system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution +system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6864 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4328173 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4457819 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335539 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 335539 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4793358 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4492142 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4621788 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342195 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 342195 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4963983 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 2212 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 174172012 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 174343786 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14081472 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14081472 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 188425258 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2786 # Total snoops (count) -system.membus.snoop_fanout::samples 3049369 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 172016940 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 172188714 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7259520 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7259520 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 179448234 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 2724 # Total snoops (count) +system.membus.snoop_fanout::samples 3239737 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3049369 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3239737 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3049369 # Request fanout histogram -system.membus.reqLayer0.occupancy 113801500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3239737 # Request fanout histogram +system.membus.reqLayer0.occupancy 113920999 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 51156 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5469002 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5444004 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 11041524273 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 8690318133 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 6008607805 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 8114396828 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 151555991 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 228917368 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -2711,54 +2754,57 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 18 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 25599599 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 25591523 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 2074158 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 25494018 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 33697 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 33697 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 8209351 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 1340869 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 1234101 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 46602 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 46614 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2167911 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2167911 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 32380531 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 29914539 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 911927 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2596271 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 65803268 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1036169984 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1212884202 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3059264 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8762408 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 2260875858 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 669395 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 37398155 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.057385 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.232578 # Request fanout histogram +system.toL2Bus.trans_dist::Writeback 9446739 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 18863436 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 46705 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 46716 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2151304 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2151304 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 16142823 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 7285144 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 1341111 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 1234447 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 48465856 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 32213596 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 910891 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2571300 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 84161643 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1034451264 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1125904618 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3051976 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8646848 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 2172054706 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 2184416 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 57389162 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.063529 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.243911 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 35252045 94.26% 94.26% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 2146110 5.74% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 53743303 93.65% 93.65% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 3645859 6.35% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 37398155 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 28102852815 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 57389162 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 36059386455 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 1161000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 1120500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 24319536063 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 24257498228 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 15088594286 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 14835156686 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 530670154 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 529789657 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 1505035766 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 1493165292 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 16426 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 16399 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt index 793637493..4ce945989 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt @@ -1,159 +1,159 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.824541 # Number of seconds simulated -sim_ticks 51824540977500 # Number of ticks simulated -final_tick 51824540977500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.832615 # Number of seconds simulated +sim_ticks 51832614542500 # Number of ticks simulated +final_tick 51832614542500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 636803 # Simulator instruction rate (inst/s) -host_op_rate 748315 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37012113234 # Simulator tick rate (ticks/s) -host_mem_usage 715168 # Number of bytes of host memory used -host_seconds 1400.21 # Real time elapsed on the host -sim_insts 891654507 # Number of instructions simulated -sim_ops 1047794539 # Number of ops (including micro ops) simulated +host_inst_rate 677235 # Simulator instruction rate (inst/s) +host_op_rate 795801 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 39828045805 # Simulator tick rate (ticks/s) +host_mem_usage 719272 # Number of bytes of host memory used +host_seconds 1301.41 # Real time elapsed on the host +sim_insts 881360160 # Number of instructions simulated +sim_ops 1035663034 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 127104 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 129344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 2579072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24306544 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 138752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 130240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2657396 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 26223832 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 397184 # Number of bytes read from this memory -system.physmem.bytes_read::total 56689468 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 2579072 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2657396 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5236468 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 77843520 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 134080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 130496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 2944516 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 40297840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 118912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 116992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2475952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 40549336 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 378752 # Number of bytes read from this memory +system.physmem.bytes_read::total 87146876 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 2944516 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2475952 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5420468 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 75611328 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 4 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 20576 # Number of bytes written to this memory -system.physmem.bytes_written::total 77864100 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1986 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2021 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 64583 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 379793 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2168 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2035 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 57644 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 409757 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6206 # Number of read requests responded to by this memory -system.physmem.num_reads::total 926193 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1216305 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 75631908 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2095 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2039 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 70534 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 629657 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1858 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1828 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 54568 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 633593 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 5918 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1402090 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1181427 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 1 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2572 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1218878 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2453 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2496 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 49765 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 469016 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 2677 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2513 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 51277 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 506012 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7664 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1093873 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 49765 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 51277 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 101042 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1502059 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1184000 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2587 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2518 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 56808 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 777461 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2294 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2257 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 47768 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 782313 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7307 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1681314 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 56808 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 47768 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 104576 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1458760 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 0 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 397 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1502456 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1502059 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2453 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2496 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 49765 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 469016 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 2677 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2513 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 51277 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 506409 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7664 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2596329 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 926193 # Number of read requests accepted -system.physmem.writeReqs 1833424 # Number of write requests accepted -system.physmem.readBursts 926193 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1833424 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 59238720 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 37632 # Total number of bytes read from write queue -system.physmem.bytesWritten 114125056 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 56689468 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 117195044 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 588 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 50220 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 36075 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 58169 # Per bank write bursts -system.physmem.perBankRdBursts::1 57047 # Per bank write bursts -system.physmem.perBankRdBursts::2 56978 # Per bank write bursts -system.physmem.perBankRdBursts::3 51307 # Per bank write bursts -system.physmem.perBankRdBursts::4 56070 # Per bank write bursts -system.physmem.perBankRdBursts::5 62899 # Per bank write bursts -system.physmem.perBankRdBursts::6 54110 # Per bank write bursts -system.physmem.perBankRdBursts::7 52791 # Per bank write bursts -system.physmem.perBankRdBursts::8 52847 # Per bank write bursts -system.physmem.perBankRdBursts::9 102886 # Per bank write bursts -system.physmem.perBankRdBursts::10 57805 # Per bank write bursts -system.physmem.perBankRdBursts::11 59371 # Per bank write bursts -system.physmem.perBankRdBursts::12 53186 # Per bank write bursts -system.physmem.perBankRdBursts::13 52009 # Per bank write bursts -system.physmem.perBankRdBursts::14 46290 # Per bank write bursts -system.physmem.perBankRdBursts::15 51840 # Per bank write bursts -system.physmem.perBankWrBursts::0 107643 # Per bank write bursts -system.physmem.perBankWrBursts::1 108842 # Per bank write bursts -system.physmem.perBankWrBursts::2 112436 # Per bank write bursts -system.physmem.perBankWrBursts::3 109534 # Per bank write bursts -system.physmem.perBankWrBursts::4 114716 # Per bank write bursts -system.physmem.perBankWrBursts::5 117944 # Per bank write bursts -system.physmem.perBankWrBursts::6 106840 # Per bank write bursts -system.physmem.perBankWrBursts::7 109826 # Per bank write bursts -system.physmem.perBankWrBursts::8 110854 # Per bank write bursts -system.physmem.perBankWrBursts::9 118905 # Per bank write bursts -system.physmem.perBankWrBursts::10 115046 # Per bank write bursts -system.physmem.perBankWrBursts::11 114249 # Per bank write bursts -system.physmem.perBankWrBursts::12 112384 # Per bank write bursts -system.physmem.perBankWrBursts::13 111972 # Per bank write bursts -system.physmem.perBankWrBursts::14 104755 # Per bank write bursts -system.physmem.perBankWrBursts::15 107258 # Per bank write bursts +system.physmem.bw_write::total 1459157 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1458760 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2587 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2518 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 56808 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 777461 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2294 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2257 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 47768 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 782710 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7307 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3140470 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1402090 # Number of read requests accepted +system.physmem.writeReqs 1184000 # Number of write requests accepted +system.physmem.readBursts 1402090 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1184000 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 89692096 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 41664 # Total number of bytes read from write queue +system.physmem.bytesWritten 75632192 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 87146876 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 75631908 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 651 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2247 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 142152 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 86151 # Per bank write bursts +system.physmem.perBankRdBursts::1 87375 # Per bank write bursts +system.physmem.perBankRdBursts::2 80357 # Per bank write bursts +system.physmem.perBankRdBursts::3 81721 # Per bank write bursts +system.physmem.perBankRdBursts::4 87059 # Per bank write bursts +system.physmem.perBankRdBursts::5 94652 # Per bank write bursts +system.physmem.perBankRdBursts::6 87531 # Per bank write bursts +system.physmem.perBankRdBursts::7 83073 # Per bank write bursts +system.physmem.perBankRdBursts::8 80243 # Per bank write bursts +system.physmem.perBankRdBursts::9 128909 # Per bank write bursts +system.physmem.perBankRdBursts::10 86457 # Per bank write bursts +system.physmem.perBankRdBursts::11 85414 # Per bank write bursts +system.physmem.perBankRdBursts::12 83586 # Per bank write bursts +system.physmem.perBankRdBursts::13 88109 # Per bank write bursts +system.physmem.perBankRdBursts::14 80365 # Per bank write bursts +system.physmem.perBankRdBursts::15 80437 # Per bank write bursts +system.physmem.perBankWrBursts::0 72704 # Per bank write bursts +system.physmem.perBankWrBursts::1 74469 # Per bank write bursts +system.physmem.perBankWrBursts::2 70529 # Per bank write bursts +system.physmem.perBankWrBursts::3 72860 # Per bank write bursts +system.physmem.perBankWrBursts::4 75808 # Per bank write bursts +system.physmem.perBankWrBursts::5 80444 # Per bank write bursts +system.physmem.perBankWrBursts::6 76110 # Per bank write bursts +system.physmem.perBankWrBursts::7 73633 # Per bank write bursts +system.physmem.perBankWrBursts::8 70562 # Per bank write bursts +system.physmem.perBankWrBursts::9 76081 # Per bank write bursts +system.physmem.perBankWrBursts::10 73660 # Per bank write bursts +system.physmem.perBankWrBursts::11 73767 # Per bank write bursts +system.physmem.perBankWrBursts::12 72713 # Per bank write bursts +system.physmem.perBankWrBursts::13 77059 # Per bank write bursts +system.physmem.perBankWrBursts::14 70231 # Per bank write bursts +system.physmem.perBankWrBursts::15 71123 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 141 # Number of times write queue was full causing retry -system.physmem.totGap 51824538352500 # Total gap between requests +system.physmem.numWrRetry 31 # Number of times write queue was full causing retry +system.physmem.totGap 51832611910500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43101 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 883077 # Read request sizes (log2) +system.physmem.readPktSize::6 1358974 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1830851 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 891893 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 27772 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 267 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 277 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 434 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 548 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 466 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 744 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 447 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1849 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 126 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 105 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 102 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 101 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 98 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 97 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 85 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 85 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 61 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 48 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1181427 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1369118 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 26985 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 376 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 299 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 442 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 427 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 463 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 477 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 766 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 841 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 338 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 144 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 146 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 107 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 107 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 101 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 89 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 69 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 49 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -165,186 +165,183 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1631 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1604 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1588 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1570 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1550 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1532 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1527 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1502 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1494 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1480 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1472 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1463 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1457 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 57426 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 60838 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 91061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 116478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 105808 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 96280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 97400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 91891 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 93113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 91599 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 92000 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 96823 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 95841 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 93430 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 103137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 95750 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 92354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 90761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 5397 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 5036 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 5548 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 7290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 7464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 6868 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 7069 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 7549 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 5718 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 5353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 5228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 5156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 4122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 3748 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 3811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 2228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1526 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 569 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 451 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 469 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 235 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 605479 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 286.324474 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 164.442500 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 326.472553 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 252649 41.73% 41.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 150060 24.78% 66.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 52055 8.60% 75.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 27939 4.61% 79.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 19251 3.18% 82.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 12886 2.13% 85.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 9838 1.62% 86.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 9006 1.49% 88.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 71795 11.86% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 605479 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 88964 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 10.404208 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 91.787630 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 88960 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::7168-8191 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-13311 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::21504-22527 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 88964 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 88964 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.044108 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.711925 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 17.727362 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-15 349 0.39% 0.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 86750 97.51% 97.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 775 0.87% 98.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 22 0.02% 98.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 52 0.06% 98.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 153 0.17% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 193 0.22% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 316 0.36% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 104 0.12% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 25 0.03% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 21 0.02% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 53 0.06% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 28 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 13 0.01% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 3 0.00% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 1 0.00% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 4 0.00% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 7 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 10 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 6 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 6 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 10 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 22 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 6 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::400-415 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::432-447 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::448-463 4 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::464-479 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 4 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 5 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::560-575 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::672-687 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::720-735 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::848-863 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::864-879 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 88964 # Writes before turning the bus around for reads -system.physmem.totQLat 11987590194 # Total ticks spent queuing -system.physmem.totMemAccLat 29342683944 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4628025000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12951.09 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::0 1627 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1594 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1574 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1554 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1528 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1499 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1460 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1444 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1433 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1423 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1412 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 16205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 18522 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 67973 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 68856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 68869 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 68651 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 68381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 71263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 71520 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 74085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 72568 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 72467 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 69770 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 69647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 70062 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 67493 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 67216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 66673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 661 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 653 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 686 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 438 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 419 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 401 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 423 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 102 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 564759 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 292.733658 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 169.256086 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 326.085017 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 228658 40.49% 40.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 138332 24.49% 64.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 49531 8.77% 73.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 28277 5.01% 78.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 20268 3.59% 82.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 14095 2.50% 84.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 11027 1.95% 86.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 10949 1.94% 88.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 63622 11.27% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 564759 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 67625 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 20.723608 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 277.022721 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 67622 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-16383 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::69632-73727 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 67625 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 67625 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.475091 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.957142 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 6.452813 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 76 0.11% 0.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 68 0.10% 0.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 65 0.10% 0.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 131 0.19% 0.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 63823 94.38% 94.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 440 0.65% 95.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 742 1.10% 96.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 499 0.74% 97.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 390 0.58% 97.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 489 0.72% 98.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 119 0.18% 98.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 25 0.04% 98.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 63 0.09% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 45 0.07% 99.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 39 0.06% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 22 0.03% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 448 0.66% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 23 0.03% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 39 0.06% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 24 0.04% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 5 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 5 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 23 0.03% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 5 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 67625 # Writes before turning the bus around for reads +system.physmem.totQLat 16718468525 # Total ticks spent queuing +system.physmem.totMemAccLat 42995449775 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 7007195000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11929.50 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31701.09 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.14 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.20 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.09 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.26 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30679.50 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.73 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.46 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.68 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.46 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.03 # Data bus utilization in percentage +system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 8.43 # Average write queue length when enqueuing -system.physmem.readRowHits 697250 # Number of row buffer hits during reads -system.physmem.writeRowHits 1406079 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.33 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.85 # Row buffer hit rate for writes -system.physmem.avgGap 18779612.66 # Average gap between requests -system.physmem.pageHitRate 77.65 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2300840640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1255419000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3505093800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5752820880 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3384927046800 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1312402504095 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29943494064750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34653637789965 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.672359 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49812972038958 # Time in different power states -system.physmem_0.memoryStateTime::REF 1730535300000 # Time in different power states +system.physmem.avgWrQLen 12.63 # Average write queue length when enqueuing +system.physmem.readRowHits 1132210 # Number of row buffer hits during reads +system.physmem.writeRowHits 886222 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.79 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.99 # Row buffer hit rate for writes +system.physmem.avgGap 20042849.21 # Average gap between requests +system.physmem.pageHitRate 78.14 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2158387560 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1177691625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 5365768200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3865689360 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3385453914960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1313258572845 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29947583060250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34658863084800 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.669107 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49819671489024 # Time in different power states +system.physmem_0.memoryStateTime::REF 1730804660000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 281033227292 # Time in different power states +system.physmem_0.memoryStateTime::ACT 282130972226 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2276580600 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1242181875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3714586200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5802341040 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3384927046800 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1307965107960 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29947386517500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34653314361975 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.666118 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49819438757970 # Time in different power states -system.physmem_1.memoryStateTime::REF 1730535300000 # Time in different power states +system.physmem_1.actEnergy 2111190480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1151939250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 5565417000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3792070080 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3385453914960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1310153724135 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29950306611750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34658534867655 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.662774 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49824215805224 # Time in different power states +system.physmem_1.memoryStateTime::REF 1730804660000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 274566508280 # Time in different power states +system.physmem_1.memoryStateTime::ACT 277593670776 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -398,64 +395,65 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 132927 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 132927 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 20422 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 96268 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 16 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 132911 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 132911 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 132911 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 116706 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 23749.820061 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 20399.632740 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 13626.974720 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 115779 99.21% 99.21% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 796 0.68% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 50 0.04% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 35 0.03% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 34 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 9 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 116706 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 17050777148 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.002177 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 -37117796 -0.22% -0.22% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 17087894944 100.22% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 17050777148 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 96268 82.50% 82.50% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 20422 17.50% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 116690 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 132927 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 130428 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 130428 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 20426 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 94161 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 14 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 130414 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 130414 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 130414 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 114601 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 25025.623686 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 21934.133741 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 14193.681922 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 113576 99.11% 99.11% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 877 0.77% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 64 0.06% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 43 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 23 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 10 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 114601 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples -626546628 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.597966 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.490309 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -251893296 40.20% 40.20% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 -374653332 59.80% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total -626546628 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 94162 82.17% 82.17% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 20426 17.83% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 114588 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 130428 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 132927 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 116690 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 130428 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 114588 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 116690 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 249617 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 114588 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 245016 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 83832092 # DTB read hits -system.cpu0.dtb.read_misses 101357 # DTB read misses -system.cpu0.dtb.write_hits 76051604 # DTB write hits -system.cpu0.dtb.write_misses 31570 # DTB write misses -system.cpu0.dtb.flush_tlb 51833 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 82615908 # DTB read hits +system.cpu0.dtb.read_misses 99897 # DTB read misses +system.cpu0.dtb.write_hits 75294881 # DTB write hits +system.cpu0.dtb.write_misses 30531 # DTB write misses +system.cpu0.dtb.flush_tlb 51838 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 21426 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 523 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 72699 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 21162 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 519 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 72657 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 4640 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 4653 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 9921 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 83933449 # DTB read accesses -system.cpu0.dtb.write_accesses 76083174 # DTB write accesses +system.cpu0.dtb.perms_faults 9875 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 82715805 # DTB read accesses +system.cpu0.dtb.write_accesses 75325412 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 159883696 # DTB hits -system.cpu0.dtb.misses 132927 # DTB misses -system.cpu0.dtb.accesses 160016623 # DTB accesses +system.cpu0.dtb.hits 157910789 # DTB hits +system.cpu0.dtb.misses 130428 # DTB misses +system.cpu0.dtb.accesses 158041217 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -485,96 +483,90 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 78456 # Table walker walks requested -system.cpu0.itb.walker.walksLong 78456 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 4330 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 68323 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 78456 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 78456 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 78456 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 72653 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 26725.888828 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 23461.567658 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 16011.465624 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-32767 35910 49.43% 49.43% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-65535 35653 49.07% 98.50% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-98303 362 0.50% 99.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::98304-131071 571 0.79% 99.78% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-163839 12 0.02% 99.80% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::163840-196607 51 0.07% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-229375 22 0.03% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::229376-262143 28 0.04% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-294911 22 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::294912-327679 7 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-360447 6 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::360448-393215 6 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 72653 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples -294752296 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 -294752296 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total -294752296 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 68323 94.04% 94.04% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 4330 5.96% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 72653 # Table walker page sizes translated +system.cpu0.itb.walker.walks 77694 # Table walker walks requested +system.cpu0.itb.walker.walksLong 77694 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 4299 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 67844 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 77694 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 77694 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 77694 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 72143 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 28108.645329 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 25072.463875 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 16528.773937 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 70985 98.39% 98.39% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 998 1.38% 99.78% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 60 0.08% 99.86% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 53 0.07% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 28 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 14 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 72143 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples -294780296 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -294780296 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total -294780296 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 67844 94.04% 94.04% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 4299 5.96% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 72143 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 78456 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 78456 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 77694 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 77694 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 72653 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 72653 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 151109 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 446243730 # ITB inst hits -system.cpu0.itb.inst_misses 78456 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 72143 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 72143 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 149837 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 440762049 # ITB inst hits +system.cpu0.itb.inst_misses 77694 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 51833 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 51838 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 21426 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 523 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 53592 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 21162 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 519 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 53801 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 446322186 # ITB inst accesses -system.cpu0.itb.hits 446243730 # DTB hits -system.cpu0.itb.misses 78456 # DTB misses -system.cpu0.itb.accesses 446322186 # DTB accesses -system.cpu0.numCycles 51824649281 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 440839743 # ITB inst accesses +system.cpu0.itb.hits 440762049 # DTB hits +system.cpu0.itb.misses 77694 # DTB misses +system.cpu0.itb.accesses 440839743 # DTB accesses +system.cpu0.numCycles 51832801454 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 445966277 # Number of instructions committed -system.cpu0.committedOps 524229812 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 481463261 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 467774 # Number of float alu accesses -system.cpu0.num_func_calls 26556698 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 68063516 # number of instructions that are conditional controls -system.cpu0.num_int_insts 481463261 # number of integer instructions -system.cpu0.num_fp_insts 467774 # number of float instructions -system.cpu0.num_int_register_reads 701970788 # number of times the integer registers were read -system.cpu0.num_int_register_writes 382111523 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 750606 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 404844 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 116882787 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 116605188 # number of times the CC registers were written -system.cpu0.num_mem_refs 159874579 # number of memory refs -system.cpu0.num_load_insts 83829017 # Number of load instructions -system.cpu0.num_store_insts 76045562 # Number of store instructions -system.cpu0.num_idle_cycles 50231597014.033707 # Number of idle cycles -system.cpu0.num_busy_cycles 1593052266.966292 # Number of busy cycles -system.cpu0.not_idle_fraction 0.030739 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.969261 # Percentage of idle cycles -system.cpu0.Branches 99615402 # Number of branches fetched +system.cpu0.committedInsts 440492275 # Number of instructions committed +system.cpu0.committedOps 517776891 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 475595742 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 442272 # Number of float alu accesses +system.cpu0.num_func_calls 26261796 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 67159010 # number of instructions that are conditional controls +system.cpu0.num_int_insts 475595742 # number of integer instructions +system.cpu0.num_fp_insts 442272 # number of float instructions +system.cpu0.num_int_register_reads 692983656 # number of times the integer registers were read +system.cpu0.num_int_register_writes 377245689 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 706646 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 389336 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 115273932 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 114990138 # number of times the CC registers were written +system.cpu0.num_mem_refs 157900832 # number of memory refs +system.cpu0.num_load_insts 82612008 # Number of load instructions +system.cpu0.num_store_insts 75288824 # Number of store instructions +system.cpu0.num_idle_cycles 50243492062.967224 # Number of idle cycles +system.cpu0.num_busy_cycles 1589309391.032773 # Number of busy cycles +system.cpu0.not_idle_fraction 0.030662 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.969338 # Percentage of idle cycles +system.cpu0.Branches 98397494 # Number of branches fetched system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 363413760 69.28% 69.28% # Class of executed instruction -system.cpu0.op_class::IntMult 1135542 0.22% 69.50% # Class of executed instruction -system.cpu0.op_class::IntDiv 49216 0.01% 69.51% # Class of executed instruction +system.cpu0.op_class::IntAlu 358993131 69.29% 69.29% # Class of executed instruction +system.cpu0.op_class::IntMult 1071583 0.21% 69.50% # Class of executed instruction +system.cpu0.op_class::IntDiv 48336 0.01% 69.51% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction system.cpu0.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction @@ -597,174 +589,174 @@ system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.51% # Cl system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.51% # Class of executed instruction system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.51% # Class of executed instruction system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 60094 0.01% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 58966 0.01% 69.52% # Class of executed instruction system.cpu0.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::MemRead 83829017 15.98% 85.50% # Class of executed instruction -system.cpu0.op_class::MemWrite 76045562 14.50% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 82612008 15.95% 85.47% # Class of executed instruction +system.cpu0.op_class::MemWrite 75288824 14.53% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 524533192 # Class of executed instruction +system.cpu0.op_class::total 518072849 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 16327 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 10196087 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.965694 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 309323716 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 10196599 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 30.335969 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 3500850250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 229.651609 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 282.314085 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.448538 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.551395 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999933 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 16267 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 10037940 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.966034 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 305864730 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 10038452 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 30.469312 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 3466781500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 221.416582 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 290.549452 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.432454 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.567479 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999934 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 398 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 60 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 394 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1288720346 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1288720346 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 78289930 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 78118799 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 156408729 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 72116454 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 72389955 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 144506409 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 198225 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 194517 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 392742 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 165535 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data 168546 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 334081 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1870803 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1796237 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 3667040 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2023404 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 1945934 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 3969338 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 150406384 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 150508754 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 300915138 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 150604609 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 150703271 # number of overall hits -system.cpu0.dcache.overall_hits::total 301307880 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 2655491 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 2654704 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 5310195 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1102314 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1104773 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2207087 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 646482 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 651674 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 1298156 # number of SoftPFReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 617789 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu1.data 615381 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 1233170 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 153457 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 150527 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 303984 # number of LoadLockedReq misses +system.cpu0.dcache.tags.tag_accesses 1274123450 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 1274123450 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 77217599 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 77513026 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 154730625 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 71443407 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 71419351 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 142862758 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 195522 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 192929 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 388451 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 168757 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu1.data 166793 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 335550 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1811257 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1789885 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 3601142 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1962197 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 1939338 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 3901535 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 148661006 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 148932377 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 297593383 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 148856528 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 149125306 # number of overall hits +system.cpu0.dcache.overall_hits::total 297981834 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 2588533 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 2647536 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 5236069 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1081685 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 1087089 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2168774 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 633947 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 631509 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 1265456 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 612829 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu1.data 615985 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 1228814 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 151773 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 150295 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 302068 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 1 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::cpu1.data 1 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3757805 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 3759477 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 7517282 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 4404287 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 4411151 # number of overall misses -system.cpu0.dcache.overall_misses::total 8815438 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41854028250 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 42227875003 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 84081903253 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 32373542448 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 33874267614 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 66247810062 # number of WriteReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 16528493005 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu1.data 16264164501 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 32792657506 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2255480492 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 2210676726 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 4466157218 # number of LoadLockedReq miss cycles +system.cpu0.dcache.demand_misses::cpu0.data 3670218 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 3734625 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 7404843 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 4304165 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 4366134 # number of overall misses +system.cpu0.dcache.overall_misses::total 8670299 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41004192000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 41620421500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 82624613500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 31575309500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 31406770000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 62982079500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 25211350000 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data 25725023500 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 50936373500 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2229514000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 2184997000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 4414511000 # number of LoadLockedReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 82000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 82000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 164000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 74227570698 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 76102142617 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 150329713315 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 74227570698 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 76102142617 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 150329713315 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 80945421 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 80773503 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 161718924 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 73218768 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 73494728 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 146713496 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 844707 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 846191 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 1690898 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 783324 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu1.data 783927 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 1567251 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2024260 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 1946764 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 3971024 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2023405 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 1945935 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 3969340 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 154164189 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 154268231 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 308432420 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 155008896 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 155114422 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 310123318 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.032806 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.032866 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.032836 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.015055 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.015032 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.015044 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.765333 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.770126 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.767732 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.788676 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.784998 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.786836 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.075809 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.077322 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.076551 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000000 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 33000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 115000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 72579501500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 73027191500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 145606693000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 72579501500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 73027191500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 145606693000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 79806132 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 80160562 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 159966694 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 72525092 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 72506440 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 145031532 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 829469 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 824438 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 1653907 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 781586 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu1.data 782778 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 1564364 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1963030 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 1940180 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 3903210 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1962198 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 1939339 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 3901537 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 152331224 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 152667002 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 304998226 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 153160693 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 153491440 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 306652133 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.032435 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033028 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.032732 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.014915 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014993 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.014954 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.764281 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.765987 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.765131 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.784084 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.786922 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.785504 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.077316 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.077464 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.077390 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000001 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000001 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.024375 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.024370 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.024373 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028413 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028438 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.028426 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15761.314292 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15906.811081 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15834.051904 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 29368.712044 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 30661.744643 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 30015.948652 # average WriteReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 26754.268860 # average WriteInvalidateReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 26429.422587 # average WriteInvalidateReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 26592.162886 # average WriteInvalidateReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14697.801286 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14686.247158 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14692.079906 # average LoadLockedReq miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.024094 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.024463 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.024278 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028102 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028445 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.028274 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15840.706686 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15720.436474 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15779.893943 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 29190.854546 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 28890.707201 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 29040.406930 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 41139.290079 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 41762.418728 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 41451.654604 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14689.793310 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14538.055158 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14614.295457 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 82000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 82000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19752.906470 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20242.747227 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 19997.881324 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16853.481778 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17252.218892 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 17053.005570 # average overall miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 33000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 57500 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19775.256265 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 19554.089500 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 19663.711033 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16862.620624 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16725.824608 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 16793.733757 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -773,220 +765,220 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 7866652 # number of writebacks -system.cpu0.dcache.writebacks::total 7866652 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 7707 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 8547 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 16254 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 10563 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 10564 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 21127 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 35866 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 35610 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 71476 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 18270 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 19111 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 37381 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 18270 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 19111 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 37381 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2647784 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 2646157 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 5293941 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1091751 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 1094209 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 2185960 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 645721 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 650689 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 1296410 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 617789 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 615381 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 1233170 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 117591 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 114917 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 232508 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.writebacks::writebacks 7725236 # number of writebacks +system.cpu0.dcache.writebacks::total 7725236 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 11311 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 11844 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 23155 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 9967 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 11283 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 21250 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 36142 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 35738 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 71880 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 21278 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 23127 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 44405 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 21278 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 23127 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 44405 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2577222 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 2635692 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 5212914 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1071718 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 1075806 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 2147524 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 633158 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 630543 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 1263701 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 612829 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data 615985 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 1228814 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 115631 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 114557 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 230188 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 1 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 1 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 3739535 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 3740366 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 7479901 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 4385256 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 4391055 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 8776311 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 17713 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 15993 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 33706 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16112 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 17598 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 33710 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 33825 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 33591 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 67416 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 37598794000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 37923223247 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 75522017247 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 30337029302 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 31768716886 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 62105746188 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 9761049258 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 10401680524 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 20162729782 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 15601809495 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 15341092999 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 30942902494 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1519625500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1476118000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 2995743500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 80500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 80500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 161000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 67935823302 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 69691940133 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 137627763435 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 77696872560 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 80093620657 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 157790493217 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2993163000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2758056250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5751219250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2831783000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2786803750 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5618586750 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5824946000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5544860000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11369806000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.032711 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032760 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.032735 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014911 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014888 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014900 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.764432 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.768962 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.766699 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.788676 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.784998 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.786836 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.058091 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.059030 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.058551 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000000 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 3648940 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 3711498 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 7360438 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 4282098 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 4342041 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 8624139 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 17286 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 16418 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 33704 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16057 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 17652 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 33709 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 33343 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 34070 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 67413 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 38167566000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 38688442500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 76856008500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 30213193500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 29970900500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 60184094000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 10061362000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 10320868500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 20382230500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 24598521000 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 25109038500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 49707559500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1553845500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1517429500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 3071275000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 81000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 113000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 68380759500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 68659343000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 137040102500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 78442121500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 78980211500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 157422333000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2977259000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2853920500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5831179500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2866948000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2828284500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5695232500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5844207000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5682205000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11526412000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.032294 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032880 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.032587 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014777 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014837 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014807 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.763329 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.764816 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.764070 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.784084 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.786922 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.785504 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.058904 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.059045 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.058974 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000001 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000001 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024257 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024246 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.024251 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028290 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028308 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.028299 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14200.098649 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14331.433565 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14265.745925 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27787.498525 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29033.499894 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28411.199742 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15116.512020 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15985.640642 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15552.741634 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 25254.268844 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 24929.422584 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25092.162876 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12922.974547 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12845.079492 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12884.474943 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 80500 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 80500 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 80500 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18166.917358 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18632.385209 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18399.677139 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17717.750699 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18240.177055 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17979.136475 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 168981.143793 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172453.964234 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 170628.945885 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 175756.144489 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 158359.117513 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 166674.184218 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 172208.307465 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 165069.810366 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 168651.447728 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023954 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024311 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.024133 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027958 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028288 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.028124 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14809.576358 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14678.665982 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14743.387000 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28191.365173 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27859.019656 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28024.876090 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15890.760284 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16368.223103 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16128.997682 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 40139.290079 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 40762.418728 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 40451.654604 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13437.966462 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13246.065278 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13342.463552 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 81000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 32000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 56500 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18739.896929 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18499.092011 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18618.471143 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18318.618934 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18189.651249 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18253.686890 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172235.277103 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173828.755025 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173011.497152 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 178548.172137 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 160224.592114 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 168952.876087 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 175275.380140 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 166780.305254 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 170982.036106 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 13976964 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.880033 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 878227495 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 13977476 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 62.831622 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 35142475250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 257.003288 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 254.876744 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.501960 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.497806 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999766 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 13866895 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.854828 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 868036851 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 13867407 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 62.595469 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 43293883500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 253.434107 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 258.420721 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.494988 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.504728 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999716 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 220 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 213 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 185 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 906182457 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 906182457 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 439239656 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 438987839 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 878227495 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 439239656 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 438987839 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 878227495 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 439239656 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 438987839 # number of overall hits -system.cpu0.icache.overall_hits::total 878227495 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 7004074 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 6973407 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 13977481 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 7004074 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 6973407 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 13977481 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 7004074 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 6973407 # number of overall misses -system.cpu0.icache.overall_misses::total 13977481 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 93843146430 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 93562942727 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 187406089157 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 93843146430 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 93562942727 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 187406089157 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 93843146430 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 93562942727 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 187406089157 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 446243730 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 445961246 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 892204976 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 446243730 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 445961246 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 892204976 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 446243730 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 445961246 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 892204976 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015696 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015637 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.015666 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015696 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015637 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.015666 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015696 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015637 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.015666 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13398.365927 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13417.106262 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13407.715536 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13398.365927 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13417.106262 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13407.715536 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13398.365927 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13417.106262 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13407.715536 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 895771675 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 895771675 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 433832015 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 434204836 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 868036851 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 433832015 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 434204836 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 868036851 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 433832015 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 434204836 # number of overall hits +system.cpu0.icache.overall_hits::total 868036851 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 6930034 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 6937378 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 13867412 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 6930034 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 6937378 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 13867412 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 6930034 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 6937378 # number of overall misses +system.cpu0.icache.overall_misses::total 13867412 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 93266994500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 92872882000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 186139876500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 93266994500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 92872882000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 186139876500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 93266994500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 92872882000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 186139876500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 440762049 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 441142214 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 881904263 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 440762049 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 441142214 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 881904263 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 440762049 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 441142214 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 881904263 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015723 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015726 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.015724 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015723 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015726 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.015724 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015723 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015726 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.015724 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13458.374735 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13387.317514 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13422.827309 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13458.374735 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13387.317514 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13422.827309 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13458.374735 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13387.317514 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13422.827309 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -995,60 +987,60 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 7004074 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 6973407 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 13977481 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 7004074 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 6973407 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 13977481 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 7004074 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 6973407 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 13977481 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 25928 # number of ReadReq MSHR uncacheable -system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst 17197 # number of ReadReq MSHR uncacheable +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6930034 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 6937378 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 13867412 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 6930034 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 6937378 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 13867412 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 6930034 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 6937378 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 13867412 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 26185 # number of ReadReq MSHR uncacheable +system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst 16940 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable -system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 25928 # number of overall MSHR uncacheable misses -system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst 17197 # number of overall MSHR uncacheable misses +system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 26185 # number of overall MSHR uncacheable misses +system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst 16940 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 83323187568 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 83088246273 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 166411433841 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 83323187568 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 83088246273 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 166411433841 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 83323187568 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 83088246273 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 166411433841 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1928508500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 1282516750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3211025250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1928508500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 1282516750 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 3211025250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.015696 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015637 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.015666 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.015696 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015637 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.015666 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.015696 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015637 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.015666 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11896.388811 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11915.014608 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11905.681277 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11896.388811 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11915.014608 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11905.681277 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11896.388811 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11915.014608 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11905.681277 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 74379.377507 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 74577.935105 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 74458.556522 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 74379.377507 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 74577.935105 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 74458.556522 # average overall mshr uncacheable latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 86336960500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 85935504000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 172272464500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 86336960500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 85935504000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 172272464500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 86336960500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 85935504000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 172272464500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1959231000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 1269892000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3229123000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1959231000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 1269892000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 3229123000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.015723 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015726 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.015724 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.015723 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015726 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.015724 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.015723 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015726 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.015724 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12458.374735 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12387.317514 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12422.827309 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12458.374735 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12387.317514 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12422.827309 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12458.374735 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12387.317514 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12422.827309 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 74822.646553 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 74964.108619 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 74878.214493 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 74822.646553 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 74964.108619 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 74878.214493 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1079,73 +1071,76 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 130358 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 130358 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 20442 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 94115 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 7 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 130351 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 0.276177 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 74.962722 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-2047 130349 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walks 127806 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 127806 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 20371 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 91874 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 17 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 127789 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.297365 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 80.104866 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-2047 127787 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::22528-24575 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 130351 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 114564 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 23894.842621 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 20601.133760 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 13695.118153 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 72946 63.67% 63.67% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 40612 35.45% 99.12% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-98303 507 0.44% 99.56% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-131071 353 0.31% 99.87% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-163839 19 0.02% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::163840-196607 47 0.04% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-229375 10 0.01% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::229376-262143 28 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-294911 26 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 127789 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 112262 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 24820.406727 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 21828.616459 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 13574.434559 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 72880 64.92% 64.92% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 38528 34.32% 99.24% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 428 0.38% 99.62% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 314 0.28% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-163839 5 0.00% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-196607 36 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-229375 8 0.01% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::229376-262143 20 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 22 0.02% 99.98% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::294912-327679 5 0.00% 99.99% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::327680-360447 4 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::360448-393215 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-425983 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::360448-393215 7 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 114564 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 26318568 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 31.814872 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -811003296 -3081.49% -3081.49% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 837321864 3181.49% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 26318568 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 94116 82.16% 82.16% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 20442 17.84% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 114558 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 130358 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkCompletionTime::458752-491519 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 112262 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 8237382924 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.971809 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.165518 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 232218204 2.82% 2.82% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 8005164720 97.18% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 8237382924 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 91874 81.85% 81.85% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 20371 18.15% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 112245 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 127806 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 130358 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 114558 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 127806 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 112245 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 114558 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 244916 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 112245 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 240051 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 83582440 # DTB read hits -system.cpu1.dtb.read_misses 99281 # DTB read misses -system.cpu1.dtb.write_hits 76249670 # DTB write hits -system.cpu1.dtb.write_misses 31077 # DTB write misses -system.cpu1.dtb.flush_tlb 51825 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 82941587 # DTB read hits +system.cpu1.dtb.read_misses 97218 # DTB read misses +system.cpu1.dtb.write_hits 75253518 # DTB write hits +system.cpu1.dtb.write_misses 30588 # DTB write misses +system.cpu1.dtb.flush_tlb 51836 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 21270 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 540 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 73142 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 20662 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 534 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 71746 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4747 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4678 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 9967 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 83681721 # DTB read accesses -system.cpu1.dtb.write_accesses 76280747 # DTB write accesses +system.cpu1.dtb.perms_faults 9800 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 83038805 # DTB read accesses +system.cpu1.dtb.write_accesses 75284106 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 159832110 # DTB hits -system.cpu1.dtb.misses 130358 # DTB misses -system.cpu1.dtb.accesses 159962468 # DTB accesses +system.cpu1.dtb.hits 158195105 # DTB hits +system.cpu1.dtb.misses 127806 # DTB misses +system.cpu1.dtb.accesses 158322911 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1175,135 +1170,133 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 77021 # Table walker walks requested -system.cpu1.itb.walker.walksLong 77021 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 4430 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 67244 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 77021 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 77021 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 77021 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 71674 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 27071.277590 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 23813.549051 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 16581.978010 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-32767 34935 48.74% 48.74% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-65535 35570 49.63% 98.37% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-98303 418 0.58% 98.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::98304-131071 591 0.82% 99.78% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-163839 6 0.01% 99.79% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::163840-196607 60 0.08% 99.87% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-229375 17 0.02% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::229376-262143 30 0.04% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-294911 20 0.03% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::294912-327679 6 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-360447 6 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 77092 # Table walker walks requested +system.cpu1.itb.walker.walksLong 77092 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 4382 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 67241 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 77092 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 77092 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 77092 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 71623 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 28009.703587 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 25156.150396 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 15232.175605 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 36121 50.43% 50.43% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 34500 48.17% 98.60% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 359 0.50% 99.10% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 519 0.72% 99.83% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 9 0.01% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 46 0.06% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 17 0.02% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 23 0.03% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 12 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 5 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 3 0.00% 99.99% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::360448-393215 5 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-425983 2 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::425984-458751 2 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-491519 4 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::491520-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 71674 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -853687296 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -853687296 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -853687296 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 67244 93.82% 93.82% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 4430 6.18% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 71674 # Table walker page sizes translated +system.cpu1.itb.walker.walkCompletionTime::total 71623 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -887431296 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -887431296 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -887431296 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 67241 93.88% 93.88% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 4382 6.12% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 71623 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 77021 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 77021 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 77092 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 77092 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 71674 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 71674 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 148695 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 445961246 # ITB inst hits -system.cpu1.itb.inst_misses 77021 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 71623 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 71623 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 148715 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 441142214 # ITB inst hits +system.cpu1.itb.inst_misses 77092 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 51825 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 51836 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 21270 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 540 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 52758 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 20662 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 534 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 52225 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 446038267 # ITB inst accesses -system.cpu1.itb.hits 445961246 # DTB hits -system.cpu1.itb.misses 77021 # DTB misses -system.cpu1.itb.accesses 446038267 # DTB accesses -system.cpu1.numCycles 51824432674 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 441219306 # ITB inst accesses +system.cpu1.itb.hits 441142214 # DTB hits +system.cpu1.itb.misses 77092 # DTB misses +system.cpu1.itb.accesses 441219306 # DTB accesses +system.cpu1.numCycles 51832427631 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 445688230 # Number of instructions committed -system.cpu1.committedOps 523564727 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 480567684 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 428483 # Number of float alu accesses -system.cpu1.num_func_calls 26273151 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 68126466 # number of instructions that are conditional controls -system.cpu1.num_int_insts 480567684 # number of integer instructions -system.cpu1.num_fp_insts 428483 # number of float instructions -system.cpu1.num_int_register_reads 701499135 # number of times the integer registers were read -system.cpu1.num_int_register_writes 381123451 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 693452 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 356440 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 117557193 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 117240637 # number of times the CC registers were written -system.cpu1.num_mem_refs 159825990 # number of memory refs -system.cpu1.num_load_insts 83579816 # Number of load instructions -system.cpu1.num_store_insts 76246174 # Number of store instructions -system.cpu1.num_idle_cycles 50239290608.732407 # Number of idle cycles -system.cpu1.num_busy_cycles 1585142065.267594 # Number of busy cycles -system.cpu1.not_idle_fraction 0.030587 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.969413 # Percentage of idle cycles -system.cpu1.Branches 99529261 # Number of branches fetched +system.cpu1.committedInsts 440867885 # Number of instructions committed +system.cpu1.committedOps 517886143 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 475513559 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 454227 # Number of float alu accesses +system.cpu1.num_func_calls 26111235 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 67284853 # number of instructions that are conditional controls +system.cpu1.num_int_insts 475513559 # number of integer instructions +system.cpu1.num_fp_insts 454227 # number of float instructions +system.cpu1.num_int_register_reads 692532840 # number of times the integer registers were read +system.cpu1.num_int_register_writes 377153809 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 737892 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 372156 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 115804323 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 115491463 # number of times the CC registers were written +system.cpu1.num_mem_refs 158189082 # number of memory refs +system.cpu1.num_load_insts 82939410 # Number of load instructions +system.cpu1.num_store_insts 75249672 # Number of store instructions +system.cpu1.num_idle_cycles 50245805753.829796 # Number of idle cycles +system.cpu1.num_busy_cycles 1586621877.170202 # Number of busy cycles +system.cpu1.not_idle_fraction 0.030611 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.969389 # Percentage of idle cycles +system.cpu1.Branches 98435537 # Number of branches fetched system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 362846766 69.26% 69.26% # Class of executed instruction -system.cpu1.op_class::IntMult 1082718 0.21% 69.47% # Class of executed instruction -system.cpu1.op_class::IntDiv 48965 0.01% 69.48% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 50459 0.01% 69.49% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::MemRead 83579816 15.95% 85.45% # Class of executed instruction -system.cpu1.op_class::MemWrite 76246174 14.55% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 358757749 69.23% 69.23% # Class of executed instruction +system.cpu1.op_class::IntMult 1128666 0.22% 69.45% # Class of executed instruction +system.cpu1.op_class::IntDiv 49961 0.01% 69.46% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 51912 0.01% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::MemRead 82939410 16.01% 85.48% # Class of executed instruction +system.cpu1.op_class::MemWrite 75249672 14.52% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 523854940 # Class of executed instruction +system.cpu1.op_class::total 518177412 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.iobus.trans_dist::ReadReq 40327 # Transaction distribution -system.iobus.trans_dist::ReadResp 40327 # Transaction distribution +system.iobus.trans_dist::ReadReq 40326 # Transaction distribution +system.iobus.trans_dist::ReadResp 40326 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution -system.iobus.trans_dist::WriteResp 29907 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution +system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -1320,11 +1313,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231012 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231012 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231010 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231010 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353796 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353794 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1341,11 +1334,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334480 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334480 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334472 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334472 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492400 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7492392 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) @@ -1374,431 +1367,444 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 606981976 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 568807378 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 148423298 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147770000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 174500 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 115487 # number of replacements -system.iocache.tags.tagsinuse 10.456623 # Cycle average of tags in use +system.iocache.tags.tagsinuse 10.455201 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 115503 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13157342382000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.510546 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.946077 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.219409 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.434130 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.653539 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13165365743000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.510018 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.945183 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.219376 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.434074 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.653450 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039911 # Number of tag accesses -system.iocache.tags.data_accesses 1039911 # Number of data accesses +system.iocache.tags.tag_accesses 1039902 # Number of tag accesses +system.iocache.tags.data_accesses 1039902 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8842 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8879 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8841 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8878 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8842 # number of demand (read+write) misses -system.iocache.demand_misses::total 8882 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8841 # number of demand (read+write) misses +system.iocache.demand_misses::total 8881 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8842 # number of overall misses -system.iocache.overall_misses::total 8882 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5072000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1565914828 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1570986828 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::realview.ethernet 352500 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 352500 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19799416850 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 19799416850 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5424500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1565914828 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1571339328 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5424500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1565914828 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1571339328 # number of overall miss cycles +system.iocache.overall_misses::realview.ide 8841 # number of overall misses +system.iocache.overall_misses::total 8881 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5069000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1579254237 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1584323237 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12612931141 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12612931141 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5420000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1579254237 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1584674237 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5420000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1579254237 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1584674237 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8842 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8879 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8841 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8878 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8842 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8882 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8841 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8881 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8842 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8882 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8841 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8881 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 177099.618638 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 176932.855952 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117500 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 117500 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 185624.173573 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 185624.173573 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 177099.618638 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 176912.781806 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 177099.618638 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 176912.781806 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 107527 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137000 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 178628.462504 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 178454.971503 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118249.185677 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118249.185677 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135500 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 178628.462504 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 178434.212026 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135500 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 178628.462504 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 178434.212026 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 30353 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 16113 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3277 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.673307 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.262435 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106630 # number of writebacks -system.iocache.writebacks::total 106630 # number of writebacks +system.iocache.writebacks::writebacks 106631 # number of writebacks +system.iocache.writebacks::total 106631 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8842 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8879 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8841 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8878 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8842 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8882 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8841 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8881 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8842 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8882 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3142000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1105053392 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1108195392 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 193500 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 193500 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14252856882 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14252856882 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3335500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1105053392 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1108388892 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3335500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1105053392 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1108388892 # number of overall MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8841 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8881 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1137204237 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1140423237 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7279731141 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7279731141 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3420000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1137204237 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1140624237 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3420000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1137204237 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1140624237 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 84918.918919 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 124977.764307 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 124810.833652 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 64500 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 64500 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133623.873866 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133623.873866 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 124977.764307 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 124790.462959 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 124977.764307 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 124790.462959 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87000 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 128628.462504 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 128454.971503 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68249.185677 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68249.185677 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 128628.462504 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 128434.212026 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 128628.462504 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 128434.212026 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1294928 # number of replacements -system.l2c.tags.tagsinuse 65284.624377 # Cycle average of tags in use -system.l2c.tags.total_refs 28063625 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1358068 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 20.664374 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 7589253000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 38468.321907 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 163.057226 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 246.703748 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3367.231509 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 9600.385059 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 149.839093 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 239.160217 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3055.361096 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 9994.564521 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.586980 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002488 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.003764 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.051380 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.146490 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002286 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.003649 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.046621 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.152505 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.996164 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 237 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 62903 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 236 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 413 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2457 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5430 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 54571 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.003616 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.959824 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 267604060 # Number of tag accesses -system.l2c.tags.data_accesses 267604060 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 246478 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 166336 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 6965395 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 3278179 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 243308 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 165231 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 6932947 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 3267656 # number of ReadReq hits -system.l2c.ReadReq_hits::total 21265530 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 7866652 # number of Writeback hits -system.l2c.Writeback_hits::total 7866652 # number of Writeback hits -system.l2c.WriteInvalidateReq_hits::cpu0.data 360316 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::cpu1.data 364967 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::total 725283 # number of WriteInvalidateReq hits -system.l2c.UpgradeReq_hits::cpu0.data 4896 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 4962 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 9858 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 821407 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 805470 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 1626877 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 246478 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 166336 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 6965395 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 4099586 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 243308 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 165231 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 6932947 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 4073126 # number of demand (read+write) hits -system.l2c.demand_hits::total 22892407 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 246478 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 166336 # number of overall hits -system.l2c.overall_hits::cpu0.inst 6965395 # number of overall hits -system.l2c.overall_hits::cpu0.data 4099586 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 243308 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 165231 # number of overall hits -system.l2c.overall_hits::cpu1.inst 6932947 # number of overall hits -system.l2c.overall_hits::cpu1.data 4073126 # number of overall hits -system.l2c.overall_hits::total 22892407 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 1986 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2021 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 38679 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 132917 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 2168 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 2035 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 40460 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 144107 # number of ReadReq misses -system.l2c.ReadReq_misses::total 364373 # number of ReadReq misses -system.l2c.WriteInvalidateReq_misses::cpu0.data 257472 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::cpu1.data 250414 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::total 507886 # number of WriteInvalidateReq misses -system.l2c.UpgradeReq_misses::cpu0.data 17895 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 17622 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 35517 # number of UpgradeReq misses +system.l2c.tags.replacements 1260623 # number of replacements +system.l2c.tags.tagsinuse 65280.532461 # Cycle average of tags in use +system.l2c.tags.total_refs 43887253 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1323818 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 33.152029 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 38344006500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 38235.631490 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 193.327159 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 255.763508 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4002.247331 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 10061.721412 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 140.225182 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 222.893104 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2612.785728 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 9555.937547 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.583429 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002950 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.003903 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.061069 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.153530 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002140 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.003401 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.039868 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.145812 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.996102 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 327 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 62868 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 327 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 408 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2451 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5488 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 54479 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.004990 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.959290 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 393981982 # Number of tag accesses +system.l2c.tags.data_accesses 393981982 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 238329 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 162891 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 232955 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 163054 # number of ReadReq hits +system.l2c.ReadReq_hits::total 797229 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 7725236 # number of Writeback hits +system.l2c.Writeback_hits::total 7725236 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 4940 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 4801 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 9741 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 806406 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 815086 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 1621492 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 6885661 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 6899737 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 13785398 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 3189949 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 3243555 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 6433504 # number of ReadSharedReq hits +system.l2c.InvalidateReq_hits::cpu0.data 361245 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::cpu1.data 357794 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::total 719039 # number of InvalidateReq hits +system.l2c.demand_hits::cpu0.dtb.walker 238329 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 162891 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 6885661 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 3996355 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 232955 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 163054 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 6899737 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 4058641 # number of demand (read+write) hits +system.l2c.demand_hits::total 22637623 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 238329 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 162891 # number of overall hits +system.l2c.overall_hits::cpu0.inst 6885661 # number of overall hits +system.l2c.overall_hits::cpu0.data 3996355 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 232955 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 163054 # number of overall hits +system.l2c.overall_hits::cpu1.inst 6899737 # number of overall hits +system.l2c.overall_hits::cpu1.data 4058641 # number of overall hits +system.l2c.overall_hits::total 22637623 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 2095 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 2039 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 1858 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 1828 # number of ReadReq misses +system.l2c.ReadReq_misses::total 7820 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 17709 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 17217 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 34926 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 247554 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 266155 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 513709 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 1986 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2021 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 38679 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 380471 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 2168 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 2035 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 40460 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 410262 # number of demand (read+write) misses -system.l2c.demand_misses::total 878082 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 1986 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 2021 # number of overall misses -system.l2c.overall_misses::cpu0.inst 38679 # number of overall misses -system.l2c.overall_misses::cpu0.data 380471 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 2168 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 2035 # number of overall misses -system.l2c.overall_misses::cpu1.inst 40460 # number of overall misses -system.l2c.overall_misses::cpu1.data 410262 # number of overall misses -system.l2c.overall_misses::total 878082 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 170354500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 177467000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 3182312556 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 11047112258 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 186335000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 177844750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 3318730008 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 12078497021 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 30338653093 # number of ReadReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::cpu0.data 123996 # number of WriteInvalidateReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::total 123996 # number of WriteInvalidateReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 276678088 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 272829710 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 549507798 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_misses::cpu0.data 242663 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 238702 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 481365 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 44373 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 37641 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 82014 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 136062 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 137237 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 273299 # number of ReadSharedReq misses +system.l2c.InvalidateReq_misses::cpu0.data 251584 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::cpu1.data 258191 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::total 509775 # number of InvalidateReq misses +system.l2c.demand_misses::cpu0.dtb.walker 2095 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 2039 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 44373 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 378725 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 1858 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 1828 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 37641 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 375939 # number of demand (read+write) misses +system.l2c.demand_misses::total 844498 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 2095 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 2039 # number of overall misses +system.l2c.overall_misses::cpu0.inst 44373 # number of overall misses +system.l2c.overall_misses::cpu0.data 378725 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 1858 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 1828 # number of overall misses +system.l2c.overall_misses::cpu1.inst 37641 # number of overall misses +system.l2c.overall_misses::cpu1.data 375939 # number of overall misses +system.l2c.overall_misses::total 844498 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 179866500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 180146000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 162156000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.itb.walker 158214500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 680383000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 276798500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 263076500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 539875000 # number of UpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::cpu0.data 79500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 79500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 20013735944 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 21618082257 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 41631818201 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 170354500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 177467000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 3182312556 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 31060848202 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 186335000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 177844750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 3318730008 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 33696579278 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 71970471294 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 170354500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 177467000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 3182312556 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 31060848202 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 186335000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 177844750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 3318730008 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 33696579278 # number of overall miss cycles -system.l2c.overall_miss_latency::total 71970471294 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 248464 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 168357 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 7004074 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 3411096 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 245476 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 167266 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 6973407 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 3411763 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 21629903 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 7866652 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 7866652 # number of Writeback accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu0.data 617788 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu1.data 615381 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::total 1233169 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 22791 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 22584 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 45375 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 30500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 110000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 19543422000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 19220420500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 38763842500 # number of ReadExReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu0.inst 3621036000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu1.inst 3060803500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 6681839500 # number of ReadCleanReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 11298249500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 11397176000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 22695425500 # number of ReadSharedReq miss cycles +system.l2c.InvalidateReq_miss_latency::cpu0.data 19886204500 # number of InvalidateReq miss cycles +system.l2c.InvalidateReq_miss_latency::cpu1.data 20428221500 # number of InvalidateReq miss cycles +system.l2c.InvalidateReq_miss_latency::total 40314426000 # number of InvalidateReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 179866500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 180146000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 3621036000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 30841671500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 162156000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 158214500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 3060803500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 30617596500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 68821490500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 179866500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 180146000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 3621036000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 30841671500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 162156000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 158214500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 3060803500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 30617596500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 68821490500 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 240424 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 164930 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 234813 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 164882 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 805049 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 7725236 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 7725236 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 22649 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 22018 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 44667 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu0.data 1 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 1 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 1068961 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 1071625 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 2140586 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 248464 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 168357 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 7004074 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 4480057 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 245476 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 167266 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 6973407 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 4483388 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 23770489 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 248464 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 168357 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 7004074 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 4480057 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 245476 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 167266 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 6973407 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 4483388 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 23770489 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.007993 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.012004 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.005522 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.038966 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.008832 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.012166 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.005802 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.042238 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.016846 # miss rate for ReadReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.416764 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.406925 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::total 0.411854 # miss rate for WriteInvalidateReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.785178 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.780287 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.782744 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_accesses::cpu0.data 1049069 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 1053788 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 2102857 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 6930034 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 6937378 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 13867412 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 3326011 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 3380792 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 6706803 # number of ReadSharedReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::cpu0.data 612829 # number of InvalidateReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::cpu1.data 615985 # number of InvalidateReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::total 1228814 # number of InvalidateReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 240424 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 164930 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 6930034 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 4375080 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 234813 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 164882 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 6937378 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 4434580 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 23482121 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 240424 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 164930 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 6930034 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 4375080 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 234813 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 164882 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 6937378 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 4434580 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 23482121 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.008714 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.012363 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.007913 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.011087 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.009714 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.781889 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.781951 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.781920 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.231584 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.248366 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.239985 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.007993 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.012004 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.005522 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.084925 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.008832 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.012166 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.005802 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.091507 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.036940 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.007993 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.012004 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.005522 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.084925 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.008832 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.012166 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.005802 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.091507 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.036940 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 85777.693857 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 87811.479466 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 82274.943923 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 83112.861846 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 85947.878229 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 87392.997543 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 82024.963124 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 83816.171463 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 83262.626740 # average ReadReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data 0.481590 # average WriteInvalidateReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::total 0.244141 # average WriteInvalidateReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 15461.195194 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 15482.335149 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 15471.683926 # average UpgradeReq miss latency +system.l2c.ReadExReq_miss_rate::cpu0.data 0.231313 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.226518 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.228910 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.006403 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.005426 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.005914 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.040908 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.040593 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.040750 # miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_miss_rate::cpu0.data 0.410529 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::cpu1.data 0.419151 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::total 0.414851 # miss rate for InvalidateReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.008714 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.012363 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.006403 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.086564 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.007913 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.011087 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.005426 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.084774 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.035963 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.008714 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.012363 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.006403 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.086564 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.007913 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.011087 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.005426 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.084774 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.035963 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 85855.131265 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 88350.171653 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 87274.488698 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 86550.601751 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 87005.498721 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 15630.385680 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 15280.042981 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 15457.681956 # average UpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 79500 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 79500 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 80845.940457 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81223.656354 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 81041.636804 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 85777.693857 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 87811.479466 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 82274.943923 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 81637.886204 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 85947.878229 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 87392.997543 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 82024.963124 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 82134.292910 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 81963.269141 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 85777.693857 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 87811.479466 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 82274.943923 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 81637.886204 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 85947.878229 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 87392.997543 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 82024.963124 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 82134.292910 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 81963.269141 # average overall miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 30500 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 55000 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 80537.296580 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 80520.567486 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 80529.000862 # average ReadExReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 81604.489216 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 81315.679711 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 81471.937718 # average ReadCleanReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 83037.508636 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 83047.399754 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 83042.475457 # average ReadSharedReq miss latency +system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 79043.995246 # average InvalidateReq miss latency +system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 79120.579339 # average InvalidateReq miss latency +system.l2c.InvalidateReq_avg_miss_latency::total 79082.783581 # average InvalidateReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 85855.131265 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 88350.171653 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 81604.489216 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 81435.531058 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 87274.488698 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 86550.601751 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 81315.679711 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 81442.990751 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 81493.965054 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 85855.131265 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 88350.171653 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 81604.489216 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 81435.531058 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 87274.488698 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 86550.601751 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 81315.679711 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 81442.990751 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 81493.965054 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1807,255 +1813,269 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 1109675 # number of writebacks -system.l2c.writebacks::total 1109675 # number of writebacks -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1986 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2021 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 38679 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 132917 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 2168 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 2035 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 40460 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 144107 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 364373 # number of ReadReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::cpu0.data 257472 # number of WriteInvalidateReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data 250414 # number of WriteInvalidateReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::total 507886 # number of WriteInvalidateReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 17895 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 17622 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 35517 # number of UpgradeReq MSHR misses +system.l2c.writebacks::writebacks 1074796 # number of writebacks +system.l2c.writebacks::total 1074796 # number of writebacks +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 2095 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2039 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1858 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1828 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 7820 # number of ReadReq MSHR misses +system.l2c.CleanEvict_mshr_misses::writebacks 1119 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 1119 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 17709 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 17217 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 34926 # number of UpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 1 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 247554 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 266155 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 513709 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 1986 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 2021 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 38679 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 380471 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 2168 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 2035 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 40460 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 410262 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 878082 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 1986 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 2021 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 38679 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 380471 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 2168 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 2035 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 40460 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 410262 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 878082 # number of overall MSHR misses -system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 25928 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 17713 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 17197 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 15993 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 76831 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 16112 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 17598 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 33710 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 25928 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 33825 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 17197 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 33591 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 110541 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 145388500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 152020000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 2697284444 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 9381927242 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 159094500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 152239750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 2811418492 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 10272794479 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 25772167407 # number of ReadReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data 8111001504 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 7888588001 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::total 15999589505 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 313790893 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 308995621 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 622786514 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 67500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 67500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 135000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 16917537056 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 18290027743 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 35207564799 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 145388500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 152020000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 2697284444 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 26299464298 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 159094500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 152239750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 2811418492 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 28562822222 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 60979732206 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 145388500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 152020000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 2697284444 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 26299464298 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 159094500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 152239750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 2811418492 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 28562822222 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 60979732206 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1552554500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2745071250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 1033159250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2534045000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 7864830000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2622187500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2557908500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 5180096000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1552554500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5367258750 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 1033159250 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5091953500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 13044926000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.007993 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.012004 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.005522 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.038966 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.008832 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.012166 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.005802 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.042238 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.016846 # mshr miss rate for ReadReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.416764 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.406925 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.411854 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.785178 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.780287 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.782744 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_misses::cpu0.data 242663 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 238702 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 481365 # number of ReadExReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 44373 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 37641 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::total 82014 # number of ReadCleanReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 136062 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 137237 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 273299 # number of ReadSharedReq MSHR misses +system.l2c.InvalidateReq_mshr_misses::cpu0.data 251584 # number of InvalidateReq MSHR misses +system.l2c.InvalidateReq_mshr_misses::cpu1.data 258191 # number of InvalidateReq MSHR misses +system.l2c.InvalidateReq_mshr_misses::total 509775 # number of InvalidateReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 2095 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 2039 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 44373 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 378725 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 1858 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 1828 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 37641 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 375939 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 844498 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 2095 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 2039 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 44373 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 378725 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 1858 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 1828 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 37641 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 375939 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 844498 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 26185 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 17286 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 16940 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 16418 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 76829 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 16057 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 17652 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 33709 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 26185 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 33343 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 16940 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 34070 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 110538 # number of overall MSHR uncacheable misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 158916500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 159756000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 143576000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 139934500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 602183000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 365788000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 355619500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 721407500 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 69500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 20500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 90000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 17116792000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 16833400500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 33950192500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 3177306000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 2684393500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 5861699500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 9937629500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 10024806000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 19962435500 # number of ReadSharedReq MSHR miss cycles +system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 17370364500 # number of InvalidateReq MSHR miss cycles +system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 17846311500 # number of InvalidateReq MSHR miss cycles +system.l2c.InvalidateReq_mshr_miss_latency::total 35216676000 # number of InvalidateReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 158916500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 159756000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 3177306000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 27054421500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 143576000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 139934500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 2684393500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 26858206500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 60376510500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 158916500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 159756000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 3177306000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 27054421500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 143576000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 139934500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 2684393500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 26858206500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 60376510500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1631918500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2761184000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 1058142000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2648695500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 8099940000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2682292500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2625286500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 5307579000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1631918500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5443476500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 1058142000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5273982000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 13407519000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.008714 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.012363 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.007913 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.011087 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.009714 # mshr miss rate for ReadReq accesses +system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.781889 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.781951 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.781920 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.231584 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.248366 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.239985 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.007993 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.012004 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.005522 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.084925 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.008832 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.012166 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005802 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.091507 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.036940 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.007993 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.012004 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.005522 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.084925 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.008832 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.012166 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005802 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.091507 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.036940 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 73206.696878 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 75220.188026 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 69735.113214 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 70584.855526 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 73383.071956 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 74810.687961 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69486.369056 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 71285.881179 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 70730.178710 # average ReadReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 31502.460477 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 31502.184387 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 31502.324350 # average WriteInvalidateReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17535.115563 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17534.651061 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17534.885097 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 67500 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 67500 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 67500 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 68338.774797 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 68719.459499 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 68536.009295 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 73206.696878 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 75220.188026 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69735.113214 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 69123.439889 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 73383.071956 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 74810.687961 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69486.369056 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69620.930581 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 69446.512064 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 73206.696878 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 75220.188026 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69735.113214 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 69123.439889 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 73383.071956 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 74810.687961 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69486.369056 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69620.930581 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 69446.512064 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 59879.454644 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 154974.947778 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60077.876955 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 158447.133121 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 102365.321290 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162747.486346 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 145352.227526 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 153666.449125 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 59879.454644 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 158677.272727 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60077.876955 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 151586.838737 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 118009.842502 # average overall mshr uncacheable latency +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.231313 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.226518 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.228910 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.006403 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.005426 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.005914 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.040908 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.040593 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.040750 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.410529 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.419151 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.414851 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.008714 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.012363 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.006403 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.086564 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.007913 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.011087 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005426 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.084774 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.035963 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.008714 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.012363 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.006403 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.086564 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.007913 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.011087 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005426 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.084774 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.035963 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 75855.131265 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 78350.171653 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 77274.488698 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76550.601751 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 77005.498721 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20655.485911 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20655.137364 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20655.314093 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 69500 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20500 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 45000 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 70537.296580 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 70520.567486 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 70529.000862 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 71604.489216 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 71315.679711 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 71471.937718 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 73037.508636 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 73047.399754 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 73042.475457 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 69043.995246 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69120.579339 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 69082.783581 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 75855.131265 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78350.171653 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71604.489216 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 71435.531058 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 77274.488698 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76550.601751 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71315.679711 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71442.990751 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 71493.965054 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 75855.131265 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78350.171653 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71604.489216 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 71435.531058 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77274.488698 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76550.601751 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71315.679711 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71442.990751 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 71493.965054 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62322.646553 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 159735.277103 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 62464.108619 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 161328.755025 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 105428.158638 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 167048.172137 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 148724.592114 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 157452.876087 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62322.646553 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 163256.950484 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 62464.108619 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 154798.415028 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 121293.301851 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 450083 # Transaction distribution -system.membus.trans_dist::ReadResp 450083 # Transaction distribution -system.membus.trans_dist::WriteReq 33710 # Transaction distribution -system.membus.trans_dist::WriteResp 33710 # Transaction distribution -system.membus.trans_dist::Writeback 1216305 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 614546 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 614546 # Transaction distribution -system.membus.trans_dist::UpgradeReq 36081 # Transaction distribution +system.membus.trans_dist::ReadReq 76829 # Transaction distribution +system.membus.trans_dist::ReadResp 448840 # Transaction distribution +system.membus.trans_dist::WriteReq 33709 # Transaction distribution +system.membus.trans_dist::WriteResp 33709 # Transaction distribution +system.membus.trans_dist::Writeback 1181427 # Transaction distribution +system.membus.trans_dist::CleanEvict 191531 # Transaction distribution +system.membus.trans_dist::UpgradeReq 35493 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 36083 # Transaction distribution -system.membus.trans_dist::ReadExReq 513152 # Transaction distribution -system.membus.trans_dist::ReadExResp 513152 # Transaction distribution +system.membus.trans_dist::UpgradeResp 35495 # Transaction distribution +system.membus.trans_dist::ReadExReq 990576 # Transaction distribution +system.membus.trans_dist::ReadExResp 990576 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 372011 # Transaction distribution +system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution +system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6942 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4043368 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4173072 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335046 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 335046 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4508118 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6936 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4129743 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4259441 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 340465 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 340465 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4599906 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13884 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 159836512 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 160006362 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14048000 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14048000 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 174054362 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3335 # Total snoops (count) -system.membus.snoop_fanout::samples 2864020 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13872 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 155575648 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 155745486 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7203136 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7203136 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 162948622 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3620 # Total snoops (count) +system.membus.snoop_fanout::samples 2991422 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2864020 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2991422 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2864020 # Request fanout histogram -system.membus.reqLayer0.occupancy 107121000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2991422 # Request fanout histogram +system.membus.reqLayer0.occupancy 107341500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5172000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5250000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 10421674858 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 7710006309 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 5445003775 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 7440287022 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 151621202 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 228944719 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -2099,51 +2119,54 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 18 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 22091229 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 22083154 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 33710 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 33710 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 7866652 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 1339933 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 1233169 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 45378 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 1264904 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 21840032 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 33709 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 33709 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 8906693 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 16372534 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 44670 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 45380 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2140586 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2140586 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 28041212 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 28486273 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 793018 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1241724 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 58562227 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 894731284 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1156290950 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2684984 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 3951520 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 2057658738 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 492069 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 33517490 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.039407 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.194561 # Request fanout histogram +system.toL2Bus.trans_dist::UpgradeResp 44672 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2102857 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2102857 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 13867412 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 6715681 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 1335478 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 1228814 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 41686402 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 30339787 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 785213 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1207911 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 74019313 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 887686868 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1058482234 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2638496 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 3801896 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 1952609494 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1875627 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 50645688 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.052912 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.223858 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 32196665 96.06% 96.06% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 1320825 3.94% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 47965928 94.71% 94.71% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 2679760 5.29% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 33517490 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 25817690750 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 1207500 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 50645688 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 32319092000 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 1371000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 21033645158 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 20844243000 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 14294630789 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 13901838902 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 457872249 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 455401000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 748277250 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 732674000 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index ebffe6201..6393b5a08 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,132 +1,132 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.122213 # Number of seconds simulated -sim_ticks 5122212682000 # Number of ticks simulated -final_tick 5122212682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.130109 # Number of seconds simulated +sim_ticks 5130108675000 # Number of ticks simulated +final_tick 5130108675000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 178126 # Simulator instruction rate (inst/s) -host_op_rate 352092 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2236626113 # Simulator tick rate (ticks/s) -host_mem_usage 810964 # Number of bytes of host memory used -host_seconds 2290.15 # Real time elapsed on the host -sim_insts 407934867 # Number of instructions simulated -sim_ops 806343968 # Number of ops (including micro ops) simulated +host_inst_rate 175723 # Simulator instruction rate (inst/s) +host_op_rate 347336 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2210269457 # Simulator tick rate (ticks/s) +host_mem_usage 810456 # Number of bytes of host memory used +host_seconds 2321.03 # Real time elapsed on the host +sim_insts 407858109 # Number of instructions simulated +sim_ops 806179275 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 4224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1047104 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10801152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 4288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1044544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10779584 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 11881280 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1047104 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1047104 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9569088 # Number of bytes written to this memory -system.physmem.bytes_written::total 9569088 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 66 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16361 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 168768 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 11857088 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1044544 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1044544 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9583168 # Number of bytes written to this memory +system.physmem.bytes_written::total 9583168 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 67 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16321 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 168431 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 185645 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 149517 # Number of write requests responded to by this memory -system.physmem.num_writes::total 149517 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 825 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 204424 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2108689 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::pc.south_bridge.ide 5535 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2319560 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 204424 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 204424 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1868155 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1868155 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1868155 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 825 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 204424 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2108689 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 5535 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4187715 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 185645 # Number of read requests accepted -system.physmem.writeReqs 196237 # Number of write requests accepted -system.physmem.readBursts 185645 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 196237 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11872960 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8320 # Total number of bytes read from write queue -system.physmem.bytesWritten 10880320 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11881280 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 12559168 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 130 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 26214 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 1708 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11253 # Per bank write bursts -system.physmem.perBankRdBursts::1 10547 # Per bank write bursts -system.physmem.perBankRdBursts::2 11972 # Per bank write bursts -system.physmem.perBankRdBursts::3 11655 # Per bank write bursts -system.physmem.perBankRdBursts::4 11971 # Per bank write bursts -system.physmem.perBankRdBursts::5 11254 # Per bank write bursts -system.physmem.perBankRdBursts::6 11364 # Per bank write bursts -system.physmem.perBankRdBursts::7 11315 # Per bank write bursts -system.physmem.perBankRdBursts::8 11445 # Per bank write bursts -system.physmem.perBankRdBursts::9 11672 # Per bank write bursts -system.physmem.perBankRdBursts::10 11062 # Per bank write bursts -system.physmem.perBankRdBursts::11 11423 # Per bank write bursts -system.physmem.perBankRdBursts::12 12308 # Per bank write bursts -system.physmem.perBankRdBursts::13 12737 # Per bank write bursts -system.physmem.perBankRdBursts::14 11748 # Per bank write bursts -system.physmem.perBankRdBursts::15 11789 # Per bank write bursts -system.physmem.perBankWrBursts::0 11864 # Per bank write bursts -system.physmem.perBankWrBursts::1 10686 # Per bank write bursts -system.physmem.perBankWrBursts::2 10651 # Per bank write bursts -system.physmem.perBankWrBursts::3 9860 # Per bank write bursts -system.physmem.perBankWrBursts::4 10294 # Per bank write bursts -system.physmem.perBankWrBursts::5 10368 # Per bank write bursts -system.physmem.perBankWrBursts::6 9733 # Per bank write bursts -system.physmem.perBankWrBursts::7 9712 # Per bank write bursts -system.physmem.perBankWrBursts::8 9632 # Per bank write bursts -system.physmem.perBankWrBursts::9 10471 # Per bank write bursts -system.physmem.perBankWrBursts::10 10725 # Per bank write bursts -system.physmem.perBankWrBursts::11 10392 # Per bank write bursts -system.physmem.perBankWrBursts::12 11457 # Per bank write bursts -system.physmem.perBankWrBursts::13 11384 # Per bank write bursts -system.physmem.perBankWrBursts::14 11667 # Per bank write bursts -system.physmem.perBankWrBursts::15 11109 # Per bank write bursts +system.physmem.num_reads::total 185267 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 149737 # Number of write requests responded to by this memory +system.physmem.num_writes::total 149737 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 836 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 203611 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2101239 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5527 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2311274 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 203611 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 203611 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1868024 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1868024 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1868024 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 836 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 203611 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2101239 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 5527 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4179299 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 185267 # Number of read requests accepted +system.physmem.writeReqs 149737 # Number of write requests accepted +system.physmem.readBursts 185267 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 149737 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11846656 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 10432 # Total number of bytes read from write queue +system.physmem.bytesWritten 9581440 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11857088 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9583168 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 163 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 48775 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11590 # Per bank write bursts +system.physmem.perBankRdBursts::1 11256 # Per bank write bursts +system.physmem.perBankRdBursts::2 12288 # Per bank write bursts +system.physmem.perBankRdBursts::3 11911 # Per bank write bursts +system.physmem.perBankRdBursts::4 11840 # Per bank write bursts +system.physmem.perBankRdBursts::5 11665 # Per bank write bursts +system.physmem.perBankRdBursts::6 10867 # Per bank write bursts +system.physmem.perBankRdBursts::7 10808 # Per bank write bursts +system.physmem.perBankRdBursts::8 11222 # Per bank write bursts +system.physmem.perBankRdBursts::9 11056 # Per bank write bursts +system.physmem.perBankRdBursts::10 11302 # Per bank write bursts +system.physmem.perBankRdBursts::11 11775 # Per bank write bursts +system.physmem.perBankRdBursts::12 11547 # Per bank write bursts +system.physmem.perBankRdBursts::13 12196 # Per bank write bursts +system.physmem.perBankRdBursts::14 11932 # Per bank write bursts +system.physmem.perBankRdBursts::15 11849 # Per bank write bursts +system.physmem.perBankWrBursts::0 10246 # Per bank write bursts +system.physmem.perBankWrBursts::1 9545 # Per bank write bursts +system.physmem.perBankWrBursts::2 9025 # Per bank write bursts +system.physmem.perBankWrBursts::3 8913 # Per bank write bursts +system.physmem.perBankWrBursts::4 9024 # Per bank write bursts +system.physmem.perBankWrBursts::5 9097 # Per bank write bursts +system.physmem.perBankWrBursts::6 8779 # Per bank write bursts +system.physmem.perBankWrBursts::7 8697 # Per bank write bursts +system.physmem.perBankWrBursts::8 8886 # Per bank write bursts +system.physmem.perBankWrBursts::9 9043 # Per bank write bursts +system.physmem.perBankWrBursts::10 9545 # Per bank write bursts +system.physmem.perBankWrBursts::11 9380 # Per bank write bursts +system.physmem.perBankWrBursts::12 9802 # Per bank write bursts +system.physmem.perBankWrBursts::13 9849 # Per bank write bursts +system.physmem.perBankWrBursts::14 10052 # Per bank write bursts +system.physmem.perBankWrBursts::15 9827 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 85 # Number of times write queue was full causing retry -system.physmem.totGap 5122212630000 # Total gap between requests +system.physmem.numWrRetry 4 # Number of times write queue was full causing retry +system.physmem.totGap 5130108625500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 185645 # Read request sizes (log2) +system.physmem.readPktSize::6 185267 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 196237 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 171240 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 11542 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1948 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 451 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see +system.physmem.writePktSize::6 149737 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 170610 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 11668 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2033 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 465 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 56 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 36 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 30 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -156,302 +156,301 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1627 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1832 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6256 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7099 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7342 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7542 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8781 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7845 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9622 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10480 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7914 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2725 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2849 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2539 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 2444 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 3285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2479 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2385 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 2208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 2459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 2080 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1599 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 975 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 483 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 399 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 342 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 363 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 200 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 73901 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 307.887796 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 180.352303 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.737558 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 28243 38.22% 38.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17330 23.45% 61.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7468 10.11% 71.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4217 5.71% 77.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3016 4.08% 81.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1973 2.67% 84.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1390 1.88% 86.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1267 1.71% 87.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8997 12.17% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 73901 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6788 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.329258 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 584.024068 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6787 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2978 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 7943 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7753 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7793 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 9624 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9979 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 11771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9975 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8508 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7621 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 257 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 9 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 72239 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 296.626919 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 176.108811 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 319.147383 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 27668 38.30% 38.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17613 24.38% 62.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7498 10.38% 73.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4242 5.87% 78.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2823 3.91% 82.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1928 2.67% 85.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1515 2.10% 87.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1131 1.57% 89.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7821 10.83% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 72239 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7351 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.179159 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 561.374907 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7350 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6788 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6788 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 25.044932 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.591825 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 43.260290 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 6382 94.02% 94.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 87 1.28% 95.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 9 0.13% 95.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 9 0.13% 95.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 22 0.32% 95.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 15 0.22% 96.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 29 0.43% 96.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 26 0.38% 96.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 35 0.52% 97.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 9 0.13% 97.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 41 0.60% 98.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 54 0.80% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 7 0.10% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 6 0.09% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 1 0.01% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 4 0.06% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 2 0.03% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 4 0.06% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 3 0.04% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 5 0.07% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 19 0.28% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 6 0.09% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 1 0.01% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::400-415 1 0.01% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::464-479 1 0.01% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 1 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 3 0.04% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::560-575 4 0.06% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6788 # Writes before turning the bus around for reads -system.physmem.totQLat 2015945224 # Total ticks spent queuing -system.physmem.totMemAccLat 5494351474 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 927575000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10866.75 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 7351 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7351 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.365937 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.603384 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.112022 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 6287 85.53% 85.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 96 1.31% 86.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 185 2.52% 89.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 82 1.12% 90.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 111 1.51% 91.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 202 2.75% 94.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 31 0.42% 95.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 14 0.19% 95.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 14 0.19% 95.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 10 0.14% 95.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 9 0.12% 95.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 5 0.07% 95.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 246 3.35% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 8 0.11% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.05% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 8 0.11% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 2 0.03% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.01% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 7 0.10% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.01% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.03% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.03% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 14 0.19% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.03% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 3 0.04% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7351 # Writes before turning the bus around for reads +system.physmem.totQLat 1992019456 # Total ticks spent queuing +system.physmem.totMemAccLat 5462719456 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 925520000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10761.62 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29616.75 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.32 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.12 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.32 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.45 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29511.62 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.31 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.87 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.31 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.87 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.03 # Average write queue length when enqueuing -system.physmem.readRowHits 152167 # Number of row buffer hits during reads -system.physmem.writeRowHits 129451 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.02 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 76.14 # Row buffer hit rate for writes -system.physmem.avgGap 13413076.89 # Average gap between requests -system.physmem.pageHitRate 79.21 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 269256960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 146916000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 712374000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 538928640 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 334557721680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 129214187775 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2959979121750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 3425418506805 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.738637 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 4924130039468 # Time in different power states -system.physmem_0.memoryStateTime::REF 171041780000 # Time in different power states +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.79 # Average write queue length when enqueuing +system.physmem.readRowHits 151846 # Number of row buffer hits during reads +system.physmem.writeRowHits 110728 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.03 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.95 # Row buffer hit rate for writes +system.physmem.avgGap 15313574.24 # Average gap between requests +system.physmem.pageHitRate 78.42 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 269393040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 146990250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 719355000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 475152480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 335073401520 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 129448929735 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2964510370500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 3430643592525 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.727957 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 4931666056220 # Time in different power states +system.physmem_0.memoryStateTime::REF 171305420000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 27040752032 # Time in different power states +system.physmem_0.memoryStateTime::ACT 27131976280 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 289434600 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 157925625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 734635200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 562703760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 334557721680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 129751534755 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2959507764750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 3425561720370 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.766596 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 4923333713433 # Time in different power states -system.physmem_1.memoryStateTime::REF 171041780000 # Time in different power states +system.physmem_1.actEnergy 276733800 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 150995625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 724448400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 494968320 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 335073401520 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 129698055360 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2964291831000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 3430710434025 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.740988 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 4931307220986 # Time in different power states +system.physmem_1.memoryStateTime::REF 171305420000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 27832687817 # Time in different power states +system.physmem_1.memoryStateTime::ACT 27495924014 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 86818912 # Number of BP lookups -system.cpu.branchPred.condPredicted 86818912 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 895085 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 80098723 # Number of BTB lookups -system.cpu.branchPred.BTBHits 78142837 # Number of BTB hits +system.cpu.branchPred.lookups 86802866 # Number of BP lookups +system.cpu.branchPred.condPredicted 86802866 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 898884 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 79915985 # Number of BTB lookups +system.cpu.branchPred.BTBHits 78142205 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.558156 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1551403 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 180089 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.780444 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1557172 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 181109 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 449999443 # number of cpu cycles simulated +system.cpu.numCycles 449354840 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 27536923 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 428761982 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86818912 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79694240 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 418469892 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1877186 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 142405 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 58257 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 203994 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 110 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 541 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9116293 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 453128 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4723 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 447350715 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.891249 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.050769 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27419696 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 428691862 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86802866 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79699377 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 417944649 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1884104 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 141232 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 57475 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 210217 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 60 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 747 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9135683 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 451645 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5364 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 446716128 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.893620 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.051973 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 282061925 63.05% 63.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2147503 0.48% 63.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72168287 16.13% 79.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1568006 0.35% 80.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2127596 0.48% 80.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2318806 0.52% 81.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1512611 0.34% 81.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1884650 0.42% 81.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 81561331 18.23% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 281460190 63.01% 63.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2138894 0.48% 63.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72152839 16.15% 79.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1576063 0.35% 79.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2129707 0.48% 80.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2325949 0.52% 80.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1505469 0.34% 81.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1859854 0.42% 81.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 81567163 18.26% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 447350715 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.192931 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.952806 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 22908567 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 265367852 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 150702709 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 7432994 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 938593 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 837990299 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 938593 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 25758226 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 223276953 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 12890661 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 154592541 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 29893741 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 834466404 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 451836 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 12178537 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 145180 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 14794285 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 996780528 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1812316725 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1114082490 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 470 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 964296204 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 32484322 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 461178 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 464876 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 38644871 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17242919 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10123129 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1280249 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1072002 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 828945592 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1192163 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 823760090 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 244912 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 23793782 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 35793426 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 146866 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 447350715 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.841419 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.417821 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 446716128 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.193172 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.954016 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 22817532 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 264818622 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 150719822 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 7418100 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 942052 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 837890793 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 942052 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 25656597 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 222831809 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 12884327 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 154608390 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 29792953 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 834381209 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 449377 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 12218260 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 146025 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 14738284 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 996692347 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1812155414 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1113986633 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 357 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 964101925 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 32590420 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 461964 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 466029 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 38550499 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17267645 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10120270 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1295034 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1078818 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 828854264 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1188467 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 823634023 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 239226 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 23863451 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 35922872 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 148640 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 446716128 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.843753 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.418621 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 263279849 58.85% 58.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13891965 3.11% 61.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 9851915 2.20% 64.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7048956 1.58% 65.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 74303394 16.61% 82.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4391366 0.98% 83.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72807233 16.28% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1204673 0.27% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 571364 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 262749029 58.82% 58.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13824325 3.09% 61.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 9784338 2.19% 64.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7058515 1.58% 65.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 74344613 16.64% 82.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4389971 0.98% 83.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72797188 16.30% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1191150 0.27% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 576999 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 447350715 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 446716128 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1986394 72.18% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 608344 22.10% 94.28% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 157420 5.72% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1965794 71.96% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 607707 22.24% 94.20% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 158405 5.80% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 285236 0.03% 0.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 795541833 96.57% 96.61% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 150365 0.02% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 127447 0.02% 96.64% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 286388 0.03% 0.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 795396124 96.57% 96.61% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 150331 0.02% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 127202 0.02% 96.64% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.64% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 108 0.00% 96.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 98 0.00% 96.64% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.64% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.64% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.64% # Type of FU issued @@ -475,98 +474,98 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.64% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.64% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.64% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 18320687 2.22% 98.87% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9334414 1.13% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 18333764 2.23% 98.87% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9340116 1.13% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 823760090 # Type of FU issued -system.cpu.iq.rate 1.830580 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2752158 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.003341 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2097867450 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 853943468 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 819213197 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 514 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 630 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 182 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 826226763 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 249 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1860072 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 823634023 # Type of FU issued +system.cpu.iq.rate 1.832926 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2731906 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.003317 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2096954851 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 853918294 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 819080568 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 454 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 494 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 158 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 826079323 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 218 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1864091 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3252614 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14803 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 3276332 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 15288 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 14318 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1702580 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 1695886 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2208153 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 72229 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2207587 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 71306 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 938593 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 204923881 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 10223668 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 830137755 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 158534 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17242919 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10123129 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 698460 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 397050 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 8973453 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 942052 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 204779875 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 9950427 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 830042731 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 154301 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17267645 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10120270 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 698404 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 395340 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 8703386 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 14318 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 514177 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 531213 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1045390 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 822137992 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17928402 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1491599 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 517416 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 531852 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1049268 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 822011733 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17933627 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1492341 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 27038601 # number of memory reference insts executed -system.cpu.iew.exec_branches 83256358 # Number of branches executed -system.cpu.iew.exec_stores 9110199 # Number of stores executed -system.cpu.iew.exec_rate 1.826976 # Inst execution rate -system.cpu.iew.wb_sent 821634339 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 819213379 # cumulative count of insts written-back -system.cpu.iew.wb_producers 640695638 # num instructions producing a value -system.cpu.iew.wb_consumers 1049922326 # num instructions consuming a value +system.cpu.iew.exec_refs 27049256 # number of memory reference insts executed +system.cpu.iew.exec_branches 83240327 # Number of branches executed +system.cpu.iew.exec_stores 9115629 # Number of stores executed +system.cpu.iew.exec_rate 1.829315 # Inst execution rate +system.cpu.iew.wb_sent 821506514 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 819080726 # cumulative count of insts written-back +system.cpu.iew.wb_producers 640638640 # num instructions producing a value +system.cpu.iew.wb_consumers 1049832937 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.820476 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.610231 # average fanout of values written-back +system.cpu.iew.wb_rate 1.822793 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.610229 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 23667492 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1045297 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 906773 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 443789392 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.816952 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.674122 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 23734474 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1039827 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 910229 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 443141458 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.819237 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.674506 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 272960111 61.51% 61.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11180384 2.52% 64.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3592831 0.81% 64.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74586039 16.81% 81.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2426818 0.55% 82.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1631046 0.37% 82.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 941888 0.21% 82.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 71056225 16.01% 98.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5414050 1.22% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 272292366 61.45% 61.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11181272 2.52% 63.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3605802 0.81% 64.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74611152 16.84% 81.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2465682 0.56% 82.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1626284 0.37% 82.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 958421 0.22% 82.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70995563 16.02% 98.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5404916 1.22% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 443789392 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407934867 # Number of instructions committed -system.cpu.commit.committedOps 806343968 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 443141458 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407858109 # Number of instructions committed +system.cpu.commit.committedOps 806179275 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22410853 # Number of memory references committed -system.cpu.commit.loads 13990304 # Number of loads committed -system.cpu.commit.membars 471837 # Number of memory barriers committed -system.cpu.commit.branches 82192569 # Number of branches committed +system.cpu.commit.refs 22415696 # Number of memory references committed +system.cpu.commit.loads 13991312 # Number of loads committed +system.cpu.commit.membars 468143 # Number of memory barriers committed +system.cpu.commit.branches 82176077 # Number of branches committed system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu.commit.int_insts 735158454 # Number of committed integer instructions. -system.cpu.commit.function_calls 1155650 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 171552 0.02% 0.02% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 783497766 97.17% 97.19% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 144918 0.02% 97.21% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 121442 0.02% 97.22% # Class of committed instruction +system.cpu.commit.int_insts 735014201 # Number of committed integer instructions. +system.cpu.commit.function_calls 1155537 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 171593 0.02% 0.02% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 783328307 97.17% 97.19% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 144946 0.02% 97.20% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 121298 0.02% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 16 0.00% 97.22% # Class of committed instruction @@ -593,231 +592,231 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 13987725 1.73% 98.96% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 8420549 1.04% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 13988731 1.74% 98.96% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 8424384 1.04% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 806343968 # Class of committed instruction -system.cpu.commit.bw_lim_events 5414050 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1268308634 # The number of ROB reads -system.cpu.rob.rob_writes 1663603607 # The number of ROB writes -system.cpu.timesIdled 289860 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 2648728 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9794423343 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407934867 # Number of Instructions Simulated -system.cpu.committedOps 806343968 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.103116 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.103116 # CPI: Total CPI of All Threads -system.cpu.ipc 0.906523 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.906523 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1091825743 # number of integer regfile reads -system.cpu.int_regfile_writes 655727641 # number of integer regfile writes -system.cpu.fp_regfile_reads 182 # number of floating regfile reads -system.cpu.cc_regfile_reads 416065488 # number of cc regfile reads -system.cpu.cc_regfile_writes 321934300 # number of cc regfile writes -system.cpu.misc_regfile_reads 265346710 # number of misc regfile reads -system.cpu.misc_regfile_writes 399949 # number of misc regfile writes -system.cpu.dcache.tags.replacements 1659310 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.993990 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 19061899 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1659822 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.484303 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 41264250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.993990 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999988 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999988 # Average percentage of cache occupancy +system.cpu.commit.op_class_0::total 806179275 # Class of committed instruction +system.cpu.commit.bw_lim_events 5404916 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1267572015 # The number of ROB reads +system.cpu.rob.rob_writes 1663421472 # The number of ROB writes +system.cpu.timesIdled 288126 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 2638712 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9810859930 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407858109 # Number of Instructions Simulated +system.cpu.committedOps 806179275 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.101743 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.101743 # CPI: Total CPI of All Threads +system.cpu.ipc 0.907653 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.907653 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1091670765 # number of integer regfile reads +system.cpu.int_regfile_writes 655627629 # number of integer regfile writes +system.cpu.fp_regfile_reads 158 # number of floating regfile reads +system.cpu.cc_regfile_reads 416000684 # number of cc regfile reads +system.cpu.cc_regfile_writes 321879904 # number of cc regfile writes +system.cpu.misc_regfile_reads 265310647 # number of misc regfile reads +system.cpu.misc_regfile_writes 400047 # number of misc regfile writes +system.cpu.dcache.tags.replacements 1661478 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.997539 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 19061070 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1661990 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.468824 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 40620500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.997539 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999995 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 212 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 283 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 225 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 272 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88087332 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88087332 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 10917280 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10917280 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8077307 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8077307 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 64579 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 64579 # number of SoftPFReq hits -system.cpu.dcache.demand_hits::cpu.data 18994587 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18994587 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19059166 # number of overall hits -system.cpu.dcache.overall_hits::total 19059166 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1807757 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1807757 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 333541 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 333541 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 406408 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 406408 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 2141298 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2141298 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2547706 # number of overall misses -system.cpu.dcache.overall_misses::total 2547706 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 27202744445 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 27202744445 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 13955718277 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 13955718277 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 41158462722 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 41158462722 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 41158462722 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 41158462722 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 12725037 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 12725037 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8410848 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8410848 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 470987 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 470987 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21135885 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21135885 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21606872 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21606872 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.142063 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.142063 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039656 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.039656 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.862886 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.862886 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.101311 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.101311 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.117912 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.117912 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15047.788196 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15047.788196 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41841.087833 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41841.087833 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19221.267998 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19221.267998 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16155.106877 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16155.106877 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 414660 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 88124232 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88124232 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 10914055 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 10914055 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8079827 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8079827 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 64080 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 64080 # number of SoftPFReq hits +system.cpu.dcache.demand_hits::cpu.data 18993882 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18993882 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 19057962 # number of overall hits +system.cpu.dcache.overall_hits::total 19057962 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1815960 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1815960 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 334906 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 334906 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 406730 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 406730 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 2150866 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2150866 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2557596 # number of overall misses +system.cpu.dcache.overall_misses::total 2557596 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 27033028000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 27033028000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 13819339247 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 13819339247 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 40852367247 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 40852367247 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 40852367247 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 40852367247 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 12730015 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 12730015 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8414733 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8414733 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 470810 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 470810 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21144748 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21144748 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21615558 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21615558 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.142652 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.142652 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039800 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.039800 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.863894 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.863894 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.101721 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.101721 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.118322 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.118322 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14886.356528 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14886.356528 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41263.337316 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41263.337316 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 18993.450660 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 18993.450660 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15972.955559 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15972.955559 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 469124 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 43514 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 51580 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.529347 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.095076 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1560749 # number of writebacks -system.cpu.dcache.writebacks::total 1560749 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 839489 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 839489 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 42702 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 42702 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 882191 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 882191 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 882191 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 882191 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 968268 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 968268 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290839 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 290839 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402958 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 402958 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1259107 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1259107 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1662065 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1662065 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 604701 # number of ReadReq MSHR uncacheable -system.cpu.dcache.ReadReq_mshr_uncacheable::total 604701 # number of ReadReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13919 # number of WriteReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::total 13919 # number of WriteReq MSHR uncacheable -system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 618620 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 618620 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12834468768 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12834468768 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12344104823 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12344104823 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5960784250 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5960784250 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25178573591 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 25178573591 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31139357841 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 31139357841 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97454292000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97454292000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2593348000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2593348000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100047640000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 100047640000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076092 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076092 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034579 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034579 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.855561 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.855561 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059572 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.059572 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076923 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.076923 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13255.078933 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13255.078933 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42443.086460 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42443.086460 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14792.569573 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14792.569573 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19997.167509 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19997.167509 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18735.342987 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18735.342987 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 161161.122604 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 161161.122604 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 186317.120483 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 186317.120483 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 161727.134590 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 161727.134590 # average overall mshr uncacheable latency +system.cpu.dcache.writebacks::writebacks 1562865 # number of writebacks +system.cpu.dcache.writebacks::total 1562865 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 845003 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 845003 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44547 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 44547 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 889550 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 889550 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 889550 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 889550 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 970957 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 970957 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290359 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 290359 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 403239 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 403239 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1261316 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1261316 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1664555 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1664555 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 602896 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadReq_mshr_uncacheable::total 602896 # number of ReadReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13875 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 13875 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 616771 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 616771 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 13333994500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 13333994500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12420799750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12420799750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6058828500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6058828500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25754794250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 25754794250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31813622750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 31813622750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97793670000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97793670000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2615433000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2615433000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100409103000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 100409103000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076273 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076273 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034506 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034506 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.856479 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.856479 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059652 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.059652 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077007 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.077007 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13732.837294 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13732.837294 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42777.388509 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42777.388509 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15025.403049 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15025.403049 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20418.986400 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20418.986400 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19112.389047 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19112.389047 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 162206.533133 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162206.533133 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188499.675676 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188499.675676 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 162798.028766 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 162798.028766 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 77765 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 13.263782 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 104942 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 77779 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.349233 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5097981011500 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 13.263782 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.828986 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.828986 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 446439 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 446439 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 104946 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 104946 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 104946 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 104946 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 104946 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 104946 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 78849 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 78849 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 78849 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 78849 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 78849 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 78849 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 941548961 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 941548961 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 941548961 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 941548961 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 941548961 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 941548961 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 183795 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 183795 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 183795 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 183795 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 183795 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 183795 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.429005 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.429005 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.429005 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.429005 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.429005 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.429005 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 11941.165532 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 11941.165532 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 11941.165532 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 11941.165532 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 11941.165532 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 11941.165532 # average overall miss latency +system.cpu.dtb_walker_cache.tags.replacements 72618 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 14.793557 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 113213 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 72633 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.558699 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5097094340500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 14.793557 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.924597 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.924597 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id +system.cpu.dtb_walker_cache.tags.tag_accesses 447394 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 447394 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 113219 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 113219 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 113219 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 113219 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 113219 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 113219 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 73652 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 73652 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 73652 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 73652 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 73652 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 73652 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 910717000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 910717000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 910717000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 910717000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 910717000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 910717000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 186871 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 186871 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 186871 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 186871 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 186871 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 186871 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.394133 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.394133 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.394133 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.394133 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.394133 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.394133 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12365.136045 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12365.136045 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12365.136045 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12365.136045 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12365.136045 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12365.136045 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -826,180 +825,180 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 22745 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 22745 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 78849 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 78849 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 78849 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 78849 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 78849 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 78849 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 823159683 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 823159683 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 823159683 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 823159683 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 823159683 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 823159683 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.429005 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.429005 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.429005 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.429005 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.429005 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.429005 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10439.697181 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10439.697181 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10439.697181 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10439.697181 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10439.697181 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10439.697181 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 18815 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 18815 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 73652 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 73652 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 73652 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 73652 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 73652 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 73652 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 837065000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 837065000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 837065000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 837065000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 837065000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 837065000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.394133 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.394133 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.394133 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.394133 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.394133 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.394133 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11365.136045 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11365.136045 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11365.136045 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 11365.136045 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11365.136045 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 11365.136045 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 996925 # number of replacements -system.cpu.icache.tags.tagsinuse 509.357790 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 8050243 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 997437 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 8.070929 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 148006664250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.357790 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.994839 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.994839 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 991040 # number of replacements +system.cpu.icache.tags.tagsinuse 509.607437 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 8073267 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 991552 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 8.142051 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 147914027500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.607437 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.995327 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.995327 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 232 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 156 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 10113779 # Number of tag accesses -system.cpu.icache.tags.data_accesses 10113779 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 8050243 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8050243 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 8050243 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8050243 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 8050243 # number of overall hits -system.cpu.icache.overall_hits::total 8050243 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1066046 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1066046 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1066046 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1066046 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1066046 # number of overall misses -system.cpu.icache.overall_misses::total 1066046 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14875004411 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14875004411 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14875004411 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14875004411 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14875004411 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14875004411 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9116289 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9116289 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9116289 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9116289 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9116289 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9116289 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.116939 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.116939 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.116939 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.116939 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.116939 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.116939 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13953.435791 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13953.435791 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13953.435791 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13953.435791 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13953.435791 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13953.435791 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 7127 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 10127588 # Number of tag accesses +system.cpu.icache.tags.data_accesses 10127588 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 8073267 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8073267 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 8073267 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 8073267 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 8073267 # number of overall hits +system.cpu.icache.overall_hits::total 8073267 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1062411 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1062411 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1062411 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1062411 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1062411 # number of overall misses +system.cpu.icache.overall_misses::total 1062411 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14792091486 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14792091486 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14792091486 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14792091486 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14792091486 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14792091486 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9135678 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9135678 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9135678 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9135678 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9135678 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9135678 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.116293 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.116293 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.116293 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.116293 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.116293 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.116293 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13923.134725 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13923.134725 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13923.134725 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13923.134725 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13923.134725 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13923.134725 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 7978 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 341 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 382 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 20.900293 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 20.884817 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68556 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 68556 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 68556 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 68556 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 68556 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 68556 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 997490 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 997490 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 997490 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 997490 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 997490 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 997490 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12688553873 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12688553873 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12688553873 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12688553873 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12688553873 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12688553873 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.109418 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.109418 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.109418 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.109418 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.109418 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.109418 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12720.482284 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12720.482284 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12720.482284 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12720.482284 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12720.482284 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12720.482284 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 70501 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 70501 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 70501 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 70501 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 70501 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 70501 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 991910 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 991910 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 991910 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 991910 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 991910 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 991910 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13114232487 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 13114232487 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13114232487 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 13114232487 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13114232487 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 13114232487 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108575 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108575 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108575 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.108575 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108575 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.108575 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13221.191930 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13221.191930 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13221.191930 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13221.191930 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13221.191930 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13221.191930 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 13512 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 6.614352 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 26763 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 13525 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 1.978780 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5101180103500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.614352 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.413397 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.413397 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.replacements 15565 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 6.022675 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 26231 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 15578 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 1.683849 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5102115273500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.022675 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.376417 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.376417 # Average percentage of cache occupancy system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id -system.cpu.itb_walker_cache.tags.tag_accesses 96721 # Number of tag accesses -system.cpu.itb_walker_cache.tags.data_accesses 96721 # Number of data accesses -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 26775 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 26775 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.tag_accesses 101828 # Number of tag accesses +system.cpu.itb_walker_cache.tags.data_accesses 101828 # Number of data accesses +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 26240 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 26240 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 26777 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 26777 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 26777 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 26777 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 14389 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 14389 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 14389 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 14389 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 14389 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 14389 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 168738994 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 168738994 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 168738994 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 168738994 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 168738994 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 168738994 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 41164 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 41164 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 26242 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 26242 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 26242 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 26242 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 16448 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 16448 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 16448 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 16448 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 16448 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 16448 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 193358500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 193358500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 193358500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 193358500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 193358500 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 193358500 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 42688 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 42688 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 41166 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 41166 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 41166 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 41166 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.349553 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.349553 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.349536 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.349536 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.349536 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.349536 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11726.943776 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11726.943776 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11726.943776 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11726.943776 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11726.943776 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11726.943776 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 42690 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 42690 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 42690 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 42690 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.385307 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.385307 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.385289 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.385289 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.385289 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.385289 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11755.745379 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11755.745379 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11755.745379 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11755.745379 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11755.745379 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11755.745379 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1008,177 +1007,183 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 3066 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 3066 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 14389 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 14389 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 14389 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 14389 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 14389 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 14389 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 147144512 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 147144512 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 147144512 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 147144512 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 147144512 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 147144512 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.349553 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.349553 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.349536 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.349536 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.349536 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.349536 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 10226.180555 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10226.180555 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 10226.180555 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 10226.180555 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 10226.180555 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 10226.180555 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 3018 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 3018 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 16448 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 16448 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 16448 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 16448 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 16448 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 16448 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 176910500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 176910500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 176910500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 176910500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 176910500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 176910500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.385307 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.385307 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.385289 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.385289 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.385289 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.385289 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 10755.745379 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10755.745379 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 10755.745379 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 10755.745379 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 10755.745379 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 10755.745379 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 112729 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64831.922119 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3833002 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 176853 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 21.673378 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 112892 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64819.691770 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4938747 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 176773 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 27.938356 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50534.450143 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 14.577905 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 1.126849 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3105.817202 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 11175.950019 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.771095 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000222 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000017 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.047391 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.170531 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.989257 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 64124 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 694 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3262 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7383 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 52712 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978455 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 35081373 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 35081373 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 68578 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12140 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 981027 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1334830 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2396575 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1586560 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1586560 # number of Writeback hits +system.cpu.l2cache.tags.occ_blocks::writebacks 50529.309735 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 20.322898 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.136173 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3138.561208 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 11131.361756 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.771016 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000310 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.047891 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.169851 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.989070 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 63881 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 774 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3319 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5177 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54573 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.974747 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 43864381 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 43864381 # Number of data accesses +system.cpu.l2cache.Writeback_hits::writebacks 1584698 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1584698 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 310 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 310 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 154702 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 154702 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 68578 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 12140 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 981027 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1489532 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2551277 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 68578 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 12140 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 981027 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1489532 # number of overall hits -system.cpu.l2cache.overall_hits::total 2551277 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 66 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 16363 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 35684 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 52120 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1439 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1439 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 134046 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 134046 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 66 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 16363 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 169730 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 186166 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 66 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 16363 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 169730 # number of overall misses -system.cpu.l2cache.overall_misses::total 186166 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 6097000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 666500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1366410532 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3072121000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 4445295032 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 22717321 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 22717321 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10374564266 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 10374564266 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 6097000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 666500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1366410532 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 13446685266 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 14819859298 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 6097000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 666500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1366410532 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 13446685266 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 14819859298 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 68644 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12147 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 997390 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1370514 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2448695 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1586560 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1586560 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1749 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1749 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 288748 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 288748 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 68644 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 12147 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 997390 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1659262 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2737443 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 68644 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 12147 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 997390 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1659262 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2737443 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000961 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000576 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016406 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026037 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.021285 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.822756 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.822756 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.464232 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.464232 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000961 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000576 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016406 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.102292 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.068007 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000961 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000576 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016406 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.102292 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.068007 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 92378.787879 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 95214.285714 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 83506.113304 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 86092.394350 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 85289.620721 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15786.880473 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15786.880473 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77395.552765 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77395.552765 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 92378.787879 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 95214.285714 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83506.113304 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79223.974937 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 79605.617019 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 92378.787879 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 95214.285714 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83506.113304 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79223.974937 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 79605.617019 # average overall miss latency +system.cpu.l2cache.ReadExReq_hits::cpu.data 154215 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 154215 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 975190 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 975190 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 67279 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 13917 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1337816 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1419012 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 67279 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 13917 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 975190 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1492031 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2548417 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 67279 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 13917 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 975190 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1492031 # number of overall hits +system.cpu.l2cache.overall_hits::total 2548417 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 1787 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 1787 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 133737 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133737 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16323 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 16323 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker 67 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker 5 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 35675 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 35747 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 67 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 16323 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 169412 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 185807 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 67 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 16323 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 169412 # number of overall misses +system.cpu.l2cache.overall_misses::total 185807 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 23917000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 23917000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10298204500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 10298204500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1359330500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 1359330500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.dtb.walker 6177500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.itb.walker 415000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3065419500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 3072012000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 6177500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 415000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1359330500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 13363624000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 14729547000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 6177500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 415000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1359330500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 13363624000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 14729547000 # number of overall miss cycles +system.cpu.l2cache.Writeback_accesses::writebacks 1584698 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1584698 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2097 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2097 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 287952 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 287952 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 991513 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 991513 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker 67346 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker 13922 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1373491 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1454759 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 67346 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 13922 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 991513 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1661443 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2734224 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 67346 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 13922 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 991513 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1661443 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2734224 # number of overall (read+write) accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.852170 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.852170 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.464442 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.464442 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.016463 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.016463 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker 0.000995 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker 0.000359 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.025974 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024572 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000995 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000359 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016463 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.101967 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.067956 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000995 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000359 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016463 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.101967 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.067956 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 13383.883604 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 13383.883604 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77003.405939 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77003.405939 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83277.001777 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83277.001777 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.dtb.walker 92201.492537 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.itb.walker 83000 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85926.264891 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85937.617143 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 92201.492537 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 83000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83277.001777 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78882.393219 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 79273.369679 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 92201.492537 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 83000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83277.001777 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78882.393219 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 79273.369679 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1187,176 +1192,187 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 102850 # number of writebacks -system.cpu.l2cache.writebacks::total 102850 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 103070 # number of writebacks +system.cpu.l2cache.writebacks::total 103070 # number of writebacks +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 4 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 4 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 3 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 66 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16361 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35683 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 52117 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1439 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 1439 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 134046 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 134046 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 66 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 16361 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 169729 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 186163 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 66 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 16361 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 169729 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 186163 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 604701 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.ReadReq_mshr_uncacheable::total 604701 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 13919 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::total 13919 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 618620 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::total 618620 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5264500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 578000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1161518218 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2626180250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3793540968 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 26446420 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 26446420 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8698623734 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8698623734 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5264500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 578000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1161518218 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11324803984 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 12492164702 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5264500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 578000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1161518218 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11324803984 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 12492164702 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 88988446000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 88988446000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2411352000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2411352000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91399798000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91399798000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000961 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000576 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016404 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026036 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021284 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.822756 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.822756 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.464232 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.464232 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000961 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000576 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016404 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102292 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.068006 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000961 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000576 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016404 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102292 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.068006 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 79765.151515 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 82571.428571 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 70993.106656 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73597.518426 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72788.935817 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18378.332175 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18378.332175 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64892.825851 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64892.825851 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 79765.151515 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 82571.428571 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70993.106656 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66722.858109 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67103.370176 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 79765.151515 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 82571.428571 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70993.106656 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66722.858109 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67103.370176 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 147161.069686 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 147161.069686 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173241.755873 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173241.755873 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 147747.887233 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 147747.887233 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 90 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 90 # number of CleanEvict MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1787 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 1787 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133737 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133737 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16321 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16321 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.dtb.walker 67 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.itb.walker 5 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 35671 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 35743 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 67 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 16321 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 169408 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 185801 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 67 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 16321 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 169408 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 185801 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 602896 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::total 602896 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 13875 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::total 13875 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 616771 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 616771 # number of overall MSHR uncacheable misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 37875000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 37875000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8960834500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8960834500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1195971500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1195971500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.dtb.walker 5507500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker 365000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2711142000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2717014500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5507500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 365000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1195971500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11671976500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12873820500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5507500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 365000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1195971500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11671976500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 12873820500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 90257461500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 90257461500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2455867500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2455867500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 92713329000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 92713329000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.852170 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.852170 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.464442 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.464442 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016461 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016461 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker 0.000995 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.000359 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.025971 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024570 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000995 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000359 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016461 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101964 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.067954 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000995 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000359 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016461 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101964 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.067954 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21194.739787 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21194.739787 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67003.405939 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67003.405939 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73278.077324 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73278.077324 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 82201.492537 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 73000 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76004.092961 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76015.289707 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 82201.492537 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 73000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73278.077324 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68898.614587 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69288.219654 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 82201.492537 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 73000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73278.077324 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68898.614587 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69288.219654 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 149706.519035 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149706.519035 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 176999.459459 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176999.459459 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 150320.506314 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 150320.506314 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 3067430 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3066889 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13919 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13919 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1586560 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46781 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2230 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2230 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 288754 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 288754 # Transaction distribution -system.cpu.toL2Bus.trans_dist::MessageReq 1643 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 4 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1994880 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6121448 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 29602 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 170238 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8316168 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63832960 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207882816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 973632 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5848896 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 278538304 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 63315 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5007317 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.009852 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.098766 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadReq 602896 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3059319 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13875 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13875 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1734439 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1113474 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2547 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2547 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 287963 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 287963 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 991910 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1465068 # Transaction distribution +system.cpu.toL2Bus.trans_dist::MessageReq 1642 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 22 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 46720 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2973341 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6222105 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 35861 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 172954 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 9404261 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63456832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 208155201 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1084160 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5514304 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 278210497 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 220375 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 6313792 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.033219 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.179209 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 4957986 99.01% 99.01% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 49331 0.99% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 6104051 96.68% 96.68% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 209741 3.32% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5007317 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4072528967 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 6313792 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4643672976 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 555000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 564000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1500637871 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1489388443 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3138590336 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3104272690 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 21588991 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 24683477 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 118331389 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 110523908 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 223899 # Transaction distribution -system.iobus.trans_dist::ReadResp 223899 # Transaction distribution -system.iobus.trans_dist::WriteReq 57753 # Transaction distribution -system.iobus.trans_dist::WriteResp 11033 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.iobus.trans_dist::MessageReq 1643 # Transaction distribution -system.iobus.trans_dist::MessageResp 1643 # Transaction distribution +system.iobus.trans_dist::ReadReq 222096 # Transaction distribution +system.iobus.trans_dist::ReadResp 222096 # Transaction distribution +system.iobus.trans_dist::WriteReq 57708 # Transaction distribution +system.iobus.trans_dist::WriteResp 57708 # Transaction distribution +system.iobus.trans_dist::MessageReq 1642 # Transaction distribution +system.iobus.trans_dist::MessageResp 1642 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11042 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 423734 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 420172 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) @@ -1366,21 +1382,21 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 468050 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95254 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95254 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3286 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3286 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 566590 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 464350 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95258 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95258 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3284 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3284 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 562892 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6660 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 211867 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 210086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) @@ -1390,19 +1406,19 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 240311 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027800 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027800 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6572 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6572 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 3274683 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 3915016 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 238452 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027816 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027816 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 3272836 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 3914184 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 8775000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -1414,7 +1430,7 @@ system.iobus.reqLayer7.occupancy 50000 # La system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 211868000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 210087000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -1432,177 +1448,179 @@ system.iobus.reqLayer17.occupancy 9000 # La system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 257302678 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 242657095 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 457017000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 453362000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 50364257 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 50170000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1643000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1642000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47572 # number of replacements -system.iocache.tags.tagsinuse 0.078977 # Cycle average of tags in use +system.iocache.tags.replacements 47574 # number of replacements +system.iocache.tags.tagsinuse 0.103760 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47588 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47590 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4993305876000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.078977 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.004936 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.004936 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 4993210499000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103760 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006485 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.006485 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428643 # Number of tag accesses -system.iocache.tags.data_accesses 428643 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 907 # number of ReadReq misses -system.iocache.ReadReq_misses::total 907 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses -system.iocache.demand_misses::pc.south_bridge.ide 907 # number of demand (read+write) misses -system.iocache.demand_misses::total 907 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 907 # number of overall misses -system.iocache.overall_misses::total 907 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 142095944 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 142095944 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 8602345477 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 8602345477 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 142095944 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 142095944 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 142095944 # number of overall miss cycles -system.iocache.overall_miss_latency::total 142095944 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 907 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 907 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 907 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 907 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 907 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 907 # number of overall (read+write) accesses +system.iocache.tags.tag_accesses 428661 # Number of tag accesses +system.iocache.tags.data_accesses 428661 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 909 # number of ReadReq misses +system.iocache.ReadReq_misses::total 909 # number of ReadReq misses +system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses +system.iocache.demand_misses::pc.south_bridge.ide 909 # number of demand (read+write) misses +system.iocache.demand_misses::total 909 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 909 # number of overall misses +system.iocache.overall_misses::total 909 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 141558677 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 141558677 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 5512975418 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5512975418 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 141558677 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 141558677 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 141558677 # number of overall miss cycles +system.iocache.overall_miss_latency::total 141558677 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 909 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses) +system.iocache.demand_accesses::pc.south_bridge.ide 909 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 909 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 909 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 909 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 156665.869901 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 156665.869901 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 184125.545313 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 184125.545313 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 156665.869901 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 156665.869901 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 156665.869901 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 156665.869901 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 29724 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 155730.117712 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 155730.117712 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 118000.330009 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118000.330009 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 155730.117712 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 155730.117712 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 155730.117712 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 155730.117712 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 548 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 4480 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 46 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.634821 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 11.913043 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 907 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 907 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 907 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 907 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 907 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 907 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 94520448 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 94520448 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 6172895487 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6172895487 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 94520448 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 94520448 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 94520448 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 94520448 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 909 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 909 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 46720 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 909 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 909 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 909 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 909 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96108677 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 96108677 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3176975418 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3176975418 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 96108677 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 96108677 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 96108677 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 96108677 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 104212.180816 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 104212.180816 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 132125.331485 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 132125.331485 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 104212.180816 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 104212.180816 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 104212.180816 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 104212.180816 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 105730.117712 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 105730.117712 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 68000.330009 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68000.330009 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 105730.117712 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 105730.117712 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 105730.117712 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 105730.117712 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 657725 # Transaction distribution -system.membus.trans_dist::ReadResp 657721 # Transaction distribution -system.membus.trans_dist::WriteReq 13919 # Transaction distribution -system.membus.trans_dist::WriteResp 13919 # Transaction distribution -system.membus.trans_dist::Writeback 149517 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2208 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1727 # Transaction distribution -system.membus.trans_dist::ReadExReq 133760 # Transaction distribution -system.membus.trans_dist::ReadExResp 133758 # Transaction distribution -system.membus.trans_dist::MessageReq 1643 # Transaction distribution -system.membus.trans_dist::MessageResp 1643 # Transaction distribution -system.membus.trans_dist::BadAddressError 4 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3286 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3286 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 468050 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 769190 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 477841 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 8 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1715089 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141457 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 141457 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1859832 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6572 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6572 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 240311 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1538377 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18435328 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20214016 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26225708 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 1635 # Total snoops (count) -system.membus.snoop_fanout::samples 1005577 # Request fanout histogram -system.membus.snoop_fanout::mean 1.001634 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.040388 # Request fanout histogram +system.membus.trans_dist::ReadReq 602896 # Transaction distribution +system.membus.trans_dist::ReadResp 655847 # Transaction distribution +system.membus.trans_dist::WriteReq 13875 # Transaction distribution +system.membus.trans_dist::WriteResp 13875 # Transaction distribution +system.membus.trans_dist::Writeback 149737 # Transaction distribution +system.membus.trans_dist::CleanEvict 10183 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2524 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2074 # Transaction distribution +system.membus.trans_dist::ReadExReq 133454 # Transaction distribution +system.membus.trans_dist::ReadExResp 133450 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 52973 # Transaction distribution +system.membus.trans_dist::MessageReq 1642 # Transaction distribution +system.membus.trans_dist::MessageResp 1642 # Transaction distribution +system.membus.trans_dist::BadAddressError 22 # Transaction distribution +system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution +system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3284 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3284 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 464350 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 769192 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 487788 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 44 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1721374 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141823 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 141823 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1866481 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6568 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6568 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 238452 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1538381 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18425216 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20202049 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3015040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 3015040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 23223657 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 1607 # Total snoops (count) +system.membus.snoop_fanout::samples 1014551 # Request fanout histogram +system.membus.snoop_fanout::mean 1.001618 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.040197 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 1003934 99.84% 99.84% # Request fanout histogram -system.membus.snoop_fanout::2 1643 0.16% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 1012909 99.84% 99.84% # Request fanout histogram +system.membus.snoop_fanout::2 1642 0.16% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 2 # Request fanout histogram -system.membus.snoop_fanout::total 1005577 # Request fanout histogram -system.membus.reqLayer0.occupancy 357821000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1014551 # Request fanout histogram +system.membus.reqLayer0.occupancy 354940000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 388531000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 388594500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3286000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3284000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1203162900 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1018302522 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 5000 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 27500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1643000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1642000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2211768878 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2206598693 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 51465743 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 86075861 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 29 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt index 4c2a41024..7d82f190a 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt @@ -1,95 +1,95 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.305853 # Number of seconds simulated -sim_ticks 5305853045500 # Number of ticks simulated -final_tick 5305853045500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.305855 # Number of seconds simulated +sim_ticks 5305855051000 # Number of ticks simulated +final_tick 5305855051000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 178751 # Simulator instruction rate (inst/s) -host_op_rate 342595 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8842177355 # Simulator tick rate (ticks/s) -host_mem_usage 856496 # Number of bytes of host memory used -host_seconds 600.06 # Real time elapsed on the host -sim_insts 107261902 # Number of instructions simulated -sim_ops 205578300 # Number of ops (including micro ops) simulated +host_inst_rate 186796 # Simulator instruction rate (inst/s) +host_op_rate 357991 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9246678170 # Simulator tick rate (ticks/s) +host_mem_usage 1105624 # Number of bytes of host memory used +host_seconds 573.81 # Real time elapsed on the host +sim_insts 107186053 # Number of instructions simulated +sim_ops 205419480 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 11415232 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 11415232 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 9161984 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 9161984 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 178363 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 178363 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 143156 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 143156 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 2151441 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 2151441 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 1726769 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 1726769 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 3878211 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 3878211 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 178363 # Number of read requests accepted -system.mem_ctrls.writeReqs 143156 # Number of write requests accepted -system.mem_ctrls.readBursts 178363 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 143156 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 11360576 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 54656 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 9153536 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 11415232 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 9161984 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 854 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 108 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 11371136 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 11371136 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 9131456 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 9131456 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 177674 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 177674 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 142679 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 142679 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 2143130 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 2143130 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 1721015 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 1721015 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 3864145 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 3864145 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 177674 # Number of read requests accepted +system.mem_ctrls.writeReqs 142679 # Number of write requests accepted +system.mem_ctrls.readBursts 177674 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 142679 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 11313280 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 57856 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 9121152 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 11371136 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 9131456 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 904 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 135 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 10856 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 10881 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 10729 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 11226 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 11595 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 12060 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 11357 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 10544 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 10640 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 10408 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 10338 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 14247 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 10851 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 10291 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 10803 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 10683 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 8741 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 8453 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 8515 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 9195 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 9530 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 9557 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 9142 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 8665 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 8844 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 8855 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 8455 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 9314 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 8873 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 8616 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 9161 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 9108 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 10805 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 10794 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 10981 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 11389 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 11550 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 12175 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 10978 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 10407 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 10706 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 10369 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 10514 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 13718 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 10819 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 10294 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 10714 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 10557 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 8779 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 8773 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 8745 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 9209 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 9395 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 9648 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 8754 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 8594 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 8776 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 8713 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 8651 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 9041 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 8739 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 8605 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 9111 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 8985 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 5305852911000 # Total gap between requests +system.mem_ctrls.totGap 5305854916500 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 178363 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 177674 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 143156 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 177440 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 69 # What read queue length does an incoming req see +system.mem_ctrls.writePktSize::6 142679 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 176703 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 67 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -135,39 +135,39 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 2057 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 2808 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 8578 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 9141 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 8600 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 9229 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 9219 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 8361 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 9057 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 9077 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 8449 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 8526 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 8348 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 8471 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 8060 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 8092 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 8178 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 7986 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 125 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 114 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 101 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 94 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 84 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 73 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 59 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 51 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 33 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 27 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 19 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 9 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 3 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 2 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 2059 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 2790 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 8563 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 9122 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 8572 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 9212 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 9228 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 8314 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 9034 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 9060 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 8413 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 8500 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 8357 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 8453 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 8029 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 8097 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 8147 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 7952 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 108 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 85 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 89 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 75 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 64 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 57 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 48 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 39 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 28 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 18 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 9 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 4 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 2 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see @@ -184,213 +184,211 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 60721 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 337.841076 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 199.411090 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 344.057801 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 20489 33.74% 33.74% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 14673 24.16% 57.91% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 6364 10.48% 68.39% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 3396 5.59% 73.98% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 2745 4.52% 78.50% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 1826 3.01% 81.51% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 1362 2.24% 83.75% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 1430 2.36% 86.11% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 8436 13.89% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 60721 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 7928 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 22.388118 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 317.537098 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::0-1023 7922 99.92% 99.92% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::1024-2047 2 0.03% 99.95% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::2048-3071 2 0.03% 99.97% # Reads before turning the bus around for writes +system.mem_ctrls.bytesPerActivate::samples 60336 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 338.676213 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 200.551275 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 343.723517 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 20068 33.26% 33.26% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 14736 24.42% 57.68% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 6373 10.56% 68.25% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 3491 5.79% 74.03% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 2657 4.40% 78.44% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 1861 3.08% 81.52% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 1364 2.26% 83.78% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 1338 2.22% 86.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 8448 14.00% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 60336 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 7897 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 22.382170 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 317.489285 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::0-1023 7891 99.92% 99.92% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::1024-2047 3 0.04% 99.96% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::2048-3071 1 0.01% 99.97% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::10240-11263 1 0.01% 99.99% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::25600-26623 1 0.01% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 7928 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 7928 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 18.040363 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 17.696882 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 3.983964 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 5814 73.34% 73.34% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 14 0.18% 73.51% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 181 2.28% 75.79% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 14 0.18% 75.97% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::20 36 0.45% 76.43% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::21 489 6.17% 82.59% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::22 149 1.88% 84.47% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::23 53 0.67% 85.14% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::24 653 8.24% 93.38% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::25 113 1.43% 94.80% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::26 3 0.04% 94.84% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::27 13 0.16% 95.01% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::28 312 3.94% 98.94% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::29 4 0.05% 98.99% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::30 10 0.13% 99.12% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::31 5 0.06% 99.18% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::32 9 0.11% 99.29% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::33 9 0.11% 99.41% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::34 2 0.03% 99.43% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::35 3 0.04% 99.47% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::36 4 0.05% 99.52% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::37 5 0.06% 99.58% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::38 2 0.03% 99.61% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::39 3 0.04% 99.65% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::40 6 0.08% 99.72% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::41 2 0.03% 99.75% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::42 1 0.01% 99.76% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::43 3 0.04% 99.80% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::44 6 0.08% 99.87% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::45 2 0.03% 99.90% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::46 1 0.01% 99.91% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::47 1 0.01% 99.92% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::48 1 0.01% 99.94% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::49 2 0.03% 99.96% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::51 3 0.04% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 7928 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 1963261998 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 5291555748 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 887545000 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 11060.07 # Average queueing delay per DRAM burst +system.mem_ctrls.rdPerTurnAround::total 7897 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 7897 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 18.047106 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 17.696875 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 4.065797 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 5800 73.45% 73.45% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 9 0.11% 73.56% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 169 2.14% 75.70% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 20 0.25% 75.95% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 37 0.47% 76.42% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::21 500 6.33% 82.75% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::22 145 1.84% 84.59% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::23 43 0.54% 85.13% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::24 653 8.27% 93.40% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::25 111 1.41% 94.81% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::26 12 0.15% 94.96% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::27 19 0.24% 95.20% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::28 304 3.85% 99.05% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::29 7 0.09% 99.14% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::30 3 0.04% 99.18% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::31 6 0.08% 99.25% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::32 6 0.08% 99.33% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::33 2 0.03% 99.35% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::34 1 0.01% 99.37% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::35 3 0.04% 99.40% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::37 1 0.01% 99.42% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::38 3 0.04% 99.46% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::39 7 0.09% 99.54% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::40 3 0.04% 99.58% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::41 3 0.04% 99.62% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::42 6 0.08% 99.70% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::43 2 0.03% 99.72% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::44 6 0.08% 99.80% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::45 1 0.01% 99.81% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::47 1 0.01% 99.82% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::48 4 0.05% 99.87% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::51 9 0.11% 99.99% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::52 1 0.01% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 7897 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 1934453242 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 5248890742 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 883850000 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 10943.33 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 29810.07 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 2.14 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 1.73 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 2.15 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 1.73 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 29693.33 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 2.13 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 1.72 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 2.14 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 1.72 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.mem_ctrls.busUtil 0.03 # Data bus utilization in percentage system.mem_ctrls.busUtilRead 0.02 # Data bus utilization in percentage for reads system.mem_ctrls.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 24.94 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 141459 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 118352 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 79.69 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 82.74 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 16502455.25 # Average gap between requests -system.mem_ctrls.pageHitRate 81.05 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 231139440 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 126117750 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 696134400 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 465251040 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 346552109280 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 149731396200 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 3052164794250 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 3549966942360 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 669.066980 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 5077378950000 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 177173880000 # Time in different power states +system.mem_ctrls.avgWrQLen 24.42 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 140774 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 118177 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 79.64 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 82.91 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 16562526.08 # Average gap between requests +system.mem_ctrls.pageHitRate 81.10 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 229839120 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 125408250 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 694816200 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 465892560 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 346552617840 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 149179147425 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 3052653894750 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 3549901616145 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 669.053686 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 5078195767000 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 177174140000 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 51294057500 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 50484766750 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 227911320 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 124356375 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 688428000 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 461544480 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 346552109280 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 149042883510 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 3052768752750 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 3549865985715 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 669.047952 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 5078391595500 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 177173880000 # Time in different power states +system.mem_ctrls_1.actEnergy 226301040 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 123477750 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 683982000 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 457624080 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 346552617840 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 148537848690 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 3053216437500 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 3549798288900 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 669.034212 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 5079136661250 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 177174140000 # Time in different power states system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 50287445500 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 49544125250 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.numCycles 10611706091 # number of cpu cycles simulated +system.cpu0.numCycles 10611710102 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 59111887 # Number of instructions committed -system.cpu0.committedOps 113456709 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 106426265 # Number of integer alu accesses +system.cpu0.committedInsts 59039296 # Number of instructions committed +system.cpu0.committedOps 113305650 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 106292214 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 48 # Number of float alu accesses -system.cpu0.num_func_calls 1016173 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 10055603 # number of instructions that are conditional controls -system.cpu0.num_int_insts 106426265 # number of integer instructions +system.cpu0.num_func_calls 1017385 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 10037497 # number of instructions that are conditional controls +system.cpu0.num_int_insts 106292214 # number of integer instructions system.cpu0.num_fp_insts 48 # number of float instructions -system.cpu0.num_int_register_reads 200823032 # number of times the integer registers were read -system.cpu0.num_int_register_writes 90335124 # number of times the integer registers were written +system.cpu0.num_int_register_reads 200616677 # number of times the integer registers were read +system.cpu0.num_int_register_writes 90211380 # number of times the integer registers were written system.cpu0.num_fp_register_reads 48 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 61044422 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 44109295 # number of times the CC registers were written -system.cpu0.num_mem_refs 12452626 # number of memory refs -system.cpu0.num_load_insts 7522002 # Number of load instructions -system.cpu0.num_store_insts 4930624 # Number of store instructions -system.cpu0.num_idle_cycles 10088968020.334099 # Number of idle cycles -system.cpu0.num_busy_cycles 522738070.665901 # Number of busy cycles -system.cpu0.not_idle_fraction 0.049261 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.950739 # Percentage of idle cycles -system.cpu0.Branches 11433567 # Number of branches fetched -system.cpu0.op_class::No_OpClass 130284 0.11% 0.11% # Class of executed instruction -system.cpu0.op_class::IntAlu 100735872 88.79% 88.90% # Class of executed instruction -system.cpu0.op_class::IntMult 86129 0.08% 88.98% # Class of executed instruction -system.cpu0.op_class::IntDiv 56904 0.05% 89.03% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::FloatCvt 16 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::MemRead 7517799 6.63% 95.65% # Class of executed instruction -system.cpu0.op_class::MemWrite 4930624 4.35% 100.00% # Class of executed instruction +system.cpu0.num_cc_register_reads 60966470 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 44030878 # number of times the CC registers were written +system.cpu0.num_mem_refs 12456031 # number of memory refs +system.cpu0.num_load_insts 7518228 # Number of load instructions +system.cpu0.num_store_insts 4937803 # Number of store instructions +system.cpu0.num_idle_cycles 10088651138.334099 # Number of idle cycles +system.cpu0.num_busy_cycles 523058963.665901 # Number of busy cycles +system.cpu0.not_idle_fraction 0.049291 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.950709 # Percentage of idle cycles +system.cpu0.Branches 11416966 # Number of branches fetched +system.cpu0.op_class::No_OpClass 131109 0.12% 0.12% # Class of executed instruction +system.cpu0.op_class::IntAlu 100580264 88.77% 88.88% # Class of executed instruction +system.cpu0.op_class::IntMult 86269 0.08% 88.96% # Class of executed instruction +system.cpu0.op_class::IntDiv 57079 0.05% 89.01% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::FloatCvt 16 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::MemRead 7514027 6.63% 95.64% # Class of executed instruction +system.cpu0.op_class::MemWrite 4937803 4.36% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 113457628 # Class of executed instruction +system.cpu0.op_class::total 113306567 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu1.numCycles 10608768454 # number of cpu cycles simulated +system.cpu1.numCycles 10608777066 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 48150015 # Number of instructions committed -system.cpu1.committedOps 92121591 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 88447957 # Number of integer alu accesses +system.cpu1.committedInsts 48146757 # Number of instructions committed +system.cpu1.committedOps 92113830 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 88441893 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 48 # Number of float alu accesses -system.cpu1.num_func_calls 1752470 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 8220366 # number of instructions that are conditional controls -system.cpu1.num_int_insts 88447957 # number of integer instructions +system.cpu1.num_func_calls 1752446 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 8219760 # number of instructions that are conditional controls +system.cpu1.num_int_insts 88441893 # number of integer instructions system.cpu1.num_fp_insts 48 # number of float instructions -system.cpu1.num_int_register_reads 171418672 # number of times the integer registers were read -system.cpu1.num_int_register_writes 73201138 # number of times the integer registers were written +system.cpu1.num_int_register_reads 171408328 # number of times the integer registers were read +system.cpu1.num_int_register_writes 73196137 # number of times the integer registers were written system.cpu1.num_fp_register_reads 48 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 50927853 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 32747912 # number of times the CC registers were written -system.cpu1.num_mem_refs 14125902 # number of memory refs -system.cpu1.num_load_insts 9133895 # Number of load instructions -system.cpu1.num_store_insts 4992007 # Number of store instructions -system.cpu1.num_idle_cycles 10273983246.713898 # Number of idle cycles -system.cpu1.num_busy_cycles 334785207.286102 # Number of busy cycles -system.cpu1.not_idle_fraction 0.031557 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.968443 # Percentage of idle cycles -system.cpu1.Branches 10582274 # Number of branches fetched -system.cpu1.op_class::No_OpClass 169782 0.18% 0.18% # Class of executed instruction -system.cpu1.op_class::IntAlu 77660290 84.30% 84.49% # Class of executed instruction -system.cpu1.op_class::IntMult 98483 0.11% 84.59% # Class of executed instruction -system.cpu1.op_class::IntDiv 71910 0.08% 84.67% # Class of executed instruction +system.cpu1.num_cc_register_reads 50924734 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 32745964 # number of times the CC registers were written +system.cpu1.num_mem_refs 14124901 # number of memory refs +system.cpu1.num_load_insts 9133293 # Number of load instructions +system.cpu1.num_store_insts 4991608 # Number of store instructions +system.cpu1.num_idle_cycles 10274072284.207695 # Number of idle cycles +system.cpu1.num_busy_cycles 334704781.792306 # Number of busy cycles +system.cpu1.not_idle_fraction 0.031550 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.968450 # Percentage of idle cycles +system.cpu1.Branches 10581617 # Number of branches fetched +system.cpu1.op_class::No_OpClass 169787 0.18% 0.18% # Class of executed instruction +system.cpu1.op_class::IntAlu 77653530 84.30% 84.49% # Class of executed instruction +system.cpu1.op_class::IntMult 98479 0.11% 84.59% # Class of executed instruction +system.cpu1.op_class::IntDiv 71918 0.08% 84.67% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 84.67% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 84.67% # Class of executed instruction system.cpu1.op_class::FloatCvt 16 0.00% 84.67% # Class of executed instruction @@ -417,17 +415,17 @@ system.cpu1.op_class::SimdFloatMisc 0 0.00% 84.67% # Cl system.cpu1.op_class::SimdFloatMult 0 0.00% 84.67% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 84.67% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 84.67% # Class of executed instruction -system.cpu1.op_class::MemRead 9129754 9.91% 94.58% # Class of executed instruction -system.cpu1.op_class::MemWrite 4992007 5.42% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 9129153 9.91% 94.58% # Class of executed instruction +system.cpu1.op_class::MemWrite 4991608 5.42% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 92122242 # Class of executed instruction +system.cpu1.op_class::total 92114491 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.iobus.trans_dist::ReadReq 857753 # Transaction distribution -system.iobus.trans_dist::ReadResp 857753 # Transaction distribution -system.iobus.trans_dist::WriteReq 36065 # Transaction distribution -system.iobus.trans_dist::WriteResp 36065 # Transaction distribution +system.iobus.trans_dist::ReadReq 842290 # Transaction distribution +system.iobus.trans_dist::ReadResp 842290 # Transaction distribution +system.iobus.trans_dist::WriteReq 35657 # Transaction distribution +system.iobus.trans_dist::WriteResp 35657 # Transaction distribution system.iobus.trans_dist::MessageReq 1791 # Transaction distribution system.iobus.trans_dist::MessageResp 1791 # Transaction distribution system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1702 # Packet count per connected master and slave (bytes) @@ -440,15 +438,15 @@ system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.p system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 66 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 38 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 934582 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 917434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 964 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 90 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 14814 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 742772 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 729402 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 158 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio 2126 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1702492 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1671974 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 5284 # Packet count per connected master and slave (bytes) @@ -456,9 +454,9 @@ system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.p system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 396 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 28 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 30942 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 30330 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 384 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 31030 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 30418 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 12448 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) @@ -466,8 +464,8 @@ system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.p system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 76 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 4614 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 85378 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 1791218 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 84154 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 1759476 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 3404 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 3292 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6696 # Cumulative packet size per connected master and slave (bytes) @@ -478,15 +476,15 @@ system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 33 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 19 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 467291 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 458717 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1928 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 45 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 7407 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1485538 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1458798 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 316 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio 4252 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1970762 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1935448 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 8 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3394 # Cumulative packet size per connected master and slave (bytes) @@ -494,9 +492,9 @@ system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 198 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 14 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15471 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15165 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 768 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 15515 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 15209 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 6224 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) @@ -504,53 +502,53 @@ system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 9225 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 51075 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2028533 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 50000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 50463 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 1992607 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 43500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 7000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 6500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 10224000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 9032500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 143500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 154500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 1064000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 940000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 97500 # Layer occupancy (ticks) +system.iobus.reqLayer5.occupancy 92000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 56000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 52500 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 20660000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 20247500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 700937500 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 458718000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 1276000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 1157500 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 31144500 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 30508000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 23664000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 20468500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 468374820 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 369412820 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 7594080 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 7528580 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 1329500 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 1593000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2404400 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2422900 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 2023552000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1846190500 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 60655000 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 57610000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD). @@ -567,48 +565,48 @@ system.pc.south_bridge.ide.disks1.dma_write_txs 1 system.ruby.clk_domain.clock 500 # Clock period in ticks system.ruby.delayHist::bucket_size 4 # delay histogram for all message system.ruby.delayHist::max_bucket 39 # delay histogram for all message -system.ruby.delayHist::samples 10895286 # delay histogram for all message -system.ruby.delayHist::mean 0.442462 # delay histogram for all message -system.ruby.delayHist::stdev 1.830078 # delay histogram for all message -system.ruby.delayHist | 10293202 94.47% 94.47% | 1309 0.01% 94.49% | 600320 5.51% 100.00% | 166 0.00% 100.00% | 230 0.00% 100.00% | 12 0.00% 100.00% | 47 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 10895286 # delay histogram for all message +system.ruby.delayHist::samples 10891010 # delay histogram for all message +system.ruby.delayHist::mean 0.442869 # delay histogram for all message +system.ruby.delayHist::stdev 1.830823 # delay histogram for all message +system.ruby.delayHist | 10288616 94.47% 94.47% | 1282 0.01% 94.48% | 600649 5.52% 100.00% | 161 0.00% 100.00% | 257 0.00% 100.00% | 11 0.00% 100.00% | 34 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 10891010 # delay histogram for all message system.ruby.outstanding_req_hist::bucket_size 1 system.ruby.outstanding_req_hist::max_bucket 9 -system.ruby.outstanding_req_hist::samples 152835089 +system.ruby.outstanding_req_hist::samples 152756591 system.ruby.outstanding_req_hist::mean 1.000166 system.ruby.outstanding_req_hist::gmean 1.000115 -system.ruby.outstanding_req_hist::stdev 0.012900 -system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 152809653 99.98% 99.98% | 25436 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 152835089 -system.ruby.latency_hist::bucket_size 256 -system.ruby.latency_hist::max_bucket 2559 -system.ruby.latency_hist::samples 152835088 -system.ruby.latency_hist::mean 3.434218 -system.ruby.latency_hist::gmean 3.107238 -system.ruby.latency_hist::stdev 5.763390 -system.ruby.latency_hist | 152826003 99.99% 99.99% | 6324 0.00% 100.00% | 2683 0.00% 100.00% | 40 0.00% 100.00% | 37 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 152835088 +system.ruby.outstanding_req_hist::stdev 0.012901 +system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 152731162 99.98% 99.98% | 25429 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 152756591 +system.ruby.latency_hist::bucket_size 128 +system.ruby.latency_hist::max_bucket 1279 +system.ruby.latency_hist::samples 152756590 +system.ruby.latency_hist::mean 3.433707 +system.ruby.latency_hist::gmean 3.107293 +system.ruby.latency_hist::stdev 5.733578 +system.ruby.latency_hist | 152719525 99.98% 99.98% | 28048 0.02% 99.99% | 2695 0.00% 100.00% | 3637 0.00% 100.00% | 2109 0.00% 100.00% | 523 0.00% 100.00% | 9 0.00% 100.00% | 20 0.00% 100.00% | 17 0.00% 100.00% | 7 0.00% 100.00% +system.ruby.latency_hist::total 152756590 system.ruby.hit_latency_hist::bucket_size 1 system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 150173511 +system.ruby.hit_latency_hist::samples 150094333 system.ruby.hit_latency_hist::mean 3 system.ruby.hit_latency_hist::gmean 3.000000 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 150173511 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 150173511 -system.ruby.miss_latency_hist::bucket_size 256 -system.ruby.miss_latency_hist::max_bucket 2559 -system.ruby.miss_latency_hist::samples 2661577 -system.ruby.miss_latency_hist::mean 27.933971 -system.ruby.miss_latency_hist::gmean 22.542647 -system.ruby.miss_latency_hist::stdev 36.007178 -system.ruby.miss_latency_hist | 2652492 99.66% 99.66% | 6324 0.24% 99.90% | 2683 0.10% 100.00% | 40 0.00% 100.00% | 37 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 2661577 -system.ruby.l1_cntrl0.L1Dcache.demand_hits 11100819 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 532265 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 11633084 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 68582952 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 323144 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 68906096 # Number of cache demand accesses +system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 150094333 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 150094333 +system.ruby.miss_latency_hist::bucket_size 128 +system.ruby.miss_latency_hist::max_bucket 1279 +system.ruby.miss_latency_hist::samples 2662257 +system.ruby.miss_latency_hist::mean 27.885506 +system.ruby.miss_latency_hist::gmean 22.530762 +system.ruby.miss_latency_hist::stdev 35.745831 +system.ruby.miss_latency_hist | 2625192 98.61% 98.61% | 28048 1.05% 99.66% | 2695 0.10% 99.76% | 3637 0.14% 99.90% | 2109 0.08% 99.98% | 523 0.02% 100.00% | 9 0.00% 100.00% | 20 0.00% 100.00% | 17 0.00% 100.00% | 7 0.00% 100.00% +system.ruby.miss_latency_hist::total 2662257 +system.ruby.l1_cntrl0.L1Dcache.demand_hits 11119260 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 532503 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 11651763 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Icache.demand_hits 68488995 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Icache.demand_misses 323914 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Icache.demand_accesses 68812909 # Number of cache demand accesses system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -618,13 +616,13 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl0.fully_busy_cycles 15 # cycles for which number of transistions == max transitions -system.ruby.l1_cntrl1.L1Dcache.demand_hits 12795046 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Dcache.demand_misses 1313851 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Dcache.demand_accesses 14108897 # Number of cache demand accesses -system.ruby.l1_cntrl1.L1Icache.demand_hits 57694694 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Icache.demand_misses 492317 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Icache.demand_accesses 58187011 # Number of cache demand accesses +system.ruby.l1_cntrl0.fully_busy_cycles 16 # cycles for which number of transistions == max transitions +system.ruby.l1_cntrl1.L1Dcache.demand_hits 12794938 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Dcache.demand_misses 1313574 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Dcache.demand_accesses 14108512 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Icache.demand_hits 57691140 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Icache.demand_misses 492266 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Icache.demand_accesses 58183406 # Number of cache demand accesses system.ruby.l1_cntrl1.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl1.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl1.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -635,71 +633,71 @@ system.ruby.l1_cntrl1.prefetcher.partial_hits 0 system.ruby.l1_cntrl1.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed system.ruby.l1_cntrl1.fully_busy_cycles 7 # cycles for which number of transistions == max transitions -system.ruby.l2_cntrl0.L2cache.demand_hits 2434372 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 227205 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 2661577 # Number of cache demand accesses -system.ruby.l2_cntrl0.fully_busy_cycles 1 # cycles for which number of transistions == max transitions +system.ruby.l2_cntrl0.L2cache.demand_hits 2435460 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 226797 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 2662257 # Number of cache demand accesses +system.ruby.l2_cntrl0.fully_busy_cycles 5 # cycles for which number of transistions == max transitions system.ruby.memctrl_clk_domain.clock 1500 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 0.029987 -system.ruby.network.routers0.msg_count.Control::0 855409 -system.ruby.network.routers0.msg_count.Request_Control::2 42371 -system.ruby.network.routers0.msg_count.Response_Data::1 883866 -system.ruby.network.routers0.msg_count.Response_Control::1 509923 -system.ruby.network.routers0.msg_count.Response_Control::2 507294 -system.ruby.network.routers0.msg_count.Writeback_Data::0 298509 -system.ruby.network.routers0.msg_count.Writeback_Data::1 176 -system.ruby.network.routers0.msg_count.Writeback_Control::0 170526 -system.ruby.network.routers0.msg_bytes.Control::0 6843272 -system.ruby.network.routers0.msg_bytes.Request_Control::2 338968 -system.ruby.network.routers0.msg_bytes.Response_Data::1 63638352 -system.ruby.network.routers0.msg_bytes.Response_Control::1 4079384 -system.ruby.network.routers0.msg_bytes.Response_Control::2 4058352 -system.ruby.network.routers0.msg_bytes.Writeback_Data::0 21492648 -system.ruby.network.routers0.msg_bytes.Writeback_Data::1 12672 -system.ruby.network.routers0.msg_bytes.Writeback_Control::0 1364208 -system.ruby.network.routers1.percent_links_utilized 0.057152 -system.ruby.network.routers1.msg_count.Control::0 1806168 -system.ruby.network.routers1.msg_count.Request_Control::2 40332 -system.ruby.network.routers1.msg_count.Response_Data::1 1830141 -system.ruby.network.routers1.msg_count.Response_Control::1 1256659 -system.ruby.network.routers1.msg_count.Response_Control::2 1255808 -system.ruby.network.routers1.msg_count.Writeback_Data::0 276119 -system.ruby.network.routers1.msg_count.Writeback_Data::1 194 -system.ruby.network.routers1.msg_count.Writeback_Control::0 942229 -system.ruby.network.routers1.msg_bytes.Control::0 14449344 -system.ruby.network.routers1.msg_bytes.Request_Control::2 322656 -system.ruby.network.routers1.msg_bytes.Response_Data::1 131770152 -system.ruby.network.routers1.msg_bytes.Response_Control::1 10053272 -system.ruby.network.routers1.msg_bytes.Response_Control::2 10046464 -system.ruby.network.routers1.msg_bytes.Writeback_Data::0 19880568 -system.ruby.network.routers1.msg_bytes.Writeback_Data::1 13968 -system.ruby.network.routers1.msg_bytes.Writeback_Control::0 7537832 -system.ruby.network.routers2.percent_links_utilized 0.091505 -system.ruby.network.routers2.msg_count.Control::0 2839493 -system.ruby.network.routers2.msg_count.Request_Control::2 81198 -system.ruby.network.routers2.msg_count.Response_Data::1 2891200 -system.ruby.network.routers2.msg_count.Response_Control::1 1848800 -system.ruby.network.routers2.msg_count.Response_Control::2 1763102 -system.ruby.network.routers2.msg_count.Writeback_Data::0 574628 -system.ruby.network.routers2.msg_count.Writeback_Data::1 370 -system.ruby.network.routers2.msg_count.Writeback_Control::0 1112755 -system.ruby.network.routers2.msg_bytes.Control::0 22715944 -system.ruby.network.routers2.msg_bytes.Request_Control::2 649584 -system.ruby.network.routers2.msg_bytes.Response_Data::1 208166400 -system.ruby.network.routers2.msg_bytes.Response_Control::1 14790400 -system.ruby.network.routers2.msg_bytes.Response_Control::2 14104816 -system.ruby.network.routers2.msg_bytes.Writeback_Data::0 41373216 -system.ruby.network.routers2.msg_bytes.Writeback_Data::1 26640 -system.ruby.network.routers2.msg_bytes.Writeback_Control::0 8902040 -system.ruby.network.routers3.percent_links_utilized 0.006812 -system.ruby.network.routers3.msg_count.Control::0 177916 -system.ruby.network.routers3.msg_count.Response_Data::1 276580 -system.ruby.network.routers3.msg_count.Response_Control::1 130228 +system.ruby.network.routers0.percent_links_utilized 0.030013 +system.ruby.network.routers0.msg_count.Control::0 856417 +system.ruby.network.routers0.msg_count.Request_Control::2 42660 +system.ruby.network.routers0.msg_count.Response_Data::1 884950 +system.ruby.network.routers0.msg_count.Response_Control::1 510141 +system.ruby.network.routers0.msg_count.Response_Control::2 507455 +system.ruby.network.routers0.msg_count.Writeback_Data::0 298492 +system.ruby.network.routers0.msg_count.Writeback_Data::1 178 +system.ruby.network.routers0.msg_count.Writeback_Control::0 170402 +system.ruby.network.routers0.msg_bytes.Control::0 6851336 +system.ruby.network.routers0.msg_bytes.Request_Control::2 341280 +system.ruby.network.routers0.msg_bytes.Response_Data::1 63716400 +system.ruby.network.routers0.msg_bytes.Response_Control::1 4081128 +system.ruby.network.routers0.msg_bytes.Response_Control::2 4059640 +system.ruby.network.routers0.msg_bytes.Writeback_Data::0 21491424 +system.ruby.network.routers0.msg_bytes.Writeback_Data::1 12816 +system.ruby.network.routers0.msg_bytes.Writeback_Control::0 1363216 +system.ruby.network.routers1.percent_links_utilized 0.057139 +system.ruby.network.routers1.msg_count.Control::0 1805840 +system.ruby.network.routers1.msg_count.Request_Control::2 40537 +system.ruby.network.routers1.msg_count.Response_Data::1 1830038 +system.ruby.network.routers1.msg_count.Response_Control::1 1255303 +system.ruby.network.routers1.msg_count.Response_Control::2 1254313 +system.ruby.network.routers1.msg_count.Writeback_Data::0 276120 +system.ruby.network.routers1.msg_count.Writeback_Data::1 190 +system.ruby.network.routers1.msg_count.Writeback_Control::0 940436 +system.ruby.network.routers1.msg_bytes.Control::0 14446720 +system.ruby.network.routers1.msg_bytes.Request_Control::2 324296 +system.ruby.network.routers1.msg_bytes.Response_Data::1 131762736 +system.ruby.network.routers1.msg_bytes.Response_Control::1 10042424 +system.ruby.network.routers1.msg_bytes.Response_Control::2 10034504 +system.ruby.network.routers1.msg_bytes.Writeback_Data::0 19880640 +system.ruby.network.routers1.msg_bytes.Writeback_Data::1 13680 +system.ruby.network.routers1.msg_bytes.Writeback_Control::0 7523488 +system.ruby.network.routers2.percent_links_utilized 0.091475 +system.ruby.network.routers2.msg_count.Control::0 2839469 +system.ruby.network.routers2.msg_count.Request_Control::2 81710 +system.ruby.network.routers2.msg_count.Response_Data::1 2890401 +system.ruby.network.routers2.msg_count.Response_Control::1 1846120 +system.ruby.network.routers2.msg_count.Response_Control::2 1761768 +system.ruby.network.routers2.msg_count.Writeback_Data::0 574612 +system.ruby.network.routers2.msg_count.Writeback_Data::1 368 +system.ruby.network.routers2.msg_count.Writeback_Control::0 1110838 +system.ruby.network.routers2.msg_bytes.Control::0 22715752 +system.ruby.network.routers2.msg_bytes.Request_Control::2 653680 +system.ruby.network.routers2.msg_bytes.Response_Data::1 208108872 +system.ruby.network.routers2.msg_bytes.Response_Control::1 14768960 +system.ruby.network.routers2.msg_bytes.Response_Control::2 14094144 +system.ruby.network.routers2.msg_bytes.Writeback_Data::0 41372064 +system.ruby.network.routers2.msg_bytes.Writeback_Data::1 26496 +system.ruby.network.routers2.msg_bytes.Writeback_Control::0 8886704 +system.ruby.network.routers3.percent_links_utilized 0.006783 +system.ruby.network.routers3.msg_count.Control::0 177212 +system.ruby.network.routers3.msg_count.Response_Data::1 275392 +system.ruby.network.routers3.msg_count.Response_Control::1 129266 system.ruby.network.routers3.msg_count.Writeback_Control::0 47545 system.ruby.network.routers3.msg_count.Writeback_Control::1 46736 -system.ruby.network.routers3.msg_bytes.Control::0 1423328 -system.ruby.network.routers3.msg_bytes.Response_Data::1 19913760 -system.ruby.network.routers3.msg_bytes.Response_Control::1 1041824 +system.ruby.network.routers3.msg_bytes.Control::0 1417696 +system.ruby.network.routers3.msg_bytes.Response_Data::1 19828224 +system.ruby.network.routers3.msg_bytes.Response_Control::1 1034128 system.ruby.network.routers3.msg_bytes.Writeback_Control::0 380360 system.ruby.network.routers3.msg_bytes.Writeback_Control::1 373888 system.ruby.network.routers4.percent_links_utilized 0.000239 @@ -710,120 +708,120 @@ system.ruby.network.routers4.msg_bytes.Response_Data::1 58248 system.ruby.network.routers4.msg_bytes.Writeback_Control::0 380360 system.ruby.network.routers4.msg_bytes.Writeback_Control::1 373888 system.ruby.network.routers5.percent_links_utilized 0 -system.ruby.network.routers6.percent_links_utilized 0.030950 -system.ruby.network.routers6.msg_count.Control::0 2839493 -system.ruby.network.routers6.msg_count.Request_Control::2 82703 -system.ruby.network.routers6.msg_count.Response_Data::1 2941298 -system.ruby.network.routers6.msg_count.Response_Control::1 1872805 -system.ruby.network.routers6.msg_count.Response_Control::2 1763102 -system.ruby.network.routers6.msg_count.Writeback_Data::0 574628 -system.ruby.network.routers6.msg_count.Writeback_Data::1 370 -system.ruby.network.routers6.msg_count.Writeback_Control::0 1160300 +system.ruby.network.routers6.percent_links_utilized 0.030942 +system.ruby.network.routers6.msg_count.Control::0 2839469 +system.ruby.network.routers6.msg_count.Request_Control::2 83197 +system.ruby.network.routers6.msg_count.Response_Data::1 2940795 +system.ruby.network.routers6.msg_count.Response_Control::1 1870415 +system.ruby.network.routers6.msg_count.Response_Control::2 1761768 +system.ruby.network.routers6.msg_count.Writeback_Data::0 574612 +system.ruby.network.routers6.msg_count.Writeback_Data::1 368 +system.ruby.network.routers6.msg_count.Writeback_Control::0 1158383 system.ruby.network.routers6.msg_count.Writeback_Control::1 46736 -system.ruby.network.routers6.msg_bytes.Control::0 22715944 -system.ruby.network.routers6.msg_bytes.Request_Control::2 661624 -system.ruby.network.routers6.msg_bytes.Response_Data::1 211773456 -system.ruby.network.routers6.msg_bytes.Response_Control::1 14982440 -system.ruby.network.routers6.msg_bytes.Response_Control::2 14104816 -system.ruby.network.routers6.msg_bytes.Writeback_Data::0 41373216 -system.ruby.network.routers6.msg_bytes.Writeback_Data::1 26640 -system.ruby.network.routers6.msg_bytes.Writeback_Control::0 9282400 +system.ruby.network.routers6.msg_bytes.Control::0 22715752 +system.ruby.network.routers6.msg_bytes.Request_Control::2 665576 +system.ruby.network.routers6.msg_bytes.Response_Data::1 211737240 +system.ruby.network.routers6.msg_bytes.Response_Control::1 14963320 +system.ruby.network.routers6.msg_bytes.Response_Control::2 14094144 +system.ruby.network.routers6.msg_bytes.Writeback_Data::0 41372064 +system.ruby.network.routers6.msg_bytes.Writeback_Data::1 26496 +system.ruby.network.routers6.msg_bytes.Writeback_Control::0 9267064 system.ruby.network.routers6.msg_bytes.Writeback_Control::1 373888 -system.ruby.network.msg_count.Control 8518479 -system.ruby.network.msg_count.Request_Control 246604 -system.ruby.network.msg_count.Response_Data 8823894 -system.ruby.network.msg_count.Response_Control 10907721 -system.ruby.network.msg_count.Writeback_Data 1724994 -system.ruby.network.msg_count.Writeback_Control 3621108 -system.ruby.network.msg_byte.Control 68147832 -system.ruby.network.msg_byte.Request_Control 1972832 -system.ruby.network.msg_byte.Response_Data 635320368 -system.ruby.network.msg_byte.Response_Control 87261768 -system.ruby.network.msg_byte.Writeback_Data 124199568 -system.ruby.network.msg_byte.Writeback_Control 28968864 -system.ruby.network.routers0.throttle0.link_utilization 0.038287 -system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 42371 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 843260 -system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 494161 -system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2 338968 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 60714720 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 3953288 -system.ruby.network.routers0.throttle1.link_utilization 0.021686 -system.ruby.network.routers0.throttle1.msg_count.Control::0 855409 -system.ruby.network.routers0.throttle1.msg_count.Response_Data::1 40606 -system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 15762 -system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 507294 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0 298509 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1 176 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 170526 -system.ruby.network.routers0.throttle1.msg_bytes.Control::0 6843272 -system.ruby.network.routers0.throttle1.msg_bytes.Response_Data::1 2923632 -system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1 126096 -system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 4058352 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0 21492648 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1 12672 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 1364208 -system.ruby.network.routers1.throttle0.link_utilization 0.082198 -system.ruby.network.routers1.throttle0.msg_count.Request_Control::2 40332 -system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 1796167 -system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 1239377 -system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::2 322656 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1 129324024 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1 9915016 -system.ruby.network.routers1.throttle1.link_utilization 0.032106 -system.ruby.network.routers1.throttle1.msg_count.Control::0 1806168 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 33974 -system.ruby.network.routers1.throttle1.msg_count.Response_Control::1 17282 -system.ruby.network.routers1.throttle1.msg_count.Response_Control::2 1255808 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::0 276119 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::1 194 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::0 942229 -system.ruby.network.routers1.throttle1.msg_bytes.Control::0 14449344 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 2446128 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 138256 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::2 10046464 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::0 19880568 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::1 13968 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0 7537832 -system.ruby.network.routers2.throttle0.link_utilization 0.059676 -system.ruby.network.routers2.throttle0.msg_count.Control::0 2661577 -system.ruby.network.routers2.throttle0.msg_count.Response_Data::1 203207 -system.ruby.network.routers2.throttle0.msg_count.Response_Control::1 123979 -system.ruby.network.routers2.throttle0.msg_count.Response_Control::2 1763102 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::0 574628 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::1 370 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::0 1112755 -system.ruby.network.routers2.throttle0.msg_bytes.Control::0 21292616 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1 14630904 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1 991832 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::2 14104816 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::0 41373216 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::1 26640 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::0 8902040 -system.ruby.network.routers2.throttle1.link_utilization 0.123335 -system.ruby.network.routers2.throttle1.msg_count.Control::0 177916 -system.ruby.network.routers2.throttle1.msg_count.Request_Control::2 81198 -system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 2687993 -system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 1724821 -system.ruby.network.routers2.throttle1.msg_bytes.Control::0 1423328 -system.ruby.network.routers2.throttle1.msg_bytes.Request_Control::2 649584 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 193535496 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 13798568 -system.ruby.network.routers3.throttle0.link_utilization 0.005284 -system.ruby.network.routers3.throttle0.msg_count.Control::0 177916 -system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 97855 -system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 15288 +system.ruby.network.msg_count.Control 8518407 +system.ruby.network.msg_count.Request_Control 248104 +system.ruby.network.msg_count.Response_Data 8822385 +system.ruby.network.msg_count.Response_Control 10896549 +system.ruby.network.msg_count.Writeback_Data 1724940 +system.ruby.network.msg_count.Writeback_Control 3615357 +system.ruby.network.msg_byte.Control 68147256 +system.ruby.network.msg_byte.Request_Control 1984832 +system.ruby.network.msg_byte.Response_Data 635211720 +system.ruby.network.msg_byte.Response_Control 87172392 +system.ruby.network.msg_byte.Writeback_Data 124195680 +system.ruby.network.msg_byte.Writeback_Control 28922856 +system.ruby.network.routers0.throttle0.link_utilization 0.038328 +system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 42660 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 844192 +system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 494162 +system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2 341280 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 60781824 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 3953296 +system.ruby.network.routers0.throttle1.link_utilization 0.021698 +system.ruby.network.routers0.throttle1.msg_count.Control::0 856417 +system.ruby.network.routers0.throttle1.msg_count.Response_Data::1 40758 +system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 15979 +system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 507455 +system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0 298492 +system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1 178 +system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 170402 +system.ruby.network.routers0.throttle1.msg_bytes.Control::0 6851336 +system.ruby.network.routers0.throttle1.msg_bytes.Response_Data::1 2934576 +system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1 127832 +system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 4059640 +system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0 21491424 +system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1 12816 +system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 1363216 +system.ruby.network.routers1.throttle0.link_utilization 0.082169 +system.ruby.network.routers1.throttle0.msg_count.Request_Control::2 40537 +system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 1795610 +system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 1238038 +system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::2 324296 +system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1 129283920 +system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1 9904304 +system.ruby.network.routers1.throttle1.link_utilization 0.032108 +system.ruby.network.routers1.throttle1.msg_count.Control::0 1805840 +system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 34428 +system.ruby.network.routers1.throttle1.msg_count.Response_Control::1 17265 +system.ruby.network.routers1.throttle1.msg_count.Response_Control::2 1254313 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::0 276120 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::1 190 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::0 940436 +system.ruby.network.routers1.throttle1.msg_bytes.Control::0 14446720 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 2478816 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 138120 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::2 10034504 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::0 19880640 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::1 13680 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0 7523488 +system.ruby.network.routers2.throttle0.link_utilization 0.059642 +system.ruby.network.routers2.throttle0.msg_count.Control::0 2662257 +system.ruby.network.routers2.throttle0.msg_count.Response_Data::1 202813 +system.ruby.network.routers2.throttle0.msg_count.Response_Control::1 123155 +system.ruby.network.routers2.throttle0.msg_count.Response_Control::2 1761768 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::0 574612 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::1 368 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::0 1110838 +system.ruby.network.routers2.throttle0.msg_bytes.Control::0 21298056 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1 14602536 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1 985240 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::2 14094144 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::0 41372064 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::1 26496 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::0 8886704 +system.ruby.network.routers2.throttle1.link_utilization 0.123308 +system.ruby.network.routers2.throttle1.msg_count.Control::0 177212 +system.ruby.network.routers2.throttle1.msg_count.Request_Control::2 81710 +system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 2687588 +system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 1722965 +system.ruby.network.routers2.throttle1.msg_bytes.Control::0 1417696 +system.ruby.network.routers2.throttle1.msg_bytes.Request_Control::2 653680 +system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 193506336 +system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 13783720 +system.ruby.network.routers3.throttle0.link_utilization 0.005259 +system.ruby.network.routers3.throttle0.msg_count.Control::0 177212 +system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 97371 +system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 15060 system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0 47545 -system.ruby.network.routers3.throttle0.msg_bytes.Control::0 1423328 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 7045560 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 122304 +system.ruby.network.routers3.throttle0.msg_bytes.Control::0 1417696 +system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 7010712 +system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 120480 system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0 380360 -system.ruby.network.routers3.throttle1.link_utilization 0.008341 -system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 178725 -system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 114940 +system.ruby.network.routers3.throttle1.link_utilization 0.008307 +system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 178021 +system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 114206 system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::1 46736 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1 12868200 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1 919520 +system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1 12817512 +system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1 913648 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1 373888 system.ruby.network.routers4.throttle0.link_utilization 0.000255 system.ruby.network.routers4.throttle0.msg_count.Response_Data::1 809 @@ -835,43 +833,43 @@ system.ruby.network.routers4.throttle1.msg_count.Writeback_Control::0 475 system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::0 380360 system.ruby.network.routers5.throttle0.link_utilization 0 system.ruby.network.routers5.throttle1.link_utilization 0 -system.ruby.network.routers6.throttle0.link_utilization 0.038287 -system.ruby.network.routers6.throttle0.msg_count.Request_Control::2 42371 -system.ruby.network.routers6.throttle0.msg_count.Response_Data::1 843260 -system.ruby.network.routers6.throttle0.msg_count.Response_Control::1 494161 -system.ruby.network.routers6.throttle0.msg_bytes.Request_Control::2 338968 -system.ruby.network.routers6.throttle0.msg_bytes.Response_Data::1 60714720 -system.ruby.network.routers6.throttle0.msg_bytes.Response_Control::1 3953288 -system.ruby.network.routers6.throttle1.link_utilization 0.082198 -system.ruby.network.routers6.throttle1.msg_count.Request_Control::2 40332 -system.ruby.network.routers6.throttle1.msg_count.Response_Data::1 1796167 -system.ruby.network.routers6.throttle1.msg_count.Response_Control::1 1239377 -system.ruby.network.routers6.throttle1.msg_bytes.Request_Control::2 322656 -system.ruby.network.routers6.throttle1.msg_bytes.Response_Data::1 129324024 -system.ruby.network.routers6.throttle1.msg_bytes.Response_Control::1 9915016 -system.ruby.network.routers6.throttle2.link_utilization 0.059676 -system.ruby.network.routers6.throttle2.msg_count.Control::0 2661577 -system.ruby.network.routers6.throttle2.msg_count.Response_Data::1 203207 -system.ruby.network.routers6.throttle2.msg_count.Response_Control::1 123979 -system.ruby.network.routers6.throttle2.msg_count.Response_Control::2 1763102 -system.ruby.network.routers6.throttle2.msg_count.Writeback_Data::0 574628 -system.ruby.network.routers6.throttle2.msg_count.Writeback_Data::1 370 -system.ruby.network.routers6.throttle2.msg_count.Writeback_Control::0 1112755 -system.ruby.network.routers6.throttle2.msg_bytes.Control::0 21292616 -system.ruby.network.routers6.throttle2.msg_bytes.Response_Data::1 14630904 -system.ruby.network.routers6.throttle2.msg_bytes.Response_Control::1 991832 -system.ruby.network.routers6.throttle2.msg_bytes.Response_Control::2 14104816 -system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::0 41373216 -system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::1 26640 -system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Control::0 8902040 -system.ruby.network.routers6.throttle3.link_utilization 0.005284 -system.ruby.network.routers6.throttle3.msg_count.Control::0 177916 -system.ruby.network.routers6.throttle3.msg_count.Response_Data::1 97855 -system.ruby.network.routers6.throttle3.msg_count.Response_Control::1 15288 +system.ruby.network.routers6.throttle0.link_utilization 0.038328 +system.ruby.network.routers6.throttle0.msg_count.Request_Control::2 42660 +system.ruby.network.routers6.throttle0.msg_count.Response_Data::1 844192 +system.ruby.network.routers6.throttle0.msg_count.Response_Control::1 494162 +system.ruby.network.routers6.throttle0.msg_bytes.Request_Control::2 341280 +system.ruby.network.routers6.throttle0.msg_bytes.Response_Data::1 60781824 +system.ruby.network.routers6.throttle0.msg_bytes.Response_Control::1 3953296 +system.ruby.network.routers6.throttle1.link_utilization 0.082169 +system.ruby.network.routers6.throttle1.msg_count.Request_Control::2 40537 +system.ruby.network.routers6.throttle1.msg_count.Response_Data::1 1795610 +system.ruby.network.routers6.throttle1.msg_count.Response_Control::1 1238038 +system.ruby.network.routers6.throttle1.msg_bytes.Request_Control::2 324296 +system.ruby.network.routers6.throttle1.msg_bytes.Response_Data::1 129283920 +system.ruby.network.routers6.throttle1.msg_bytes.Response_Control::1 9904304 +system.ruby.network.routers6.throttle2.link_utilization 0.059642 +system.ruby.network.routers6.throttle2.msg_count.Control::0 2662257 +system.ruby.network.routers6.throttle2.msg_count.Response_Data::1 202813 +system.ruby.network.routers6.throttle2.msg_count.Response_Control::1 123155 +system.ruby.network.routers6.throttle2.msg_count.Response_Control::2 1761768 +system.ruby.network.routers6.throttle2.msg_count.Writeback_Data::0 574612 +system.ruby.network.routers6.throttle2.msg_count.Writeback_Data::1 368 +system.ruby.network.routers6.throttle2.msg_count.Writeback_Control::0 1110838 +system.ruby.network.routers6.throttle2.msg_bytes.Control::0 21298056 +system.ruby.network.routers6.throttle2.msg_bytes.Response_Data::1 14602536 +system.ruby.network.routers6.throttle2.msg_bytes.Response_Control::1 985240 +system.ruby.network.routers6.throttle2.msg_bytes.Response_Control::2 14094144 +system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::0 41372064 +system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::1 26496 +system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Control::0 8886704 +system.ruby.network.routers6.throttle3.link_utilization 0.005259 +system.ruby.network.routers6.throttle3.msg_count.Control::0 177212 +system.ruby.network.routers6.throttle3.msg_count.Response_Data::1 97371 +system.ruby.network.routers6.throttle3.msg_count.Response_Control::1 15060 system.ruby.network.routers6.throttle3.msg_count.Writeback_Control::0 47545 -system.ruby.network.routers6.throttle3.msg_bytes.Control::0 1423328 -system.ruby.network.routers6.throttle3.msg_bytes.Response_Data::1 7045560 -system.ruby.network.routers6.throttle3.msg_bytes.Response_Control::1 122304 +system.ruby.network.routers6.throttle3.msg_bytes.Control::0 1417696 +system.ruby.network.routers6.throttle3.msg_bytes.Response_Data::1 7010712 +system.ruby.network.routers6.throttle3.msg_bytes.Response_Control::1 120480 system.ruby.network.routers6.throttle3.msg_bytes.Writeback_Control::0 380360 system.ruby.network.routers6.throttle4.link_utilization 0.000255 system.ruby.network.routers6.throttle4.msg_count.Response_Data::1 809 @@ -881,176 +879,176 @@ system.ruby.network.routers6.throttle4.msg_bytes.Writeback_Control::1 3738 system.ruby.network.routers6.throttle5.link_utilization 0 system.ruby.delayVCHist.vnet_0::bucket_size 4 # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_0::max_bucket 39 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::samples 6112062 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::mean 0.754100 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::stdev 2.339998 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0 | 5536581 90.58% 90.58% | 390 0.01% 90.59% | 574653 9.40% 99.99% | 162 0.00% 100.00% | 217 0.00% 100.00% | 12 0.00% 100.00% | 47 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::total 6112062 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::samples 6109475 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::mean 0.754420 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::stdev 2.340404 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0 | 5533989 90.58% 90.58% | 406 0.01% 90.59% | 574630 9.41% 99.99% | 158 0.00% 100.00% | 247 0.00% 100.00% | 11 0.00% 100.00% | 34 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::total 6109475 # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_1::bucket_size 2 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_1::max_bucket 19 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 4700521 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::mean 0.045023 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::stdev 0.596216 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 4673467 99.42% 99.42% | 451 0.01% 99.43% | 352 0.01% 99.44% | 567 0.01% 99.45% | 25509 0.54% 100.00% | 158 0.00% 100.00% | 2 0.00% 100.00% | 2 0.00% 100.00% | 10 0.00% 100.00% | 3 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 4700521 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 4698338 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::mean 0.045583 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::stdev 0.599791 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 4670953 99.42% 99.42% | 477 0.01% 99.43% | 336 0.01% 99.43% | 540 0.01% 99.45% | 25880 0.55% 100.00% | 139 0.00% 100.00% | 2 0.00% 100.00% | 1 0.00% 100.00% | 10 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 4698338 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 82703 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::mean 0.000121 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::stdev 0.015550 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 82698 99.99% 99.99% | 0 0.00% 99.99% | 5 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 82703 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 83197 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::mean 0.000192 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::stdev 0.019611 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 83189 99.99% 99.99% | 0 0.00% 99.99% | 8 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 83197 # delay histogram for vnet_2 system.ruby.LD.latency_hist::bucket_size 128 system.ruby.LD.latency_hist::max_bucket 1279 -system.ruby.LD.latency_hist::samples 15017729 -system.ruby.LD.latency_hist::mean 4.875603 -system.ruby.LD.latency_hist::gmean 3.591894 -system.ruby.LD.latency_hist::stdev 9.357158 -system.ruby.LD.latency_hist | 15001612 99.89% 99.89% | 13925 0.09% 99.99% | 816 0.01% 99.99% | 883 0.01% 100.00% | 364 0.00% 100.00% | 107 0.00% 100.00% | 3 0.00% 100.00% | 9 0.00% 100.00% | 7 0.00% 100.00% | 3 0.00% 100.00% -system.ruby.LD.latency_hist::total 15017729 +system.ruby.LD.latency_hist::samples 15027912 +system.ruby.LD.latency_hist::mean 4.869020 +system.ruby.LD.latency_hist::gmean 3.591147 +system.ruby.LD.latency_hist::stdev 9.231737 +system.ruby.LD.latency_hist | 15011958 99.89% 99.89% | 13851 0.09% 99.99% | 851 0.01% 99.99% | 792 0.01% 100.00% | 329 0.00% 100.00% | 121 0.00% 100.00% | 2 0.00% 100.00% | 3 0.00% 100.00% | 4 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.LD.latency_hist::total 15027912 system.ruby.LD.hit_latency_hist::bucket_size 1 system.ruby.LD.hit_latency_hist::max_bucket 9 -system.ruby.LD.hit_latency_hist::samples 13626729 +system.ruby.LD.hit_latency_hist::samples 13637263 system.ruby.LD.hit_latency_hist::mean 3 system.ruby.LD.hit_latency_hist::gmean 3.000000 -system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 13626729 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 13626729 +system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 13637263 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist::total 13637263 system.ruby.LD.miss_latency_hist::bucket_size 128 system.ruby.LD.miss_latency_hist::max_bucket 1279 -system.ruby.LD.miss_latency_hist::samples 1391000 -system.ruby.LD.miss_latency_hist::mean 23.249676 -system.ruby.LD.miss_latency_hist::gmean 20.961439 -system.ruby.LD.miss_latency_hist::stdev 23.942041 -system.ruby.LD.miss_latency_hist | 1374883 98.84% 98.84% | 13925 1.00% 99.84% | 816 0.06% 99.90% | 883 0.06% 99.96% | 364 0.03% 99.99% | 107 0.01% 100.00% | 3 0.00% 100.00% | 9 0.00% 100.00% | 7 0.00% 100.00% | 3 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 1391000 -system.ruby.ST.latency_hist::bucket_size 256 -system.ruby.ST.latency_hist::max_bucket 2559 -system.ruby.ST.latency_hist::samples 9551572 -system.ruby.ST.latency_hist::mean 5.175450 -system.ruby.ST.latency_hist::gmean 3.300315 -system.ruby.ST.latency_hist::stdev 17.651145 -system.ruby.ST.latency_hist | 9545751 99.94% 99.94% | 3768 0.04% 99.98% | 2002 0.02% 100.00% | 25 0.00% 100.00% | 25 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 9551572 +system.ruby.LD.miss_latency_hist::samples 1390649 +system.ruby.LD.miss_latency_hist::mean 23.197386 +system.ruby.LD.miss_latency_hist::gmean 20.952196 +system.ruby.LD.miss_latency_hist::stdev 23.468925 +system.ruby.LD.miss_latency_hist | 1374695 98.85% 98.85% | 13851 1.00% 99.85% | 851 0.06% 99.91% | 792 0.06% 99.97% | 329 0.02% 99.99% | 121 0.01% 100.00% | 2 0.00% 100.00% | 3 0.00% 100.00% | 4 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.LD.miss_latency_hist::total 1390649 +system.ruby.ST.latency_hist::bucket_size 128 +system.ruby.ST.latency_hist::max_bucket 1279 +system.ruby.ST.latency_hist::samples 9558783 +system.ruby.ST.latency_hist::mean 5.170026 +system.ruby.ST.latency_hist::gmean 3.300098 +system.ruby.ST.latency_hist::stdev 17.579302 +system.ruby.ST.latency_hist | 9544781 99.85% 99.85% | 8164 0.09% 99.94% | 1330 0.01% 99.95% | 2504 0.03% 99.98% | 1628 0.02% 100.00% | 340 0.00% 100.00% | 7 0.00% 100.00% | 12 0.00% 100.00% | 11 0.00% 100.00% | 6 0.00% 100.00% +system.ruby.ST.latency_hist::total 9558783 system.ruby.ST.hit_latency_hist::bucket_size 1 system.ruby.ST.hit_latency_hist::max_bucket 9 -system.ruby.ST.hit_latency_hist::samples 9200825 +system.ruby.ST.hit_latency_hist::samples 9207752 system.ruby.ST.hit_latency_hist::mean 3 system.ruby.ST.hit_latency_hist::gmean 3.000000 -system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 9200825 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 9200825 -system.ruby.ST.miss_latency_hist::bucket_size 256 -system.ruby.ST.miss_latency_hist::max_bucket 2559 -system.ruby.ST.miss_latency_hist::samples 350747 -system.ruby.ST.miss_latency_hist::mean 62.242032 -system.ruby.ST.miss_latency_hist::gmean 40.314149 -system.ruby.ST.miss_latency_hist::stdev 71.440751 -system.ruby.ST.miss_latency_hist | 344926 98.34% 98.34% | 3768 1.07% 99.41% | 2002 0.57% 99.99% | 25 0.01% 99.99% | 25 0.01% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 350747 +system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 9207752 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist::total 9207752 +system.ruby.ST.miss_latency_hist::bucket_size 128 +system.ruby.ST.miss_latency_hist::max_bucket 1279 +system.ruby.ST.miss_latency_hist::samples 351031 +system.ruby.ST.miss_latency_hist::mean 62.091086 +system.ruby.ST.miss_latency_hist::gmean 40.236579 +system.ruby.ST.miss_latency_hist::stdev 71.074662 +system.ruby.ST.miss_latency_hist | 337029 96.01% 96.01% | 8164 2.33% 98.34% | 1330 0.38% 98.72% | 2504 0.71% 99.43% | 1628 0.46% 99.89% | 340 0.10% 99.99% | 7 0.00% 99.99% | 12 0.00% 100.00% | 11 0.00% 100.00% | 6 0.00% 100.00% +system.ruby.ST.miss_latency_hist::total 351031 system.ruby.IFETCH.latency_hist::bucket_size 128 system.ruby.IFETCH.latency_hist::max_bucket 1279 -system.ruby.IFETCH.latency_hist::samples 127093107 -system.ruby.IFETCH.latency_hist::mean 3.119052 -system.ruby.IFETCH.latency_hist::gmean 3.036517 -system.ruby.IFETCH.latency_hist::stdev 2.234317 -system.ruby.IFETCH.latency_hist | 127086452 99.99% 99.99% | 5646 0.00% 100.00% | 489 0.00% 100.00% | 322 0.00% 100.00% | 142 0.00% 100.00% | 52 0.00% 100.00% | 0 0.00% 100.00% | 2 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist::total 127093107 +system.ruby.IFETCH.latency_hist::samples 126996315 +system.ruby.IFETCH.latency_hist::mean 3.119134 +system.ruby.IFETCH.latency_hist::gmean 3.036572 +system.ruby.IFETCH.latency_hist::stdev 2.233716 +system.ruby.IFETCH.latency_hist | 126989642 99.99% 99.99% | 5673 0.00% 100.00% | 484 0.00% 100.00% | 317 0.00% 100.00% | 137 0.00% 100.00% | 55 0.00% 100.00% | 0 0.00% 100.00% | 5 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::total 126996315 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 system.ruby.IFETCH.hit_latency_hist::max_bucket 9 -system.ruby.IFETCH.hit_latency_hist::samples 126277646 +system.ruby.IFETCH.hit_latency_hist::samples 126180135 system.ruby.IFETCH.hit_latency_hist::mean 3 system.ruby.IFETCH.hit_latency_hist::gmean 3.000000 -system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 126277646 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist::total 126277646 +system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 126180135 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist::total 126180135 system.ruby.IFETCH.miss_latency_hist::bucket_size 128 system.ruby.IFETCH.miss_latency_hist::max_bucket 1279 -system.ruby.IFETCH.miss_latency_hist::samples 815461 -system.ruby.IFETCH.miss_latency_hist::mean 21.554760 -system.ruby.IFETCH.miss_latency_hist::gmean 19.772157 -system.ruby.IFETCH.miss_latency_hist::stdev 20.880175 -system.ruby.IFETCH.miss_latency_hist | 808806 99.18% 99.18% | 5646 0.69% 99.88% | 489 0.06% 99.94% | 322 0.04% 99.98% | 142 0.02% 99.99% | 52 0.01% 100.00% | 0 0.00% 100.00% | 2 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist::total 815461 +system.ruby.IFETCH.miss_latency_hist::samples 816180 +system.ruby.IFETCH.miss_latency_hist::mean 21.537108 +system.ruby.IFETCH.miss_latency_hist::gmean 19.766480 +system.ruby.IFETCH.miss_latency_hist::stdev 20.855244 +system.ruby.IFETCH.miss_latency_hist | 809507 99.18% 99.18% | 5673 0.70% 99.88% | 484 0.06% 99.94% | 317 0.04% 99.98% | 137 0.02% 99.99% | 55 0.01% 100.00% | 0 0.00% 100.00% | 5 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::total 816180 system.ruby.RMW_Read.latency_hist::bucket_size 128 system.ruby.RMW_Read.latency_hist::max_bucket 1279 -system.ruby.RMW_Read.latency_hist::samples 493320 -system.ruby.RMW_Read.latency_hist::mean 6.020587 -system.ruby.RMW_Read.latency_hist::gmean 3.953175 -system.ruby.RMW_Read.latency_hist::stdev 10.251324 -system.ruby.RMW_Read.latency_hist | 493147 99.96% 99.96% | 127 0.03% 99.99% | 17 0.00% 99.99% | 15 0.00% 100.00% | 9 0.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.RMW_Read.latency_hist::total 493320 +system.ruby.RMW_Read.latency_hist::samples 494272 +system.ruby.RMW_Read.latency_hist::mean 6.020764 +system.ruby.RMW_Read.latency_hist::gmean 3.952362 +system.ruby.RMW_Read.latency_hist::stdev 10.313773 +system.ruby.RMW_Read.latency_hist | 494092 99.96% 99.96% | 129 0.03% 99.99% | 18 0.00% 99.99% | 18 0.00% 100.00% | 11 0.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.latency_hist::total 494272 system.ruby.RMW_Read.hit_latency_hist::bucket_size 1 system.ruby.RMW_Read.hit_latency_hist::max_bucket 9 -system.ruby.RMW_Read.hit_latency_hist::samples 428060 +system.ruby.RMW_Read.hit_latency_hist::samples 428940 system.ruby.RMW_Read.hit_latency_hist::mean 3 system.ruby.RMW_Read.hit_latency_hist::gmean 3.000000 -system.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 428060 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.RMW_Read.hit_latency_hist::total 428060 +system.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 428940 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.hit_latency_hist::total 428940 system.ruby.RMW_Read.miss_latency_hist::bucket_size 128 system.ruby.RMW_Read.miss_latency_hist::max_bucket 1279 -system.ruby.RMW_Read.miss_latency_hist::samples 65260 -system.ruby.RMW_Read.miss_latency_hist::mean 25.833527 -system.ruby.RMW_Read.miss_latency_hist::gmean 24.149766 -system.ruby.RMW_Read.miss_latency_hist::stdev 18.493474 -system.ruby.RMW_Read.miss_latency_hist | 65087 99.73% 99.73% | 127 0.19% 99.93% | 17 0.03% 99.96% | 15 0.02% 99.98% | 9 0.01% 99.99% | 4 0.01% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.RMW_Read.miss_latency_hist::total 65260 +system.ruby.RMW_Read.miss_latency_hist::samples 65332 +system.ruby.RMW_Read.miss_latency_hist::mean 25.853716 +system.ruby.RMW_Read.miss_latency_hist::gmean 24.153784 +system.ruby.RMW_Read.miss_latency_hist::stdev 18.748956 +system.ruby.RMW_Read.miss_latency_hist | 65152 99.72% 99.72% | 129 0.20% 99.92% | 18 0.03% 99.95% | 18 0.03% 99.98% | 11 0.02% 99.99% | 4 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.miss_latency_hist::total 65332 system.ruby.Locked_RMW_Read.latency_hist::bucket_size 128 system.ruby.Locked_RMW_Read.latency_hist::max_bucket 1279 -system.ruby.Locked_RMW_Read.latency_hist::samples 339680 -system.ruby.Locked_RMW_Read.latency_hist::mean 5.345204 -system.ruby.Locked_RMW_Read.latency_hist::gmean 3.780937 -system.ruby.Locked_RMW_Read.latency_hist::stdev 8.076413 -system.ruby.Locked_RMW_Read.latency_hist | 339429 99.93% 99.93% | 234 0.07% 99.99% | 11 0.00% 100.00% | 3 0.00% 100.00% | 1 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Read.latency_hist::total 339680 +system.ruby.Locked_RMW_Read.latency_hist::samples 339654 +system.ruby.Locked_RMW_Read.latency_hist::mean 5.351331 +system.ruby.Locked_RMW_Read.latency_hist::gmean 3.780101 +system.ruby.Locked_RMW_Read.latency_hist::stdev 8.370233 +system.ruby.Locked_RMW_Read.latency_hist | 339398 99.92% 99.92% | 231 0.07% 99.99% | 12 0.00% 100.00% | 6 0.00% 100.00% | 4 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Read.latency_hist::total 339654 system.ruby.Locked_RMW_Read.hit_latency_hist::bucket_size 1 system.ruby.Locked_RMW_Read.hit_latency_hist::max_bucket 9 -system.ruby.Locked_RMW_Read.hit_latency_hist::samples 300571 +system.ruby.Locked_RMW_Read.hit_latency_hist::samples 300589 system.ruby.Locked_RMW_Read.hit_latency_hist::mean 3 system.ruby.Locked_RMW_Read.hit_latency_hist::gmean 3.000000 -system.ruby.Locked_RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 300571 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Read.hit_latency_hist::total 300571 +system.ruby.Locked_RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 300589 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Read.hit_latency_hist::total 300589 system.ruby.Locked_RMW_Read.miss_latency_hist::bucket_size 128 system.ruby.Locked_RMW_Read.miss_latency_hist::max_bucket 1279 -system.ruby.Locked_RMW_Read.miss_latency_hist::samples 39109 -system.ruby.Locked_RMW_Read.miss_latency_hist::mean 23.369199 -system.ruby.Locked_RMW_Read.miss_latency_hist::gmean 22.378025 -system.ruby.Locked_RMW_Read.miss_latency_hist::stdev 14.121215 -system.ruby.Locked_RMW_Read.miss_latency_hist | 38858 99.36% 99.36% | 234 0.60% 99.96% | 11 0.03% 99.98% | 3 0.01% 99.99% | 1 0.00% 99.99% | 2 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Read.miss_latency_hist::total 39109 +system.ruby.Locked_RMW_Read.miss_latency_hist::samples 39065 +system.ruby.Locked_RMW_Read.miss_latency_hist::mean 23.443850 +system.ruby.Locked_RMW_Read.miss_latency_hist::gmean 22.382210 +system.ruby.Locked_RMW_Read.miss_latency_hist::stdev 15.468459 +system.ruby.Locked_RMW_Read.miss_latency_hist | 38809 99.34% 99.34% | 231 0.59% 99.94% | 12 0.03% 99.97% | 6 0.02% 99.98% | 4 0.01% 99.99% | 3 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Read.miss_latency_hist::total 39065 system.ruby.Locked_RMW_Write.latency_hist::bucket_size 1 system.ruby.Locked_RMW_Write.latency_hist::max_bucket 9 -system.ruby.Locked_RMW_Write.latency_hist::samples 339680 +system.ruby.Locked_RMW_Write.latency_hist::samples 339654 system.ruby.Locked_RMW_Write.latency_hist::mean 3 system.ruby.Locked_RMW_Write.latency_hist::gmean 3.000000 -system.ruby.Locked_RMW_Write.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 339680 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Write.latency_hist::total 339680 +system.ruby.Locked_RMW_Write.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 339654 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Write.latency_hist::total 339654 system.ruby.Locked_RMW_Write.hit_latency_hist::bucket_size 1 system.ruby.Locked_RMW_Write.hit_latency_hist::max_bucket 9 -system.ruby.Locked_RMW_Write.hit_latency_hist::samples 339680 +system.ruby.Locked_RMW_Write.hit_latency_hist::samples 339654 system.ruby.Locked_RMW_Write.hit_latency_hist::mean 3 system.ruby.Locked_RMW_Write.hit_latency_hist::gmean 3.000000 -system.ruby.Locked_RMW_Write.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 339680 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Write.hit_latency_hist::total 339680 -system.ruby.Directory_Controller.Fetch 177916 0.00% 0.00% -system.ruby.Directory_Controller.Data 97855 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 178363 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 143156 0.00% 0.00% +system.ruby.Locked_RMW_Write.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 339654 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Write.hit_latency_hist::total 339654 +system.ruby.Directory_Controller.Fetch 177212 0.00% 0.00% +system.ruby.Directory_Controller.Data 97371 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 177674 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 142679 0.00% 0.00% system.ruby.Directory_Controller.DMA_READ 809 0.00% 0.00% system.ruby.Directory_Controller.DMA_WRITE 46736 0.00% 0.00% -system.ruby.Directory_Controller.CleanReplacement 15288 0.00% 0.00% -system.ruby.Directory_Controller.I.Fetch 177916 0.00% 0.00% -system.ruby.Directory_Controller.I.DMA_READ 447 0.00% 0.00% -system.ruby.Directory_Controller.I.DMA_WRITE 45301 0.00% 0.00% -system.ruby.Directory_Controller.ID.Memory_Data 447 0.00% 0.00% -system.ruby.Directory_Controller.ID_W.Memory_Ack 45301 0.00% 0.00% -system.ruby.Directory_Controller.M.Data 96058 0.00% 0.00% -system.ruby.Directory_Controller.M.DMA_READ 362 0.00% 0.00% -system.ruby.Directory_Controller.M.DMA_WRITE 1435 0.00% 0.00% -system.ruby.Directory_Controller.M.CleanReplacement 15288 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 177916 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 96058 0.00% 0.00% -system.ruby.Directory_Controller.M_DRD.Data 362 0.00% 0.00% -system.ruby.Directory_Controller.M_DRDI.Memory_Ack 362 0.00% 0.00% -system.ruby.Directory_Controller.M_DWR.Data 1435 0.00% 0.00% -system.ruby.Directory_Controller.M_DWRI.Memory_Ack 1435 0.00% 0.00% +system.ruby.Directory_Controller.CleanReplacement 15060 0.00% 0.00% +system.ruby.Directory_Controller.I.Fetch 177212 0.00% 0.00% +system.ruby.Directory_Controller.I.DMA_READ 462 0.00% 0.00% +system.ruby.Directory_Controller.I.DMA_WRITE 45308 0.00% 0.00% +system.ruby.Directory_Controller.ID.Memory_Data 462 0.00% 0.00% +system.ruby.Directory_Controller.ID_W.Memory_Ack 45308 0.00% 0.00% +system.ruby.Directory_Controller.M.Data 95596 0.00% 0.00% +system.ruby.Directory_Controller.M.DMA_READ 347 0.00% 0.00% +system.ruby.Directory_Controller.M.DMA_WRITE 1428 0.00% 0.00% +system.ruby.Directory_Controller.M.CleanReplacement 15060 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 177212 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 95596 0.00% 0.00% +system.ruby.Directory_Controller.M_DRD.Data 347 0.00% 0.00% +system.ruby.Directory_Controller.M_DRDI.Memory_Ack 347 0.00% 0.00% +system.ruby.Directory_Controller.M_DWR.Data 1428 0.00% 0.00% +system.ruby.Directory_Controller.M_DWRI.Memory_Ack 1428 0.00% 0.00% system.ruby.DMA_Controller.ReadRequest | 809 100.00% 100.00% | 0 0.00% 100.00% system.ruby.DMA_Controller.ReadRequest::total 809 system.ruby.DMA_Controller.WriteRequest | 46736 100.00% 100.00% | 0 0.00% 100.00% @@ -1067,169 +1065,169 @@ system.ruby.DMA_Controller.BUSY_RD.Data | 809 100.00% 100.00% | system.ruby.DMA_Controller.BUSY_RD.Data::total 809 system.ruby.DMA_Controller.BUSY_WR.Ack | 46736 100.00% 100.00% | 0 0.00% 100.00% system.ruby.DMA_Controller.BUSY_WR.Ack::total 46736 -system.ruby.L1Cache_Controller.Load | 6268725 41.74% 41.74% | 8749004 58.26% 100.00% -system.ruby.L1Cache_Controller.Load::total 15017729 -system.ruby.L1Cache_Controller.Ifetch | 68906101 54.22% 54.22% | 58187012 45.78% 100.00% -system.ruby.L1Cache_Controller.Ifetch::total 127093113 -system.ruby.L1Cache_Controller.Store | 5364359 50.02% 50.02% | 5359893 49.98% 100.00% -system.ruby.L1Cache_Controller.Store::total 10724252 -system.ruby.L1Cache_Controller.Inv | 15938 47.70% 47.70% | 17476 52.30% 100.00% -system.ruby.L1Cache_Controller.Inv::total 33414 -system.ruby.L1Cache_Controller.L1_Replacement | 827888 31.76% 31.76% | 1778547 68.24% 100.00% -system.ruby.L1Cache_Controller.L1_Replacement::total 2606435 -system.ruby.L1Cache_Controller.Fwd_GETX | 12260 51.09% 51.09% | 11738 48.91% 100.00% -system.ruby.L1Cache_Controller.Fwd_GETX::total 23998 -system.ruby.L1Cache_Controller.Fwd_GETS | 14169 56.03% 56.03% | 11118 43.97% 100.00% -system.ruby.L1Cache_Controller.Fwd_GETS::total 25287 +system.ruby.L1Cache_Controller.Load | 6279317 41.78% 41.78% | 8748595 58.22% 100.00% +system.ruby.L1Cache_Controller.Load::total 15027912 +system.ruby.L1Cache_Controller.Ifetch | 68812914 54.18% 54.18% | 58183407 45.82% 100.00% +system.ruby.L1Cache_Controller.Ifetch::total 126996321 +system.ruby.L1Cache_Controller.Store | 5372446 50.06% 50.06% | 5359917 49.94% 100.00% +system.ruby.L1Cache_Controller.Store::total 10732363 +system.ruby.L1Cache_Controller.Inv | 16157 48.07% 48.07% | 17455 51.93% 100.00% +system.ruby.L1Cache_Controller.Inv::total 33612 +system.ruby.L1Cache_Controller.L1_Replacement | 828605 31.79% 31.79% | 1777971 68.21% 100.00% +system.ruby.L1Cache_Controller.L1_Replacement::total 2606576 +system.ruby.L1Cache_Controller.Fwd_GETX | 12248 51.07% 51.07% | 11736 48.93% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETX::total 23984 +system.ruby.L1Cache_Controller.Fwd_GETS | 14251 55.67% 55.67% | 11346 44.33% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETS::total 25597 system.ruby.L1Cache_Controller.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.Fwd_GET_INSTR::total 4 -system.ruby.L1Cache_Controller.Data | 828 44.64% 44.64% | 1027 55.36% 100.00% -system.ruby.L1Cache_Controller.Data::total 1855 -system.ruby.L1Cache_Controller.Data_Exclusive | 252860 19.71% 19.71% | 1029835 80.29% 100.00% -system.ruby.L1Cache_Controller.Data_Exclusive::total 1282695 -system.ruby.L1Cache_Controller.DataS_fromL1 | 11118 43.96% 43.96% | 14173 56.04% 100.00% -system.ruby.L1Cache_Controller.DataS_fromL1::total 25291 -system.ruby.L1Cache_Controller.Data_all_Acks | 578454 43.51% 43.51% | 751132 56.49% 100.00% -system.ruby.L1Cache_Controller.Data_all_Acks::total 1329586 -system.ruby.L1Cache_Controller.Ack | 12149 54.85% 54.85% | 10001 45.15% 100.00% -system.ruby.L1Cache_Controller.Ack::total 22150 -system.ruby.L1Cache_Controller.Ack_all | 12977 54.06% 54.06% | 11028 45.94% 100.00% -system.ruby.L1Cache_Controller.Ack_all::total 24005 -system.ruby.L1Cache_Controller.WB_Ack | 469035 27.80% 27.80% | 1218348 72.20% 100.00% -system.ruby.L1Cache_Controller.WB_Ack::total 1687383 -system.ruby.L1Cache_Controller.NP.Load | 280457 20.44% 20.44% | 1091772 79.56% 100.00% -system.ruby.L1Cache_Controller.NP.Load::total 1372229 -system.ruby.L1Cache_Controller.NP.Ifetch | 323032 39.65% 39.65% | 491723 60.35% 100.00% -system.ruby.L1Cache_Controller.NP.Ifetch::total 814755 -system.ruby.L1Cache_Controller.NP.Store | 225423 53.48% 53.48% | 196076 46.52% 100.00% -system.ruby.L1Cache_Controller.NP.Store::total 421499 -system.ruby.L1Cache_Controller.NP.Inv | 4849 53.95% 53.95% | 4139 46.05% 100.00% -system.ruby.L1Cache_Controller.NP.Inv::total 8988 -system.ruby.L1Cache_Controller.I.Load | 8492 45.24% 45.24% | 10279 54.76% 100.00% -system.ruby.L1Cache_Controller.I.Load::total 18771 -system.ruby.L1Cache_Controller.I.Ifetch | 112 15.86% 15.86% | 594 84.14% 100.00% -system.ruby.L1Cache_Controller.I.Ifetch::total 706 -system.ruby.L1Cache_Controller.I.Store | 5744 50.09% 50.09% | 5723 49.91% 100.00% -system.ruby.L1Cache_Controller.I.Store::total 11467 -system.ruby.L1Cache_Controller.I.L1_Replacement | 9001 51.76% 51.76% | 8389 48.24% 100.00% -system.ruby.L1Cache_Controller.I.L1_Replacement::total 17390 -system.ruby.L1Cache_Controller.S.Load | 552961 51.86% 51.86% | 513218 48.14% 100.00% -system.ruby.L1Cache_Controller.S.Load::total 1066179 -system.ruby.L1Cache_Controller.S.Ifetch | 68582952 54.31% 54.31% | 57694694 45.69% 100.00% -system.ruby.L1Cache_Controller.S.Ifetch::total 126277646 -system.ruby.L1Cache_Controller.S.Store | 12149 54.85% 54.85% | 10001 45.15% 100.00% -system.ruby.L1Cache_Controller.S.Store::total 22150 -system.ruby.L1Cache_Controller.S.Inv | 10866 45.32% 45.32% | 13108 54.68% 100.00% -system.ruby.L1Cache_Controller.S.Inv::total 23974 -system.ruby.L1Cache_Controller.S.L1_Replacement | 349852 38.80% 38.80% | 551810 61.20% 100.00% -system.ruby.L1Cache_Controller.S.L1_Replacement::total 901662 -system.ruby.L1Cache_Controller.E.Load | 1151502 29.73% 29.73% | 2721068 70.27% 100.00% -system.ruby.L1Cache_Controller.E.Load::total 3872570 -system.ruby.L1Cache_Controller.E.Store | 80746 48.37% 48.37% | 86187 51.63% 100.00% -system.ruby.L1Cache_Controller.E.Store::total 166933 -system.ruby.L1Cache_Controller.E.Inv | 47 57.32% 57.32% | 35 42.68% 100.00% -system.ruby.L1Cache_Controller.E.Inv::total 82 -system.ruby.L1Cache_Controller.E.L1_Replacement | 170526 15.32% 15.32% | 942229 84.68% 100.00% -system.ruby.L1Cache_Controller.E.L1_Replacement::total 1112755 -system.ruby.L1Cache_Controller.E.Fwd_GETX | 332 72.81% 72.81% | 124 27.19% 100.00% -system.ruby.L1Cache_Controller.E.Fwd_GETX::total 456 -system.ruby.L1Cache_Controller.E.Fwd_GETS | 992 45.23% 45.23% | 1201 54.77% 100.00% -system.ruby.L1Cache_Controller.E.Fwd_GETS::total 2193 -system.ruby.L1Cache_Controller.M.Load | 4275313 49.21% 49.21% | 4412667 50.79% 100.00% -system.ruby.L1Cache_Controller.M.Load::total 8687980 -system.ruby.L1Cache_Controller.M.Store | 5040297 49.89% 49.89% | 5061906 50.11% 100.00% -system.ruby.L1Cache_Controller.M.Store::total 10102203 -system.ruby.L1Cache_Controller.M.Inv | 176 47.57% 47.57% | 194 52.43% 100.00% -system.ruby.L1Cache_Controller.M.Inv::total 370 -system.ruby.L1Cache_Controller.M.L1_Replacement | 298509 51.95% 51.95% | 276119 48.05% 100.00% -system.ruby.L1Cache_Controller.M.L1_Replacement::total 574628 -system.ruby.L1Cache_Controller.M.Fwd_GETX | 11928 50.67% 50.67% | 11614 49.33% 100.00% -system.ruby.L1Cache_Controller.M.Fwd_GETX::total 23542 -system.ruby.L1Cache_Controller.M.Fwd_GETS | 13177 57.06% 57.06% | 9917 42.94% 100.00% -system.ruby.L1Cache_Controller.M.Fwd_GETS::total 23094 +system.ruby.L1Cache_Controller.Data | 818 44.46% 44.46% | 1022 55.54% 100.00% +system.ruby.L1Cache_Controller.Data::total 1840 +system.ruby.L1Cache_Controller.Data_Exclusive | 252712 19.73% 19.73% | 1028027 80.27% 100.00% +system.ruby.L1Cache_Controller.Data_Exclusive::total 1280739 +system.ruby.L1Cache_Controller.DataS_fromL1 | 11346 44.32% 44.32% | 14255 55.68% 100.00% +system.ruby.L1Cache_Controller.DataS_fromL1::total 25601 +system.ruby.L1Cache_Controller.Data_all_Acks | 579316 43.50% 43.50% | 752306 56.50% 100.00% +system.ruby.L1Cache_Controller.Data_all_Acks::total 1331622 +system.ruby.L1Cache_Controller.Ack | 12225 54.44% 54.44% | 10230 45.56% 100.00% +system.ruby.L1Cache_Controller.Ack::total 22455 +system.ruby.L1Cache_Controller.Ack_all | 13043 53.69% 53.69% | 11252 46.31% 100.00% +system.ruby.L1Cache_Controller.Ack_all::total 24295 +system.ruby.L1Cache_Controller.WB_Ack | 468894 27.82% 27.82% | 1216556 72.18% 100.00% +system.ruby.L1Cache_Controller.WB_Ack::total 1685450 +system.ruby.L1Cache_Controller.NP.Load | 280382 20.44% 20.44% | 1091184 79.56% 100.00% +system.ruby.L1Cache_Controller.NP.Load::total 1371566 +system.ruby.L1Cache_Controller.NP.Ifetch | 323814 39.71% 39.71% | 491732 60.29% 100.00% +system.ruby.L1Cache_Controller.NP.Ifetch::total 815546 +system.ruby.L1Cache_Controller.NP.Store | 225433 53.48% 53.48% | 196079 46.52% 100.00% +system.ruby.L1Cache_Controller.NP.Store::total 421512 +system.ruby.L1Cache_Controller.NP.Inv | 4849 54.09% 54.09% | 4115 45.91% 100.00% +system.ruby.L1Cache_Controller.NP.Inv::total 8964 +system.ruby.L1Cache_Controller.I.Load | 8724 45.72% 45.72% | 10359 54.28% 100.00% +system.ruby.L1Cache_Controller.I.Load::total 19083 +system.ruby.L1Cache_Controller.I.Ifetch | 100 15.77% 15.77% | 534 84.23% 100.00% +system.ruby.L1Cache_Controller.I.Ifetch::total 634 +system.ruby.L1Cache_Controller.I.Store | 5739 50.07% 50.07% | 5722 49.93% 100.00% +system.ruby.L1Cache_Controller.I.Store::total 11461 +system.ruby.L1Cache_Controller.I.L1_Replacement | 8993 51.78% 51.78% | 8375 48.22% 100.00% +system.ruby.L1Cache_Controller.I.L1_Replacement::total 17368 +system.ruby.L1Cache_Controller.S.Load | 555624 51.88% 51.88% | 515377 48.12% 100.00% +system.ruby.L1Cache_Controller.S.Load::total 1071001 +system.ruby.L1Cache_Controller.S.Ifetch | 68488995 54.28% 54.28% | 57691140 45.72% 100.00% +system.ruby.L1Cache_Controller.S.Ifetch::total 126180135 +system.ruby.L1Cache_Controller.S.Store | 12225 54.44% 54.44% | 10230 45.56% 100.00% +system.ruby.L1Cache_Controller.S.Store::total 22455 +system.ruby.L1Cache_Controller.S.Inv | 11078 45.79% 45.79% | 13115 54.21% 100.00% +system.ruby.L1Cache_Controller.S.Inv::total 24193 +system.ruby.L1Cache_Controller.S.L1_Replacement | 350718 38.81% 38.81% | 553040 61.19% 100.00% +system.ruby.L1Cache_Controller.S.L1_Replacement::total 903758 +system.ruby.L1Cache_Controller.E.Load | 1152084 29.74% 29.74% | 2722150 70.26% 100.00% +system.ruby.L1Cache_Controller.E.Load::total 3874234 +system.ruby.L1Cache_Controller.E.Store | 80726 48.37% 48.37% | 86165 51.63% 100.00% +system.ruby.L1Cache_Controller.E.Store::total 166891 +system.ruby.L1Cache_Controller.E.Inv | 52 59.77% 59.77% | 35 40.23% 100.00% +system.ruby.L1Cache_Controller.E.Inv::total 87 +system.ruby.L1Cache_Controller.E.L1_Replacement | 170402 15.34% 15.34% | 940436 84.66% 100.00% +system.ruby.L1Cache_Controller.E.L1_Replacement::total 1110838 +system.ruby.L1Cache_Controller.E.Fwd_GETX | 330 72.53% 72.53% | 125 27.47% 100.00% +system.ruby.L1Cache_Controller.E.Fwd_GETX::total 455 +system.ruby.L1Cache_Controller.E.Fwd_GETS | 996 45.17% 45.17% | 1209 54.83% 100.00% +system.ruby.L1Cache_Controller.E.Fwd_GETS::total 2205 +system.ruby.L1Cache_Controller.M.Load | 4282503 49.27% 49.27% | 4409525 50.73% 100.00% +system.ruby.L1Cache_Controller.M.Load::total 8692028 +system.ruby.L1Cache_Controller.M.Store | 5048323 49.93% 49.93% | 5061721 50.07% 100.00% +system.ruby.L1Cache_Controller.M.Store::total 10110044 +system.ruby.L1Cache_Controller.M.Inv | 178 48.37% 48.37% | 190 51.63% 100.00% +system.ruby.L1Cache_Controller.M.Inv::total 368 +system.ruby.L1Cache_Controller.M.L1_Replacement | 298492 51.95% 51.95% | 276120 48.05% 100.00% +system.ruby.L1Cache_Controller.M.L1_Replacement::total 574612 +system.ruby.L1Cache_Controller.M.Fwd_GETX | 11918 50.65% 50.65% | 11611 49.35% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GETX::total 23529 +system.ruby.L1Cache_Controller.M.Fwd_GETS | 13255 56.66% 56.66% | 10137 43.34% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GETS::total 23392 system.ruby.L1Cache_Controller.M.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.M.Fwd_GET_INSTR::total 4 -system.ruby.L1Cache_Controller.IS.Data_Exclusive | 252860 19.71% 19.71% | 1029835 80.29% 100.00% -system.ruby.L1Cache_Controller.IS.Data_Exclusive::total 1282695 -system.ruby.L1Cache_Controller.IS.DataS_fromL1 | 11118 43.96% 43.96% | 14173 56.04% 100.00% -system.ruby.L1Cache_Controller.IS.DataS_fromL1::total 25291 -system.ruby.L1Cache_Controller.IS.Data_all_Acks | 348115 38.75% 38.75% | 550360 61.25% 100.00% -system.ruby.L1Cache_Controller.IS.Data_all_Acks::total 898475 -system.ruby.L1Cache_Controller.IM.Data | 828 44.64% 44.64% | 1027 55.36% 100.00% -system.ruby.L1Cache_Controller.IM.Data::total 1855 -system.ruby.L1Cache_Controller.IM.Data_all_Acks | 230339 53.43% 53.43% | 200772 46.57% 100.00% -system.ruby.L1Cache_Controller.IM.Data_all_Acks::total 431111 -system.ruby.L1Cache_Controller.SM.Ack | 12149 54.85% 54.85% | 10001 45.15% 100.00% -system.ruby.L1Cache_Controller.SM.Ack::total 22150 -system.ruby.L1Cache_Controller.SM.Ack_all | 12977 54.06% 54.06% | 11028 45.94% 100.00% -system.ruby.L1Cache_Controller.SM.Ack_all::total 24005 +system.ruby.L1Cache_Controller.IS.Data_Exclusive | 252712 19.73% 19.73% | 1028027 80.27% 100.00% +system.ruby.L1Cache_Controller.IS.Data_Exclusive::total 1280739 +system.ruby.L1Cache_Controller.IS.DataS_fromL1 | 11346 44.32% 44.32% | 14255 55.68% 100.00% +system.ruby.L1Cache_Controller.IS.DataS_fromL1::total 25601 +system.ruby.L1Cache_Controller.IS.Data_all_Acks | 348962 38.75% 38.75% | 551527 61.25% 100.00% +system.ruby.L1Cache_Controller.IS.Data_all_Acks::total 900489 +system.ruby.L1Cache_Controller.IM.Data | 818 44.46% 44.46% | 1022 55.54% 100.00% +system.ruby.L1Cache_Controller.IM.Data::total 1840 +system.ruby.L1Cache_Controller.IM.Data_all_Acks | 230354 53.43% 53.43% | 200779 46.57% 100.00% +system.ruby.L1Cache_Controller.IM.Data_all_Acks::total 431133 +system.ruby.L1Cache_Controller.SM.Ack | 12225 54.44% 54.44% | 10230 45.56% 100.00% +system.ruby.L1Cache_Controller.SM.Ack::total 22455 +system.ruby.L1Cache_Controller.SM.Ack_all | 13043 53.69% 53.69% | 11252 46.31% 100.00% +system.ruby.L1Cache_Controller.SM.Ack_all::total 24295 system.ruby.L1Cache_Controller.M_I.Ifetch | 5 83.33% 83.33% | 1 16.67% 100.00% system.ruby.L1Cache_Controller.M_I.Ifetch::total 6 -system.ruby.L1Cache_Controller.M_I.WB_Ack | 469035 27.80% 27.80% | 1218348 72.20% 100.00% -system.ruby.L1Cache_Controller.M_I.WB_Ack::total 1687383 -system.ruby.L2Cache_Controller.L1_GET_INSTR 815461 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETS 1391156 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETX 432966 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_UPGRADE 22150 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX 1687383 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement 95998 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement_clean 15348 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Data 177916 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Ack 113143 0.00% 0.00% -system.ruby.L2Cache_Controller.WB_Data 23468 0.00% 0.00% -system.ruby.L2Cache_Controller.WB_Data_clean 2193 0.00% 0.00% -system.ruby.L2Cache_Controller.Ack 1505 0.00% 0.00% -system.ruby.L2Cache_Controller.Ack_all 7534 0.00% 0.00% -system.ruby.L2Cache_Controller.Unblock 25291 0.00% 0.00% -system.ruby.L2Cache_Controller.Exclusive_Unblock 1737811 0.00% 0.00% -system.ruby.L2Cache_Controller.MEM_Inv 3594 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 16427 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 34220 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETX 127269 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GET_INSTR 799004 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETS 83018 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETX 1958 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_UPGRADE 22150 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L2_Replacement 257 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 7192 0.00% 0.00% +system.ruby.L1Cache_Controller.M_I.WB_Ack | 468894 27.82% 27.82% | 1216556 72.18% 100.00% +system.ruby.L1Cache_Controller.M_I.WB_Ack::total 1685450 +system.ruby.L2Cache_Controller.L1_GET_INSTR 816180 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETS 1390821 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETX 432975 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_UPGRADE 22455 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTX 1685450 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement 95536 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement_clean 15120 0.00% 0.00% +system.ruby.L2Cache_Controller.Mem_Data 177212 0.00% 0.00% +system.ruby.L2Cache_Controller.Mem_Ack 112431 0.00% 0.00% +system.ruby.L2Cache_Controller.WB_Data 23764 0.00% 0.00% +system.ruby.L2Cache_Controller.WB_Data_clean 2205 0.00% 0.00% +system.ruby.L2Cache_Controller.Ack 1487 0.00% 0.00% +system.ruby.L2Cache_Controller.Ack_all 7462 0.00% 0.00% +system.ruby.L2Cache_Controller.Unblock 25601 0.00% 0.00% +system.ruby.L2Cache_Controller.Exclusive_Unblock 1736167 0.00% 0.00% +system.ruby.L2Cache_Controller.MEM_Inv 3550 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 16316 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETS 33914 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETX 126982 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GET_INSTR 799834 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETS 84313 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETX 1944 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_UPGRADE 22455 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L2_Replacement 252 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 7120 0.00% 0.00% system.ruby.L2Cache_Controller.SS.MEM_Inv 3 0.00% 0.00% system.ruby.L2Cache_Controller.M.L1_GET_INSTR 26 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETS 1248475 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETX 279741 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement 95619 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement_clean 8056 0.00% 0.00% -system.ruby.L2Cache_Controller.M.MEM_Inv 1564 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETS 1246825 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETX 280063 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement 95163 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement_clean 7896 0.00% 0.00% +system.ruby.L2Cache_Controller.M.MEM_Inv 1542 0.00% 0.00% system.ruby.L2Cache_Controller.MT.L1_GET_INSTR 4 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_GETS 25287 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_GETX 23998 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_PUTX 1687383 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L2_Replacement 122 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 100 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_GETS 25597 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_GETX 23984 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_PUTX 1685450 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L2_Replacement 121 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 104 0.00% 0.00% system.ruby.L2Cache_Controller.MT.MEM_Inv 230 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.Mem_Ack 113143 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.MEM_Inv 1564 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_I.WB_Data 310 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_I.Ack_all 42 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.Mem_Ack 112431 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.MEM_Inv 1542 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_I.WB_Data 308 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_I.Ack_all 43 0.00% 0.00% system.ruby.L2Cache_Controller.MT_I.MEM_Inv 230 0.00% 0.00% system.ruby.L2Cache_Controller.MCT_I.WB_Data 60 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.Ack_all 40 0.00% 0.00% -system.ruby.L2Cache_Controller.I_I.Ack 1245 0.00% 0.00% -system.ruby.L2Cache_Controller.I_I.Ack_all 7192 0.00% 0.00% -system.ruby.L2Cache_Controller.S_I.Ack 260 0.00% 0.00% -system.ruby.L2Cache_Controller.S_I.Ack_all 260 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.Ack_all 44 0.00% 0.00% +system.ruby.L2Cache_Controller.I_I.Ack 1232 0.00% 0.00% +system.ruby.L2Cache_Controller.I_I.Ack_all 7120 0.00% 0.00% +system.ruby.L2Cache_Controller.S_I.Ack 255 0.00% 0.00% +system.ruby.L2Cache_Controller.S_I.Ack_all 255 0.00% 0.00% system.ruby.L2Cache_Controller.S_I.MEM_Inv 3 0.00% 0.00% -system.ruby.L2Cache_Controller.ISS.Mem_Data 34220 0.00% 0.00% -system.ruby.L2Cache_Controller.IS.Mem_Data 16427 0.00% 0.00% -system.ruby.L2Cache_Controller.IM.Mem_Data 127269 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.L1_GETS 115 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 24108 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.L1_GETS 41 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 1713703 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.WB_Data 23085 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 2191 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.Unblock 15 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IB.WB_Data 13 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IB.WB_Data_clean 2 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_SB.Unblock 25276 0.00% 0.00% +system.ruby.L2Cache_Controller.ISS.Mem_Data 33914 0.00% 0.00% +system.ruby.L2Cache_Controller.IS.Mem_Data 16316 0.00% 0.00% +system.ruby.L2Cache_Controller.IM.Mem_Data 126982 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.L1_GETS 122 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 24399 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L1_GETS 50 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L1_GETX 2 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 1711768 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.WB_Data 23385 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 2205 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.Unblock 11 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IB.WB_Data 11 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_SB.Unblock 25590 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index 81562c0f3..99542453a 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -1,157 +1,157 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.133731 # Number of seconds simulated -sim_ticks 5133731116500 # Number of ticks simulated -final_tick 5133731116500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.134211 # Number of seconds simulated +sim_ticks 5134211428000 # Number of ticks simulated +final_tick 5134211428000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 268887 # Simulator instruction rate (inst/s) -host_op_rate 534560 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5655392824 # Simulator tick rate (ticks/s) -host_mem_usage 1025452 # Number of bytes of host memory used -host_seconds 907.76 # Real time elapsed on the host -sim_insts 244084329 # Number of instructions simulated -sim_ops 485251122 # Number of ops (including micro ops) simulated +host_inst_rate 263536 # Simulator instruction rate (inst/s) +host_op_rate 523907 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5540037627 # Simulator tick rate (ticks/s) +host_mem_usage 1021876 # Number of bytes of host memory used +host_seconds 926.75 # Real time elapsed on the host +sim_insts 244230745 # Number of instructions simulated +sim_ops 485529516 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 445760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5319424 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 180800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1995776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 2240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 334336 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 3134080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 393536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5140544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 149632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1859072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 2496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 422208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 3469952 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 11441152 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 445760 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 180800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 334336 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 960896 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9198080 # Number of bytes written to this memory -system.physmem.bytes_written::total 9198080 # Number of bytes written to this memory +system.physmem.bytes_read::total 11466176 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 393536 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 149632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 422208 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 965376 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9230336 # Number of bytes written to this memory +system.physmem.bytes_written::total 9230336 # Number of bytes written to this memory system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6965 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 83116 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2825 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 31184 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 35 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 5224 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 48970 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6149 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 80321 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2338 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 29048 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 39 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 6597 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 54218 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 178768 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 143720 # Number of write requests responded to by this memory -system.physmem.num_writes::total 143720 # Number of write requests responded to by this memory +system.physmem.num_reads::total 179159 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 144224 # Number of write requests responded to by this memory +system.physmem.num_writes::total 144224 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 86830 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1036171 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 12 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 35218 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 388757 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 436 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 65125 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 610488 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::pc.south_bridge.ide 5523 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2228623 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 86830 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 35218 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 65125 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 187173 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1791695 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1791695 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1791695 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 76650 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1001233 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 29144 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 362095 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 486 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.itb.walker 12 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 82234 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 675849 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5522 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2233289 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 76650 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 29144 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 82234 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 188028 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1797810 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1797810 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1797810 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 86830 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1036171 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 35218 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 388757 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 436 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 65125 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 610488 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 5523 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4020318 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 88682 # Number of read requests accepted -system.physmem.writeReqs 112966 # Number of write requests accepted -system.physmem.readBursts 88682 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 112966 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5672000 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 3648 # Total number of bytes read from write queue -system.physmem.bytesWritten 6262656 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5675648 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7229824 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 57 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 15112 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 1053 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 5542 # Per bank write bursts -system.physmem.perBankRdBursts::1 5155 # Per bank write bursts -system.physmem.perBankRdBursts::2 5253 # Per bank write bursts -system.physmem.perBankRdBursts::3 5290 # Per bank write bursts -system.physmem.perBankRdBursts::4 5356 # Per bank write bursts -system.physmem.perBankRdBursts::5 4920 # Per bank write bursts -system.physmem.perBankRdBursts::6 5387 # Per bank write bursts -system.physmem.perBankRdBursts::7 5003 # Per bank write bursts -system.physmem.perBankRdBursts::8 5335 # Per bank write bursts -system.physmem.perBankRdBursts::9 5304 # Per bank write bursts -system.physmem.perBankRdBursts::10 5486 # Per bank write bursts -system.physmem.perBankRdBursts::11 5354 # Per bank write bursts -system.physmem.perBankRdBursts::12 5802 # Per bank write bursts -system.physmem.perBankRdBursts::13 6837 # Per bank write bursts -system.physmem.perBankRdBursts::14 6164 # Per bank write bursts -system.physmem.perBankRdBursts::15 6437 # Per bank write bursts -system.physmem.perBankWrBursts::0 6158 # Per bank write bursts -system.physmem.perBankWrBursts::1 6179 # Per bank write bursts -system.physmem.perBankWrBursts::2 6254 # Per bank write bursts -system.physmem.perBankWrBursts::3 6080 # Per bank write bursts -system.physmem.perBankWrBursts::4 5432 # Per bank write bursts -system.physmem.perBankWrBursts::5 5660 # Per bank write bursts -system.physmem.perBankWrBursts::6 6180 # Per bank write bursts -system.physmem.perBankWrBursts::7 5898 # Per bank write bursts -system.physmem.perBankWrBursts::8 5226 # Per bank write bursts -system.physmem.perBankWrBursts::9 5788 # Per bank write bursts -system.physmem.perBankWrBursts::10 6663 # Per bank write bursts -system.physmem.perBankWrBursts::11 6618 # Per bank write bursts -system.physmem.perBankWrBursts::12 6477 # Per bank write bursts -system.physmem.perBankWrBursts::13 6666 # Per bank write bursts -system.physmem.perBankWrBursts::14 5929 # Per bank write bursts -system.physmem.perBankWrBursts::15 6646 # Per bank write bursts +system.physmem.bw_total::cpu0.inst 76650 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1001233 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 29144 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 362095 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 486 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.itb.walker 12 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 82234 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 675849 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 5522 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4031099 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 92684 # Number of read requests accepted +system.physmem.writeReqs 79104 # Number of write requests accepted +system.physmem.readBursts 92684 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 79104 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5924224 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7552 # Total number of bytes read from write queue +system.physmem.bytesWritten 5060672 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5931776 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5062656 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 118 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 20933 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 6439 # Per bank write bursts +system.physmem.perBankRdBursts::1 5501 # Per bank write bursts +system.physmem.perBankRdBursts::2 5319 # Per bank write bursts +system.physmem.perBankRdBursts::3 5591 # Per bank write bursts +system.physmem.perBankRdBursts::4 5862 # Per bank write bursts +system.physmem.perBankRdBursts::5 5383 # Per bank write bursts +system.physmem.perBankRdBursts::6 5425 # Per bank write bursts +system.physmem.perBankRdBursts::7 4840 # Per bank write bursts +system.physmem.perBankRdBursts::8 6025 # Per bank write bursts +system.physmem.perBankRdBursts::9 5959 # Per bank write bursts +system.physmem.perBankRdBursts::10 5660 # Per bank write bursts +system.physmem.perBankRdBursts::11 5754 # Per bank write bursts +system.physmem.perBankRdBursts::12 5715 # Per bank write bursts +system.physmem.perBankRdBursts::13 6523 # Per bank write bursts +system.physmem.perBankRdBursts::14 5966 # Per bank write bursts +system.physmem.perBankRdBursts::15 6604 # Per bank write bursts +system.physmem.perBankWrBursts::0 5842 # Per bank write bursts +system.physmem.perBankWrBursts::1 5111 # Per bank write bursts +system.physmem.perBankWrBursts::2 4865 # Per bank write bursts +system.physmem.perBankWrBursts::3 5025 # Per bank write bursts +system.physmem.perBankWrBursts::4 5489 # Per bank write bursts +system.physmem.perBankWrBursts::5 4924 # Per bank write bursts +system.physmem.perBankWrBursts::6 4816 # Per bank write bursts +system.physmem.perBankWrBursts::7 4154 # Per bank write bursts +system.physmem.perBankWrBursts::8 4431 # Per bank write bursts +system.physmem.perBankWrBursts::9 4666 # Per bank write bursts +system.physmem.perBankWrBursts::10 4446 # Per bank write bursts +system.physmem.perBankWrBursts::11 4728 # Per bank write bursts +system.physmem.perBankWrBursts::12 4725 # Per bank write bursts +system.physmem.perBankWrBursts::13 5504 # Per bank write bursts +system.physmem.perBankWrBursts::14 4686 # Per bank write bursts +system.physmem.perBankWrBursts::15 5661 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 21 # Number of times write queue was full causing retry -system.physmem.totGap 5132592336000 # Total gap between requests +system.physmem.numWrRetry 3 # Number of times write queue was full causing retry +system.physmem.totGap 5133211221000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 88682 # Read request sizes (log2) +system.physmem.readPktSize::6 92684 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 112966 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 81919 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 5154 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1007 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 209 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 47 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 40 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 32 # What read queue length does an incoming req see +system.physmem.writePktSize::6 79104 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 86281 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4975 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 810 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 180 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 46 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 35 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 30 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 26 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 23 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 23 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -165,986 +165,984 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 124 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 52 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1363 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3421 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3754 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4080 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4535 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5377 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6323 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4558 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4427 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 749 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 961 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1599 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1755 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1575 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1912 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1553 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1565 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 976 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 485 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 22 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 40590 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 294.012121 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 173.528709 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 319.654231 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15917 39.21% 39.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 9832 24.22% 63.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4000 9.85% 73.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2295 5.65% 78.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1624 4.00% 82.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1126 2.77% 85.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 717 1.77% 87.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 617 1.52% 89.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4462 10.99% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 40590 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 3784 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.420983 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 192.521538 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 3781 99.92% 99.92% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1535 1 0.03% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::6144-6655 1 0.03% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::9728-10239 1 0.03% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 3784 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 3784 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 25.859937 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.216089 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 44.163335 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-15 82 2.17% 2.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 3425 90.51% 92.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 68 1.80% 94.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 12 0.32% 94.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 7 0.18% 94.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 15 0.40% 95.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 10 0.26% 95.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 22 0.58% 96.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 22 0.58% 96.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 17 0.45% 97.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 6 0.16% 97.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 22 0.58% 97.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 36 0.95% 98.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 7 0.18% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 2 0.05% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 3 0.08% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 1 0.03% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 1 0.03% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 5 0.13% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 4 0.11% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 6 0.16% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 5 0.13% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 1 0.03% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 1 0.03% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 1 0.03% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 1 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::560-575 1 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::576-591 1 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 3784 # Writes before turning the bus around for reads -system.physmem.totQLat 1019929900 # Total ticks spent queuing -system.physmem.totMemAccLat 2681648650 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 443125000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11508.38 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::8 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1628 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4925 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5092 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5826 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5070 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4491 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4712 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4886 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 9 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 40692 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 269.949081 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 163.456020 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 296.352111 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 16538 40.64% 40.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10119 24.87% 65.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4173 10.26% 75.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2507 6.16% 81.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1551 3.81% 85.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1073 2.64% 88.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 750 1.84% 90.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 656 1.61% 91.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3325 8.17% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 40692 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4120 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.462136 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 184.101810 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 4117 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1535 1 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::6144-6655 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::9728-10239 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4120 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4120 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.192476 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.355155 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 11.050068 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 67 1.63% 1.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 6 0.15% 1.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 4 0.10% 1.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 3537 85.85% 87.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 61 1.48% 89.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 102 2.48% 91.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 51 1.24% 92.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 38 0.92% 93.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 95 2.31% 96.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 16 0.39% 96.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 6 0.15% 96.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 9 0.22% 96.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 2 0.05% 96.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 2 0.05% 96.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.05% 97.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 98 2.38% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 2 0.05% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 5 0.12% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 2 0.05% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.05% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 3 0.07% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.02% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 6 0.15% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4120 # Writes before turning the bus around for reads +system.physmem.totQLat 1055441928 # Total ticks spent queuing +system.physmem.totMemAccLat 2791054428 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 462830000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11402.05 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30258.38 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.10 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.22 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.11 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.41 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30152.05 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.15 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.99 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.16 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.99 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 11.85 # Average write queue length when enqueuing -system.physmem.readRowHits 70792 # Number of row buffer hits during reads -system.physmem.writeRowHits 75088 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.88 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 76.73 # Row buffer hit rate for writes -system.physmem.avgGap 25453227.09 # Average gap between requests -system.physmem.pageHitRate 78.23 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 147351960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 80169375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 326866800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 309938400 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 250042678080 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 94629197520 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2236697889750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 2582234091885 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.903813 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 3683333970938 # Time in different power states -system.physmem_0.memoryStateTime::REF 127833680000 # Time in different power states +system.physmem.avgRdQLen 1.11 # Average read queue length when enqueuing +system.physmem.avgWrQLen 9.29 # Average write queue length when enqueuing +system.physmem.readRowHits 74063 # Number of row buffer hits during reads +system.physmem.writeRowHits 56883 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.01 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 71.91 # Row buffer hit rate for writes +system.physmem.avgGap 29881081.46 # Average gap between requests +system.physmem.pageHitRate 76.28 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 149294880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 81184125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 345992400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 260664480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 250017250080 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 94809930840 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2241062736000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 2586727052805 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.763806 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 3682666821734 # Time in different power states +system.physmem_0.memoryStateTime::REF 127820680000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 17533181312 # Time in different power states +system.physmem_0.memoryStateTime::ACT 17822753766 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 159410160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 86781750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 364408200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 323974080 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 250042678080 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 95188577850 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2235010334250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 2581176164370 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.974824 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 3682508953468 # Time in different power states -system.physmem_1.memoryStateTime::REF 127833680000 # Time in different power states +system.physmem_1.actEnergy 158336640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 86183625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 376006800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 251728560 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 250017250080 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 95265143955 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2233496235000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 2579650884660 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.996985 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 3682005807728 # Time in different power states +system.physmem_1.memoryStateTime::REF 127820680000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 18355082532 # Time in different power states +system.physmem_1.memoryStateTime::ACT 18463901522 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.numCycles 819384850 # number of cpu cycles simulated +system.cpu0.numCycles 814812843 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 70809878 # Number of instructions committed -system.cpu0.committedOps 144569383 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 132504639 # Number of integer alu accesses +system.cpu0.committedInsts 70855773 # Number of instructions committed +system.cpu0.committedOps 144639705 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 132581707 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 914830 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14060186 # number of instructions that are conditional controls -system.cpu0.num_int_insts 132504639 # number of integer instructions +system.cpu0.num_func_calls 911803 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14069363 # number of instructions that are conditional controls +system.cpu0.num_int_insts 132581707 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 242769596 # number of times the integer registers were read -system.cpu0.num_int_register_writes 113987635 # number of times the integer registers were written +system.cpu0.num_int_register_reads 242934374 # number of times the integer registers were read +system.cpu0.num_int_register_writes 114063964 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 82531896 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 55153606 # number of times the CC registers were written -system.cpu0.num_mem_refs 13358556 # number of memory refs -system.cpu0.num_load_insts 9930193 # Number of load instructions -system.cpu0.num_store_insts 3428363 # Number of store instructions -system.cpu0.num_idle_cycles 778171794.138464 # Number of idle cycles -system.cpu0.num_busy_cycles 41213055.861536 # Number of busy cycles -system.cpu0.not_idle_fraction 0.050298 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.949702 # Percentage of idle cycles -system.cpu0.Branches 15315720 # Number of branches fetched -system.cpu0.op_class::No_OpClass 88912 0.06% 0.06% # Class of executed instruction -system.cpu0.op_class::IntAlu 131019698 90.63% 90.69% # Class of executed instruction -system.cpu0.op_class::IntMult 57722 0.04% 90.73% # Class of executed instruction -system.cpu0.op_class::IntDiv 46561 0.03% 90.76% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::MemRead 9928558 6.87% 97.63% # Class of executed instruction -system.cpu0.op_class::MemWrite 3428363 2.37% 100.00% # Class of executed instruction +system.cpu0.num_cc_register_reads 82574901 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 55200628 # number of times the CC registers were written +system.cpu0.num_mem_refs 13389972 # number of memory refs +system.cpu0.num_load_insts 9966183 # Number of load instructions +system.cpu0.num_store_insts 3423789 # Number of store instructions +system.cpu0.num_idle_cycles 774643417.179050 # Number of idle cycles +system.cpu0.num_busy_cycles 40169425.820950 # Number of busy cycles +system.cpu0.not_idle_fraction 0.049299 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.950701 # Percentage of idle cycles +system.cpu0.Branches 15322983 # Number of branches fetched +system.cpu0.op_class::No_OpClass 87668 0.06% 0.06% # Class of executed instruction +system.cpu0.op_class::IntAlu 131058913 90.61% 90.67% # Class of executed instruction +system.cpu0.op_class::IntMult 57724 0.04% 90.71% # Class of executed instruction +system.cpu0.op_class::IntDiv 47555 0.03% 90.74% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::MemRead 9964546 6.89% 97.63% # Class of executed instruction +system.cpu0.op_class::MemWrite 3423789 2.37% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 144569814 # Class of executed instruction +system.cpu0.op_class::total 144640195 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 1636339 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.999246 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 19643358 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1636851 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 12.000700 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 1639692 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.999446 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 19677629 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1640204 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 11.997062 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 232.510577 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 255.541861 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 23.946808 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.454122 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.499105 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.046771 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 231.527826 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 256.098734 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 24.372886 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.452203 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.500193 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.047603 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 238 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 163 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 88441515 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 88441515 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 4745925 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 2412981 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4334563 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 11493469 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3299103 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1688891 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 3099986 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 8087980 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 19676 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 9874 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 30514 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 60064 # number of SoftPFReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8045028 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 4101872 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 7434549 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 19581449 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8064704 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 4111746 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 7465063 # number of overall hits -system.cpu0.dcache.overall_hits::total 19641513 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 345343 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 160729 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 822143 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1328215 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 125592 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 64251 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 135437 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 325280 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 145872 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 63796 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu2.data 196481 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 406149 # number of SoftPFReq misses -system.cpu0.dcache.demand_misses::cpu0.data 470935 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 224980 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 957580 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1653495 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 616807 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 288776 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1154061 # number of overall misses -system.cpu0.dcache.overall_misses::total 2059644 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2230470250 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 12318599402 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 14549069652 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2662717793 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 4381161307 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 7043879100 # number of WriteReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 4893188043 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 16699760709 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 21592948752 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 4893188043 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 16699760709 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 21592948752 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 5091268 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 2573710 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 5156706 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 12821684 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3424695 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1753142 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 3235423 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 8413260 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 165548 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 73670 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 226995 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 466213 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 8515963 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 4326852 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 8392129 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 21234944 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 8681511 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 4400522 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 8619124 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 21701157 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.067830 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.062450 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.159432 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.103591 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.036672 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.036649 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.041861 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.038663 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.881146 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.865970 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.865574 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.871166 # miss rate for SoftPFReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.055300 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.051996 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.114105 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.077867 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.071048 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.065623 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.133895 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.094909 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13877.211020 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14983.524037 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 10953.851336 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 41442.433472 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32348.333963 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 21654.817696 # average WriteReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21749.435697 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17439.546261 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 13058.974325 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16944.580031 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 14470.431553 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 10483.825725 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 172709 # number of cycles access was blocked +system.cpu0.dcache.tags.tag_accesses 88605943 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 88605943 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 4782117 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 2413671 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 4330956 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 11526744 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3296356 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 1699008 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 3093469 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 8088833 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 19899 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 9911 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu2.data 30439 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 60249 # number of SoftPFReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8078473 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 4112679 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 7424425 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 19615577 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8098372 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 4122590 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 7454864 # number of overall hits +system.cpu0.dcache.overall_hits::total 19675826 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 346307 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 159141 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 827752 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1333200 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 123952 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 63357 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 139093 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 326402 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 144703 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 63873 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu2.data 197428 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 406004 # number of SoftPFReq misses +system.cpu0.dcache.demand_misses::cpu0.data 470259 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 222498 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 966845 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1659602 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 614962 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 286371 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 1164273 # number of overall misses +system.cpu0.dcache.overall_misses::total 2065606 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2189850500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 12100176000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 14290026500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2530090000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 4783086364 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 7313176364 # number of WriteReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 4719940500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 16883262364 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 21603202864 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 4719940500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 16883262364 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 21603202864 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 5128424 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 2572812 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 5158708 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 12859944 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 3420308 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 1762365 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 3232562 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 8415235 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 164602 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 73784 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 227867 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 466253 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 8548732 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 4335177 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 8391270 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 21275179 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 8713334 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 4408961 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 8619137 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 21741432 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.067527 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.061855 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.160457 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.103671 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.036240 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.035950 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.043029 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.038787 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.879108 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.865675 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.866418 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.870780 # miss rate for SoftPFReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.055009 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.051324 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.115220 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.078006 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.070577 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.064952 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.135080 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.095008 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13760.441998 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14618.117504 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 10718.591734 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 39933.866818 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 34387.685678 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 22405.427553 # average WriteReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21213.406413 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17462.222346 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 13017.098596 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16481.908084 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 14501.119895 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 10458.530264 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 191338 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 19385 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 22795 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8.909414 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8.393858 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 1546428 # number of writebacks -system.cpu0.dcache.writebacks::total 1546428 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 54 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 384012 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 384066 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1567 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 32068 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 33635 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 1621 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 416080 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 417701 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 1621 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 416080 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 417701 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 160675 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 438131 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 598806 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 62684 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 103369 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 166053 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 63795 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 193085 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 256880 # number of SoftPFReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 223359 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 541500 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 764859 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 287154 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 734585 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1021739 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 186614 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 205311 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 391925 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 3448 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 3872 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 7320 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 190062 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 209183 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 399245 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1988518250 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 5713340764 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7701859014 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2470174689 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3635352900 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6105527589 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 932249000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 2770809752 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 3703058752 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4458692939 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 9348693664 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 13807386603 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 5390941939 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 12119503416 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 17510445355 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30496812500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33031149000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63527961500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 600115500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 761942500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1362058000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31096928000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33793091500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 64890019500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.062429 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.084963 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.046703 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.035755 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.031949 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019737 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.865956 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.850613 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.550993 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.051622 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.064525 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.036019 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.065255 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.085227 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.047082 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12376.027696 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13040.256827 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12862.027124 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39406.781459 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 35168.695644 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36768.547325 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14613.198527 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14350.207173 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14415.519900 # average SoftPFReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 19962.002601 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17264.438899 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18052.198644 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18773.696132 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16498.435737 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17137.884876 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163421.889569 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 160883.484080 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162092.138802 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 174047.418794 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 196782.670455 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 186073.497268 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 163614.652061 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 161547.981911 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 162531.827575 # average overall mshr uncacheable latency +system.cpu0.dcache.writebacks::writebacks 1548927 # number of writebacks +system.cpu0.dcache.writebacks::total 1548927 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 51 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 386553 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 386604 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1542 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 32157 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 33699 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1593 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 418710 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 420303 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1593 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 418710 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 420303 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 159090 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 441199 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 600289 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 61815 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 106936 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 168751 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 63873 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 194014 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 257887 # number of SoftPFReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 220905 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 548135 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 769040 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 284778 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 742149 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1026927 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 185834 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 205183 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 391017 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 3059 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 4433 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 7492 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 188893 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 209616 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 398509 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2030358500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 5964591000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7994949500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2384524000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 4092527864 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6477051864 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 931095000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 2819292000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 3750387000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4414882500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 10057118864 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 14472001364 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 5345977500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 12876410864 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 18222388364 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30572400500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33247121500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63819522000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 547435500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 878869500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1426305000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31119836000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 34125991000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65245827000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.061835 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.085525 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.046679 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.035075 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.033081 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.020053 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.865675 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.851435 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.553105 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.050956 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.065322 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.036147 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.064591 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.086105 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.047234 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12762.326356 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13519.049227 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13318.500755 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38575.167840 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 38270.814917 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38382.302114 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14577.286177 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14531.384333 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14542.753221 # average SoftPFReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 19985.434915 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18347.886678 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18818.268704 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18772.438531 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17350.169392 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17744.580057 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164514.569454 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 162036.433330 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 163214.187618 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178958.973521 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 198256.147079 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 190377.068873 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 164748.487239 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 162802.414892 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 163724.851885 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 871419 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.241344 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 127964014 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 871931 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 146.759335 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 150504235000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 260.667168 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 143.237667 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 106.336510 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.509116 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.279761 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.207688 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.996565 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 881776 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.250144 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 127955824 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 882288 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 145.027275 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 149037485500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 260.904392 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 141.200601 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 108.145151 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.509579 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.275782 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.211221 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.996582 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 303 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 285 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 129734477 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 129734477 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 86118928 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 38597787 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 3247299 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 127964014 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 86118928 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 38597787 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 3247299 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 127964014 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 86118928 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 38597787 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 3247299 # number of overall hits -system.cpu0.icache.overall_hits::total 127964014 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 294029 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 171033 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 433450 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 898512 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 294029 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 171033 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 433450 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 898512 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 294029 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 171033 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 433450 # number of overall misses -system.cpu0.icache.overall_misses::total 898512 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2424026997 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5943573307 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 8367600304 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 2424026997 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 5943573307 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 8367600304 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 2424026997 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 5943573307 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 8367600304 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 86412957 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 38768820 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 3680749 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 128862526 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 86412957 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 38768820 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 3680749 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 128862526 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 86412957 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 38768820 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 3680749 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 128862526 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003403 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004412 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.117761 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.006973 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003403 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004412 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.117761 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.006973 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003403 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004412 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.117761 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.006973 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14172.861360 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13712.246642 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9312.730719 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14172.861360 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13712.246642 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9312.730719 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14172.861360 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13712.246642 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9312.730719 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 7161 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 313 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 22.878594 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.tags.tag_accesses 129749175 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 129749175 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 86200122 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 38494727 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 3260975 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 127955824 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 86200122 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 38494727 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 3260975 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 127955824 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 86200122 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 38494727 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 3260975 # number of overall hits +system.cpu0.icache.overall_hits::total 127955824 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 293889 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 163550 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 453609 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 911048 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 293889 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 163550 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 453609 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 911048 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 293889 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 163550 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 453609 # number of overall misses +system.cpu0.icache.overall_misses::total 911048 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2290465000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 6298842980 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 8589307980 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 2290465000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 6298842980 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 8589307980 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 2290465000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 6298842980 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 8589307980 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 86494011 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 38658277 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 3714584 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 128866872 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 86494011 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 38658277 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 3714584 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 128866872 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 86494011 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 38658277 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 3714584 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 128866872 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003398 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004231 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122116 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.007070 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003398 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004231 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122116 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.007070 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003398 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004231 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122116 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.007070 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14004.677469 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13886.062622 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9427.942304 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14004.677469 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13886.062622 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9427.942304 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14004.677469 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13886.062622 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9427.942304 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 6492 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 22 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 290 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 22.386207 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 22 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 26561 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 26561 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 26561 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 26561 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 26561 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 26561 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 171033 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 406889 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 577922 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 171033 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 406889 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 577922 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 171033 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 406889 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 577922 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2166425503 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 5084799831 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 7251225334 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2166425503 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 5084799831 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 7251225334 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2166425503 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 5084799831 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 7251225334 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004412 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.110545 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004485 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004412 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.110545 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.004485 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004412 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.110545 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.004485 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12666.710535 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12496.773889 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12547.065753 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12666.710535 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12496.773889 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12547.065753 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12666.710535 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12496.773889 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12547.065753 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 28745 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 28745 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 28745 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 28745 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 28745 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 28745 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 163550 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 424864 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 588414 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 163550 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 424864 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 588414 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 163550 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 424864 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 588414 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2126915000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 5601122480 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 7728037480 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2126915000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 5601122480 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 7728037480 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2126915000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 5601122480 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 7728037480 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004231 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.114377 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004566 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004231 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.114377 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.004566 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004231 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.114377 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.004566 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13004.677469 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13183.330383 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13133.673706 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13004.677469 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13183.330383 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13133.673706 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13004.677469 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13183.330383 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13133.673706 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 2604016269 # number of cpu cycles simulated +system.cpu1.numCycles 2606017483 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 35221864 # Number of instructions committed -system.cpu1.committedOps 68477973 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 63543554 # Number of integer alu accesses +system.cpu1.committedInsts 35137560 # Number of instructions committed +system.cpu1.committedOps 68325691 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 63404843 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 474559 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 6488284 # number of instructions that are conditional controls -system.cpu1.num_int_insts 63543554 # number of integer instructions +system.cpu1.num_func_calls 475454 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 6463819 # number of instructions that are conditional controls +system.cpu1.num_int_insts 63404843 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 117503426 # number of times the integer registers were read -system.cpu1.num_int_register_writes 54764358 # number of times the integer registers were written +system.cpu1.num_int_register_reads 117292769 # number of times the integer registers were read +system.cpu1.num_int_register_writes 54636862 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 35994299 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 26824776 # number of times the CC registers were written -system.cpu1.num_mem_refs 4585615 # number of memory refs -system.cpu1.num_load_insts 2831531 # Number of load instructions -system.cpu1.num_store_insts 1754084 # Number of store instructions -system.cpu1.num_idle_cycles 2478252415.347472 # Number of idle cycles -system.cpu1.num_busy_cycles 125763853.652528 # Number of busy cycles -system.cpu1.not_idle_fraction 0.048296 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.951704 # Percentage of idle cycles -system.cpu1.Branches 7131846 # Number of branches fetched -system.cpu1.op_class::No_OpClass 33642 0.05% 0.05% # Class of executed instruction -system.cpu1.op_class::IntAlu 63809884 93.18% 93.23% # Class of executed instruction -system.cpu1.op_class::IntMult 28068 0.04% 93.27% # Class of executed instruction -system.cpu1.op_class::IntDiv 22761 0.03% 93.31% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::MemRead 2829816 4.13% 97.44% # Class of executed instruction -system.cpu1.op_class::MemWrite 1754084 2.56% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 35859650 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 26723526 # number of times the CC registers were written +system.cpu1.num_mem_refs 4592942 # number of memory refs +system.cpu1.num_load_insts 2829969 # Number of load instructions +system.cpu1.num_store_insts 1762973 # Number of store instructions +system.cpu1.num_idle_cycles 2483716878.762911 # Number of idle cycles +system.cpu1.num_busy_cycles 122300604.237089 # Number of busy cycles +system.cpu1.not_idle_fraction 0.046930 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.953070 # Percentage of idle cycles +system.cpu1.Branches 7109683 # Number of branches fetched +system.cpu1.op_class::No_OpClass 33619 0.05% 0.05% # Class of executed instruction +system.cpu1.op_class::IntAlu 63651336 93.16% 93.21% # Class of executed instruction +system.cpu1.op_class::IntMult 27621 0.04% 93.25% # Class of executed instruction +system.cpu1.op_class::IntDiv 22176 0.03% 93.28% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::MemRead 2828254 4.14% 97.42% # Class of executed instruction +system.cpu1.op_class::MemWrite 1762973 2.58% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 68478255 # Class of executed instruction +system.cpu1.op_class::total 68325979 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 29642945 # Number of BP lookups -system.cpu2.branchPred.condPredicted 29642945 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 342109 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 26793966 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 26087449 # Number of BTB hits +system.cpu2.branchPred.lookups 29728292 # Number of BP lookups +system.cpu2.branchPred.condPredicted 29728292 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 354491 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 26875418 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 26145153 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.363149 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 617263 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 68240 # Number of incorrect RAS predictions. -system.cpu2.numCycles 154815215 # number of cpu cycles simulated +system.cpu2.branchPred.BTBHitPct 97.282777 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 627673 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 71339 # Number of incorrect RAS predictions. +system.cpu2.numCycles 156747191 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 11226493 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 146138571 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 29642945 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 26704712 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 142088964 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 715876 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 100355 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 5095 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 9800 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 59006 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 22 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 1044 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3680756 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 177933 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 3589 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 153848066 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.868751 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 3.040918 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 11575217 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 146531331 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 29728292 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 26772826 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 143455759 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 740896 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 117693 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 8882 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 9184 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 67495 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 36 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 614 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3714591 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 185121 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 4402 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 155604677 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.852545 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 3.032784 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 97905187 63.64% 63.64% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 902052 0.59% 64.22% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 23780045 15.46% 79.68% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 607949 0.40% 80.08% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 861058 0.56% 80.64% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 871308 0.57% 81.20% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 586027 0.38% 81.58% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 774714 0.50% 82.09% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 27559726 17.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 99528214 63.96% 63.96% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 894883 0.58% 64.54% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 23827863 15.31% 79.85% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 616054 0.40% 80.25% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 865023 0.56% 80.80% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 874152 0.56% 81.36% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 593045 0.38% 81.75% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 766815 0.49% 82.24% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 27638628 17.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 153848066 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.191473 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.943955 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 10308577 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 93114688 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 23867360 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 5032797 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 358589 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 284536277 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 358589 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 12446525 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 76456474 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 4505534 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 26483485 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 12431465 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 283232358 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 203213 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 5874103 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 62488 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 4343022 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 338256341 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 618855518 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 379959971 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 144 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 325490778 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 12765563 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 164991 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 166448 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 24511654 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6973831 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3905800 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 411343 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 337090 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 281177337 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 428187 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 278961410 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 111637 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 9401758 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 14188384 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 65116 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 153848066 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.813227 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 2.402216 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 155604677 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.189658 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.934826 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 10653655 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 94438460 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 23846115 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 5077401 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 371099 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 285226302 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 371099 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 12813669 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 77065666 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 4747202 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 26484696 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 12904465 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 283889044 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 204785 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 5893747 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 54074 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 4792782 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 339006774 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 620283621 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 380802622 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 280 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 325933868 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 13072904 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 167839 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 169378 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 24708176 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6969767 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3922969 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 416514 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 341941 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 281777756 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 433047 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 279489336 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 112446 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 9646678 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 14520235 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 68066 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 155604677 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.796150 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.396491 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 90533816 58.85% 58.85% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 5362080 3.49% 62.33% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 3874219 2.52% 64.85% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 3850508 2.50% 67.35% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 22615321 14.70% 82.05% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 2805299 1.82% 83.88% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 24069627 15.65% 99.52% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 503741 0.33% 99.85% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 233455 0.15% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 92126087 59.21% 59.21% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 5408193 3.48% 62.68% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 3871909 2.49% 65.17% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 3896687 2.50% 67.67% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 22645736 14.55% 82.23% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 2817206 1.81% 84.04% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 24121295 15.50% 99.54% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 489992 0.31% 99.85% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 227572 0.15% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 153848066 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 155604677 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 1762451 85.95% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 222010 10.83% 96.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 66103 3.22% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 1782744 86.25% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 2 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 219490 10.62% 96.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 64665 3.13% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 83756 0.03% 0.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 267874850 96.03% 96.06% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 60171 0.02% 96.08% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 55540 0.02% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 52 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 7279557 2.61% 98.71% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3607484 1.29% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 84223 0.03% 0.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 268409283 96.04% 96.07% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 60791 0.02% 96.09% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 54867 0.02% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 128 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 7262488 2.60% 98.71% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3617556 1.29% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 278961410 # Type of FU issued -system.cpu2.iq.rate 1.801899 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 2050564 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.007351 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 713932890 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 291011736 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 277302749 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 197 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 156 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 76 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 280928122 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 96 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 764231 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 279489336 # Type of FU issued +system.cpu2.iq.rate 1.783058 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 2066901 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.007395 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 716762296 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 291861984 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 277802443 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 399 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 402 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 161 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 281471819 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 195 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 741069 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1280710 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 6256 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 5226 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 665708 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1314442 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 6549 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 5531 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 685228 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 750625 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 30616 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 750208 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 28435 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 358589 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 70562607 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 2840752 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 281605524 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 45396 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6973831 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3905800 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 251212 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 165628 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2346507 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 5226 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 195667 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 202777 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 398444 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 278332986 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 7126227 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 571848 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 371099 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 70840326 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 3147966 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 282210803 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 45613 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6969767 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3922969 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 254598 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 166407 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2652713 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 5531 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 201920 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 210112 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 412032 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 278837771 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 7102995 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 592219 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 0 # number of nop insts executed -system.cpu2.iew.exec_refs 10641796 # number of memory reference insts executed -system.cpu2.iew.exec_branches 28281444 # Number of branches executed -system.cpu2.iew.exec_stores 3515569 # Number of stores executed -system.cpu2.iew.exec_rate 1.797840 # Inst execution rate -system.cpu2.iew.wb_sent 278129863 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 277302825 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 216123267 # num instructions producing a value -system.cpu2.iew.wb_consumers 354504830 # num instructions consuming a value +system.cpu2.iew.exec_refs 10623704 # number of memory reference insts executed +system.cpu2.iew.exec_branches 28332312 # Number of branches executed +system.cpu2.iew.exec_stores 3520709 # Number of stores executed +system.cpu2.iew.exec_rate 1.778901 # Inst execution rate +system.cpu2.iew.wb_sent 278631802 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 277802604 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 216492114 # num instructions producing a value +system.cpu2.iew.wb_consumers 355079818 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.791186 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.609648 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.772297 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.609700 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 9397385 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 363071 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 345314 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 152442881 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.785612 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.660258 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 9642578 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 364981 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 357554 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 154160156 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.768058 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.650606 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 94319401 61.87% 61.87% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4425348 2.90% 64.77% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1302226 0.85% 65.63% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 24740165 16.23% 81.86% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 979797 0.64% 82.50% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 733746 0.48% 82.98% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 423992 0.28% 83.26% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 23324047 15.30% 98.56% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 2194159 1.44% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 95860610 62.18% 62.18% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4461430 2.89% 65.08% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1337416 0.87% 65.94% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 24820120 16.10% 82.04% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1009976 0.66% 82.70% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 732580 0.48% 83.17% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 443548 0.29% 83.46% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 23352402 15.15% 98.61% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 2142074 1.39% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 152442881 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 138052587 # Number of instructions committed -system.cpu2.commit.committedOps 272203766 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 154160156 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 138237412 # Number of instructions committed +system.cpu2.commit.committedOps 272564120 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8933213 # Number of memory references committed -system.cpu2.commit.loads 5693121 # Number of loads committed -system.cpu2.commit.membars 162094 # Number of memory barriers committed -system.cpu2.commit.branches 27859693 # Number of branches committed +system.cpu2.commit.refs 8893065 # Number of memory references committed +system.cpu2.commit.loads 5655324 # Number of loads committed +system.cpu2.commit.membars 162767 # Number of memory barriers committed +system.cpu2.commit.branches 27901240 # Number of branches committed system.cpu2.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 248852946 # Number of committed integer instructions. -system.cpu2.commit.function_calls 461863 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 49962 0.02% 0.02% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 263110099 96.66% 96.68% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 57933 0.02% 96.70% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 52599 0.02% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 16 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 5693065 2.09% 98.81% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 3240092 1.19% 100.00% # Class of committed instruction +system.cpu2.commit.int_insts 249166189 # Number of committed integer instructions. +system.cpu2.commit.function_calls 462772 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 50638 0.02% 0.02% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 263510022 96.68% 96.70% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 58397 0.02% 96.72% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 52041 0.02% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 16 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 5655265 2.07% 98.81% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 3237741 1.19% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 272203766 # Class of committed instruction -system.cpu2.commit.bw_lim_events 2194159 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 431819572 # The number of ROB reads -system.cpu2.rob.rob_writes 564614589 # The number of ROB writes -system.cpu2.timesIdled 120593 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 967149 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 4904349916 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 138052587 # Number of Instructions Simulated -system.cpu2.committedOps 272203766 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.121422 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.121422 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.891725 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.891725 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 371027158 # number of integer regfile reads -system.cpu2.int_regfile_writes 222252306 # number of integer regfile writes -system.cpu2.fp_regfile_reads 72988 # number of floating regfile reads -system.cpu2.fp_regfile_writes 72912 # number of floating regfile writes -system.cpu2.cc_regfile_reads 141449053 # number of cc regfile reads -system.cpu2.cc_regfile_writes 108603776 # number of cc regfile writes -system.cpu2.misc_regfile_reads 90794642 # number of misc regfile reads -system.cpu2.misc_regfile_writes 144161 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 3553347 # Transaction distribution -system.iobus.trans_dist::ReadResp 3553347 # Transaction distribution -system.iobus.trans_dist::WriteReq 57679 # Transaction distribution -system.iobus.trans_dist::WriteResp 10959 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.iobus.trans_dist::MessageReq 1698 # Transaction distribution -system.iobus.trans_dist::MessageResp 1698 # Transaction distribution +system.cpu2.commit.op_class_0::total 272564120 # Class of committed instruction +system.cpu2.commit.bw_lim_events 2142074 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 434194585 # The number of ROB reads +system.cpu2.rob.rob_writes 565865422 # The number of ROB writes +system.cpu2.timesIdled 127222 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1142514 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 4899644826 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 138237412 # Number of Instructions Simulated +system.cpu2.committedOps 272564120 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.133898 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.133898 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.881913 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.881913 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 371610814 # number of integer regfile reads +system.cpu2.int_regfile_writes 222643670 # number of integer regfile writes +system.cpu2.fp_regfile_reads 73073 # number of floating regfile reads +system.cpu2.fp_regfile_writes 72968 # number of floating regfile writes +system.cpu2.cc_regfile_reads 141701796 # number of cc regfile reads +system.cpu2.cc_regfile_writes 108796323 # number of cc regfile writes +system.cpu2.misc_regfile_reads 90941344 # number of misc regfile reads +system.cpu2.misc_regfile_writes 144983 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 3552121 # Transaction distribution +system.iobus.trans_dist::ReadResp 3552121 # Transaction distribution +system.iobus.trans_dist::WriteReq 57703 # Transaction distribution +system.iobus.trans_dist::WriteResp 57703 # Transaction distribution +system.iobus.trans_dist::MessageReq 1657 # Transaction distribution +system.iobus.trans_dist::MessageResp 1657 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11042 # Packet count per connected master and slave (bytes) @@ -1153,22 +1151,22 @@ system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 7082616 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1098 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 7080216 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1182 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27940 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27854 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 7126806 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95246 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95246 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3396 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3396 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 7225448 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 7124404 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95244 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95244 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3314 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3314 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 7222962 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6660 # Cumulative packet size per connected master and slave (bytes) @@ -1177,425 +1175,437 @@ system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3541308 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2196 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3540108 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2364 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13970 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13927 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 3569512 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027768 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027768 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6792 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6792 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 6604072 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 2741680 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 3568437 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027760 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027760 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6628 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6628 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 6602825 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 2786496 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 28000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 6074000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 5677000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 758000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 16000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 141309000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 140109000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 285000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 441000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer11.occupancy 86000 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 10492000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 11327000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 4000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 155889253 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 104116682 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 1032000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 301765000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 300127000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 31644993 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 23084000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1151000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1172000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47568 # number of replacements -system.iocache.tags.tagsinuse 0.079964 # Cycle average of tags in use +system.iocache.tags.replacements 47567 # number of replacements +system.iocache.tags.tagsinuse 0.081431 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47584 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47583 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5000587823009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.079964 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.004998 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.004998 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 5000591236509 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.081431 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005089 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.005089 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428607 # Number of tag accesses -system.iocache.tags.data_accesses 428607 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 903 # number of ReadReq misses -system.iocache.ReadReq_misses::total 903 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses -system.iocache.demand_misses::pc.south_bridge.ide 903 # number of demand (read+write) misses -system.iocache.demand_misses::total 903 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 903 # number of overall misses -system.iocache.overall_misses::total 903 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 128377230 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 128377230 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 5164742030 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 5164742030 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 128377230 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 128377230 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 128377230 # number of overall miss cycles -system.iocache.overall_miss_latency::total 128377230 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 903 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 903 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 903 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 903 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 903 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 903 # number of overall (read+write) accesses +system.iocache.tags.tag_accesses 428598 # Number of tag accesses +system.iocache.tags.data_accesses 428598 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 902 # number of ReadReq misses +system.iocache.ReadReq_misses::total 902 # number of ReadReq misses +system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses +system.iocache.demand_misses::pc.south_bridge.ide 902 # number of demand (read+write) misses +system.iocache.demand_misses::total 902 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 902 # number of overall misses +system.iocache.overall_misses::total 902 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 121586746 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 121586746 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 2354972936 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 2354972936 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 121586746 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 121586746 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 121586746 # number of overall miss cycles +system.iocache.overall_miss_latency::total 121586746 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 902 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 902 # number of ReadReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses) +system.iocache.demand_accesses::pc.south_bridge.ide 902 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 902 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 902 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 902 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 142167.475083 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 142167.475083 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 110546.704409 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 110546.704409 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 142167.475083 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 142167.475083 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 142167.475083 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 142167.475083 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 17612 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 134796.835920 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 134796.835920 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 50406.098801 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 50406.098801 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 134796.835920 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 134796.835920 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 134796.835920 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 134796.835920 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 552 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 2632 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 46 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.691489 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 12 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 801 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 801 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 28264 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 28264 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 801 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 801 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 801 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 801 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 86423212 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 86423212 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 3695010034 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 3695010034 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 86423212 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 86423212 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 86423212 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 86423212 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.887043 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.887043 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 0.604966 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.604966 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.887043 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.887043 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.887043 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.887043 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 107894.147316 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 107894.147316 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 130732.027809 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 130732.027809 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 107894.147316 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 107894.147316 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 107894.147316 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 107894.147316 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 746 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 746 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 19960 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 19960 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 746 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 746 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 746 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 746 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 84286746 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 84286746 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 1356972936 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 1356972936 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 84286746 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 84286746 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 84286746 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 84286746 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.827051 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.827051 # mshr miss rate for ReadReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 0.427226 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.427226 # mshr miss rate for WriteLineReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.827051 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.827051 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.827051 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.827051 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 112984.914209 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 112984.914209 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 67984.616032 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67984.616032 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 112984.914209 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 112984.914209 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 112984.914209 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 112984.914209 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 105369 # number of replacements -system.l2c.tags.tagsinuse 64830.626845 # Cycle average of tags in use -system.l2c.tags.total_refs 3705679 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 169446 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 21.869380 # Average number of references to valid blocks. +system.l2c.tags.replacements 105904 # number of replacements +system.l2c.tags.tagsinuse 64832.216142 # Cycle average of tags in use +system.l2c.tags.total_refs 4698304 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 170185 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 27.607039 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 50858.096780 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.134526 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1601.427587 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5289.246768 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000914 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 232.896636 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1549.888722 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 7.632040 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1227.720144 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 4063.582728 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.776033 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 50894.263020 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.125303 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1602.122983 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 5170.967993 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 244.936624 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1566.576743 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 6.469260 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.itb.walker 0.003420 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1245.636306 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 4101.114491 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.776585 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.024436 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.080708 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003554 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.023649 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000116 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.018734 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.062005 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.989237 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 64077 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 4057 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 8155 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 51563 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.977737 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 33969935 # Number of tag accesses -system.l2c.tags.data_accesses 33969935 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 19552 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 10769 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 287050 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 476755 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 13141 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 7558 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 168208 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 219838 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 66288 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 13297 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 401625 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 617193 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2301274 # number of ReadReq hits +system.l2c.tags.occ_percent::cpu0.inst 0.024446 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.078903 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.003737 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.023904 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000099 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.019007 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.062578 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.989261 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 64281 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 679 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3076 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 7407 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 53037 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.980850 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 41908906 # Number of tag accesses +system.l2c.tags.data_accesses 41908906 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 18995 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 10333 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 12983 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 7660 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 68713 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 15994 # number of ReadReq hits +system.l2c.ReadReq_hits::total 134678 # number of ReadReq hits system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits system.l2c.WriteReq_hits::total 2 # number of WriteReq hits -system.l2c.Writeback_hits::writebacks 1546428 # number of Writeback hits -system.l2c.Writeback_hits::total 1546428 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 105 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 47 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 96 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 248 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 55987 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 35553 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 67356 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 158896 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 19552 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 10771 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 287050 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 532742 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 13141 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 7558 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 168208 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 255391 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 66288 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 13297 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 401625 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 684549 # number of demand (read+write) hits -system.l2c.demand_hits::total 2460172 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 19552 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 10771 # number of overall hits -system.l2c.overall_hits::cpu0.inst 287050 # number of overall hits -system.l2c.overall_hits::cpu0.data 532742 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 13141 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 7558 # number of overall hits -system.l2c.overall_hits::cpu1.inst 168208 # number of overall hits -system.l2c.overall_hits::cpu1.data 255391 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 66288 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 13297 # number of overall hits -system.l2c.overall_hits::cpu2.inst 401625 # number of overall hits -system.l2c.overall_hits::cpu2.data 684549 # number of overall hits -system.l2c.overall_hits::total 2460172 # number of overall hits +system.l2c.Writeback_hits::writebacks 1548927 # number of Writeback hits +system.l2c.Writeback_hits::total 1548927 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 114 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 55 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2.data 87 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 256 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 58015 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 36167 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 65709 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 159891 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 287726 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 161212 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu2.inst 418246 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 867184 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 475648 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 219061 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu2.data 621112 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 1315821 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 18995 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 10335 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 287726 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 533663 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 12983 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 7660 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 161212 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 255228 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.dtb.walker 68713 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.itb.walker 15994 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 418246 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 686821 # number of demand (read+write) hits +system.l2c.demand_hits::total 2477576 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 18995 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 10335 # number of overall hits +system.l2c.overall_hits::cpu0.inst 287726 # number of overall hits +system.l2c.overall_hits::cpu0.data 533663 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 12983 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 7660 # number of overall hits +system.l2c.overall_hits::cpu1.inst 161212 # number of overall hits +system.l2c.overall_hits::cpu1.data 255228 # number of overall hits +system.l2c.overall_hits::cpu2.dtb.walker 68713 # number of overall hits +system.l2c.overall_hits::cpu2.itb.walker 15994 # number of overall hits +system.l2c.overall_hits::cpu2.inst 418246 # number of overall hits +system.l2c.overall_hits::cpu2.data 686821 # number of overall hits +system.l2c.overall_hits::total 2477576 # number of overall hits system.l2c.ReadReq_misses::cpu0.itb.walker 5 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6966 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 14460 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2825 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4632 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 35 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 5226 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 13983 # number of ReadReq misses -system.l2c.ReadReq_misses::total 48133 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 556 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 254 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 614 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1424 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 68944 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 26842 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 35344 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 131130 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu2.dtb.walker 39 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.itb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::total 45 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 613 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 245 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 572 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1430 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 65210 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 25360 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 40614 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 131184 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 6150 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 2338 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu2.inst 6597 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 15085 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 15362 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 3902 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu2.data 14056 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 33320 # number of ReadSharedReq misses system.l2c.demand_misses::cpu0.itb.walker 5 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 6966 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 83404 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2825 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 31474 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.dtb.walker 35 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 5226 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 49327 # number of demand (read+write) misses -system.l2c.demand_misses::total 179263 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 6150 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 80572 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2338 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 29262 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.dtb.walker 39 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.itb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 6597 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 54670 # number of demand (read+write) misses +system.l2c.demand_misses::total 179634 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.itb.walker 5 # number of overall misses -system.l2c.overall_misses::cpu0.inst 6966 # number of overall misses -system.l2c.overall_misses::cpu0.data 83404 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2825 # number of overall misses -system.l2c.overall_misses::cpu1.data 31474 # number of overall misses -system.l2c.overall_misses::cpu2.dtb.walker 35 # number of overall misses -system.l2c.overall_misses::cpu2.inst 5226 # number of overall misses -system.l2c.overall_misses::cpu2.data 49327 # number of overall misses -system.l2c.overall_misses::total 179263 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 82500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 229197000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 387947750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 3073999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 450638500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 1224001500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 2294941249 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 5739854 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2.data 7551262 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 13291116 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 2024405687 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 2802525365 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 4826931052 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 82500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 229197000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 2412353437 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.dtb.walker 3073999 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 450638500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 4026526865 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 7121872301 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 82500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 229197000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 2412353437 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.dtb.walker 3073999 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 450638500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 4026526865 # number of overall miss cycles -system.l2c.overall_miss_latency::total 7121872301 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 19552 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 10774 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 294016 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 491215 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 13142 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 7558 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 171033 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 224470 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.dtb.walker 66323 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.itb.walker 13297 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 406851 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 631176 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2349407 # number of ReadReq accesses(hits+misses) +system.l2c.overall_misses::cpu0.inst 6150 # number of overall misses +system.l2c.overall_misses::cpu0.data 80572 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2338 # number of overall misses +system.l2c.overall_misses::cpu1.data 29262 # number of overall misses +system.l2c.overall_misses::cpu2.dtb.walker 39 # number of overall misses +system.l2c.overall_misses::cpu2.itb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu2.inst 6597 # number of overall misses +system.l2c.overall_misses::cpu2.data 54670 # number of overall misses +system.l2c.overall_misses::total 179634 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 3644000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.itb.walker 97000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 3741000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 5007000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2.data 7177500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 12184500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 1902681000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 3220187500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 5122868500 # number of ReadExReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu1.inst 188281500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu2.inst 560185000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 748466500 # number of ReadCleanReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 326831000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu2.data 1213452000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 1540283000 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu1.inst 188281500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 2229512000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.dtb.walker 3644000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.itb.walker 97000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 560185000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 4433639500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 7415359000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu1.inst 188281500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 2229512000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.dtb.walker 3644000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.itb.walker 97000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 560185000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 4433639500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 7415359000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 18995 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 10338 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 12983 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 7660 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.dtb.walker 68752 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.itb.walker 15995 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 134723 # number of ReadReq accesses(hits+misses) system.l2c.WriteReq_accesses::cpu0.itb.walker 2 # number of WriteReq accesses(hits+misses) system.l2c.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1546428 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1546428 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 661 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 301 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 710 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1672 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 124931 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 62395 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 102700 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 290026 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 19552 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 10776 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 294016 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 616146 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 13142 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 7558 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 171033 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 286865 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.dtb.walker 66323 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.itb.walker 13297 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 406851 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 733876 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2639435 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 19552 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 10776 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 294016 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 616146 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 13142 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 7558 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 171033 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 286865 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.dtb.walker 66323 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.itb.walker 13297 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 406851 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 733876 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2639435 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000464 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.023693 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.029437 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000076 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.016517 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.020635 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000528 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.012845 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.022154 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.020487 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.841150 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.843854 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 0.864789 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.851675 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.551857 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.430195 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 0.344148 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.452132 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000464 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.023693 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.135364 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000076 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.016517 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.109717 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000528 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.012845 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.067214 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.067917 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000464 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.023693 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.135364 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000076 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.016517 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.109717 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000528 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.012845 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.067214 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.067917 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 82500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 81131.681416 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 83753.832038 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 87828.542857 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 86230.099502 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 87534.971036 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 47679.165001 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 22597.850394 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 12298.472313 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 9333.648876 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75419.331160 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 79292.818159 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 36810.272645 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 82500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 81131.681416 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 76645.912086 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 87828.542857 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 86230.099502 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 81629.267237 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 39728.623871 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 82500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 81131.681416 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 76645.912086 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 87828.542857 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 86230.099502 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 81629.267237 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 39728.623871 # average overall miss latency +system.l2c.Writeback_accesses::writebacks 1548927 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1548927 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 727 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 300 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 659 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1686 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 123225 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 61527 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 106323 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 291075 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 293876 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 163550 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu2.inst 424843 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 882269 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 491010 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 222963 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu2.data 635168 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 1349141 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 18995 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 10340 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 293876 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 614235 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 12983 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 7660 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 163550 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 284490 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.dtb.walker 68752 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.itb.walker 15995 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 424843 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 741491 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2657210 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 18995 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 10340 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 293876 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 614235 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 12983 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 7660 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 163550 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 284490 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.dtb.walker 68752 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.itb.walker 15995 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 424843 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 741491 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2657210 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000484 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000567 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.itb.walker 0.000063 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.000334 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.843191 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.816667 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 0.867982 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.848161 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.529195 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.412177 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 0.381987 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.450688 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.020927 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.014295 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.015528 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.017098 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.031287 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.017501 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.022130 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.024697 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000484 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.020927 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.131175 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.014295 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.102858 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000567 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.itb.walker 0.000063 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.015528 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.073730 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.067602 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000484 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.020927 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.131175 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.014295 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.102858 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000567 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.itb.walker 0.000063 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.015528 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.073730 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.067602 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 93435.897436 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 97000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 83133.333333 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 20436.734694 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 12548.076923 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 8520.629371 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75026.853312 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 79287.622495 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 39051.016130 # average ReadExReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 80531.009410 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 84915.112930 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 49616.605900 # average ReadCleanReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 83759.866735 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 86329.823563 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 46226.980792 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 80531.009410 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 76191.374479 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 93435.897436 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.itb.walker 97000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 84915.112930 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 81098.216572 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 41280.375653 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 80531.009410 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 76191.374479 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 93435.897436 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.itb.walker 97000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 84915.112930 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 81098.216572 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 41280.375653 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1604,206 +1614,218 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 97053 # number of writebacks -system.l2c.writebacks::total 97053 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu2.inst 2 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu2.inst 2 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 2 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu2.inst 2 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 2 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 2825 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 4632 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 35 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 5224 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 13983 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 26700 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 254 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 614 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 868 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 26842 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 35344 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 62186 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 2825 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 31474 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.dtb.walker 35 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 5224 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 49327 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 88886 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 2825 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 31474 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.dtb.walker 35 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 5224 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 49327 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 88886 # number of overall MSHR misses -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 186614 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu2.data 205311 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 391925 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3448 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu2.data 3872 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 7320 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 190062 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu2.data 209183 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 399245 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 70000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 193782500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 330037250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 2632999 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 385025750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 1049073500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1960621999 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5213239 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 10949612 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 16162851 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1688636313 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 2360590135 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 4049226448 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 70000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 193782500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 2018673563 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 2632999 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 385025750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 3409663635 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 6009848447 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 70000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 193782500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 2018673563 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 2632999 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 385025750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 3409663635 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 6009848447 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 27827045500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30156785500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 57983831000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 554838500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 711575000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1266413500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 28381884000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 30868360500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 59250244500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000076 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.016517 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.020635 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000528 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.012840 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.022154 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.011365 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.843854 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.864789 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.519139 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.430195 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.344148 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.214415 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000076 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.016517 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.109717 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000528 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.012840 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.067214 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.033676 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000076 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.016517 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.109717 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000528 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.012840 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.067214 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.033676 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 70000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 68595.575221 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 71251.565199 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 75228.542857 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 73703.244640 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 75024.923121 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 73431.535543 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20524.562992 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 17833.244300 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 18620.796083 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62910.226995 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 66788.992050 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 65114.759721 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 70000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 68595.575221 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 64137.814164 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 75228.542857 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73703.244640 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 69123.677398 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 67612.992451 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 68595.575221 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 64137.814164 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 75228.542857 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73703.244640 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 69123.677398 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 67612.992451 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 149115.529917 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 146883.437809 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 147946.242266 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 160916.038283 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 183774.535124 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 173007.308743 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 149329.608233 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 147566.296018 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 148405.727060 # average overall mshr uncacheable latency +system.l2c.writebacks::writebacks 97557 # number of writebacks +system.l2c.writebacks::total 97557 # number of writebacks +system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 39 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.itb.walker 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 40 # number of ReadReq MSHR misses +system.l2c.CleanEvict_mshr_misses::writebacks 51 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 51 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 245 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 572 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 817 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 25360 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 40614 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 65974 # number of ReadExReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 2338 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 6597 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::total 8935 # number of ReadCleanReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 3902 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu2.data 14056 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 17958 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 2338 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 29262 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.dtb.walker 39 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.itb.walker 1 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 6597 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 54670 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 92907 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 2338 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 29262 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.dtb.walker 39 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.itb.walker 1 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 6597 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 54670 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 92907 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 185834 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu2.data 205183 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 391017 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3059 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu2.data 4433 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 7492 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 188893 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu2.data 209616 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 398509 # number of overall MSHR uncacheable misses +system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 3254000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 87000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 3341000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5679500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 11921500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 17601000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1649081000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 2814047500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 4463128500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 164901500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 494215000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 659116500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 287811000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 1073015000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 1360826000 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 164901500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1936892000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 3254000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 87000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 494215000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 3887062500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 6486412000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 164901500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1936892000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 3254000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 87000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 494215000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 3887062500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6486412000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28249472000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30682332500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 58931804500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 512257000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 827881000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1340138000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 28761729000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 31510213500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 60271942500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000567 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.000063 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.000297 # mshr miss rate for ReadReq accesses +system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.816667 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.867982 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.484579 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.412177 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.381987 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.226656 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.014295 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.015528 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.010127 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.017501 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.022130 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.013311 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014295 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.102858 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000567 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000063 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.015528 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.073730 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.034964 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014295 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.102858 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000567 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000063 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.015528 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.073730 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.034964 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 83435.897436 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 87000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 83525 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 23181.632653 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20841.783217 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21543.451652 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65026.853312 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69287.622495 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 67649.809016 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 70531.009410 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 74915.112930 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73767.935087 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 73759.866735 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 76338.574274 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 75778.260385 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70531.009410 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66191.374479 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 83435.897436 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 87000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 74915.112930 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 71100.466435 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 69816.181773 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70531.009410 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66191.374479 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 83435.897436 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 87000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 74915.112930 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 71100.466435 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 69816.181773 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 152014.550620 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 149536.426020 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 150714.174831 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 167458.973521 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 186754.116851 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 178875.867592 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 152264.663063 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 150323.512995 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 151243.616832 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 5117226 # Transaction distribution -system.membus.trans_dist::ReadResp 5117226 # Transaction distribution -system.membus.trans_dist::WriteReq 13905 # Transaction distribution -system.membus.trans_dist::WriteResp 13905 # Transaction distribution -system.membus.trans_dist::Writeback 143720 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.membus.trans_dist::UpgradeReq 1707 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1707 # Transaction distribution -system.membus.trans_dist::ReadExReq 130847 # Transaction distribution -system.membus.trans_dist::ReadExResp 130847 # Transaction distribution -system.membus.trans_dist::MessageReq 1698 # Transaction distribution -system.membus.trans_dist::MessageResp 1698 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3396 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3396 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7126806 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3037388 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 457961 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 10622155 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141555 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 141555 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10767106 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6792 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6792 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3569512 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6074773 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17637504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 27281789 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6011648 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 6011648 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33300229 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 820 # Total snoops (count) -system.membus.snoop_fanout::samples 5455844 # Request fanout histogram -system.membus.snoop_fanout::mean 1.000311 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.017639 # Request fanout histogram +system.membus.trans_dist::ReadReq 5067078 # Transaction distribution +system.membus.trans_dist::ReadResp 5116429 # Transaction distribution +system.membus.trans_dist::WriteReq 13886 # Transaction distribution +system.membus.trans_dist::WriteResp 13886 # Transaction distribution +system.membus.trans_dist::Writeback 144224 # Transaction distribution +system.membus.trans_dist::CleanEvict 8915 # Transaction distribution +system.membus.trans_dist::UpgradeReq 1691 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1691 # Transaction distribution +system.membus.trans_dist::ReadExReq 130923 # Transaction distribution +system.membus.trans_dist::ReadExResp 130923 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 49352 # Transaction distribution +system.membus.trans_dist::MessageReq 1657 # Transaction distribution +system.membus.trans_dist::MessageResp 1657 # Transaction distribution +system.membus.trans_dist::BadAddressError 1 # Transaction distribution +system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution +system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3314 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3314 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7124404 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3037524 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 467564 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 10629494 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 142133 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 142133 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10774941 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6628 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6628 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3568437 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6075045 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17691840 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 27335322 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3025024 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 3025024 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 30366974 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 812 # Total snoops (count) +system.membus.snoop_fanout::samples 5464824 # Request fanout histogram +system.membus.snoop_fanout::mean 1.000303 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.017410 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 5454146 99.97% 99.97% # Request fanout histogram -system.membus.snoop_fanout::2 1698 0.03% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 5463167 99.97% 99.97% # Request fanout histogram +system.membus.snoop_fanout::2 1657 0.03% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 2 # Request fanout histogram -system.membus.snoop_fanout::total 5455844 # Request fanout histogram -system.membus.reqLayer0.occupancy 234105000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5464824 # Request fanout histogram +system.membus.reqLayer0.occupancy 233042000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 304102500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 304115000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 2302000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 2344000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 670380805 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 525464887 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1151000 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) +system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.membus.respLayer0.occupancy 1172000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1321113701 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1340471277 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 32422007 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 38659394 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -1817,50 +1839,54 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 7449528 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 7448995 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13907 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13907 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 1546428 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 28278 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1672 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1672 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 290026 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 290026 # Transaction distribution -system.toL2Bus.trans_dist::MessageReq 1151 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1743864 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 14988008 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 73882 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 225048 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 17030802 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 55802432 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213393597 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 274152 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 823488 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 270293669 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 74263 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 9350095 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.022573 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.148538 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 5232649 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 7464311 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13888 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13888 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 1628034 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 977588 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1686 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1686 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 291075 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 291075 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 882303 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1349887 # Transaction distribution +system.toL2Bus.trans_dist::MessageReq 1172 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 1 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 19960 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2645849 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 15085510 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 77708 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 228805 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 18037872 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 56466048 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213762586 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 290440 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 837080 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 271356154 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 159100 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 10426288 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.028740 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.167075 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 9139035 97.74% 97.74% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 211060 2.26% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 10126637 97.13% 97.13% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 299651 2.87% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 9350095 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2511915480 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 402000 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 10426288 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2853173500 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 328500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 868906655 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 883247245 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1944011740 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1934319786 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 26208491 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 28757491 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 98848126 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 101435667 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed |